Attachment #2143 for bug #12221

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Lines 109-114 Link Here

(-)kernel-source-2.6.18.orig/drivers/net/forcedeth.c (-690 / +1790 lines)
109	* 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.	109	* 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110	* 0.55: 22 Mar 2006: Add flow control (pause frame).	110	* 0.55: 22 Mar 2006: Add flow control (pause frame).
111	* 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.	111	* 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
		112	* 0.57: 14 May 2006: Moved mac address writes to nv_probe and nv_remove.
		113	* 0.58: 20 May 2006: Optimized rx and tx data paths.
		114	* 0.59: 31 May 2006: Added support for sideband management unit.
		115	* 0.60: 31 May 2006: Added support for recoverable error.
112	*	116	*
113	* Known bugs:	117	* Known bugs:
114	* We suspect that on some hardware no TX done interrupts are generated.	118	* We suspect that on some hardware no TX done interrupts are generated.
Lines 120-126 Link Here
120	* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few	124	* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
121	* superfluous timer interrupts from the nic.	125	* superfluous timer interrupts from the nic.
122	*/	126	*/
123	#define FORCEDETH_VERSION "0.56"	127	#define FORCEDETH_VERSION "0.60"
124	#define DRV_NAME "forcedeth"	128	#define DRV_NAME "forcedeth"
125		129
126	#include <linux/module.h>	130	#include <linux/module.h>
Lines 168-178 Link Here
168	#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */	172	#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
169	#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */	173	#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
170	#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */	174	#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
		175	#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
		176
		177	#define NVIDIA_ETHERNET_ID(deviceid,nv_driver_data) {\
		178	.vendor = PCI_VENDOR_ID_NVIDIA, \
		179	.device = deviceid, \
		180	.subvendor = PCI_ANY_ID, \
		181	.subdevice = PCI_ANY_ID, \
		182	.driver_data = nv_driver_data, \
		183	},
		184
		185	#define Mv_LED_Control 16
		186	#define Mv_Page_Address 22
171		187
172	enum {	188	enum {
173	NvRegIrqStatus = 0x000,	189	NvRegIrqStatus = 0x000,
174	#define NVREG_IRQSTAT_MIIEVENT 0x040	190	#define NVREG_IRQSTAT_MIIEVENT 0x040
175	#define NVREG_IRQSTAT_MASK 0x1ff	191	#define NVREG_IRQSTAT_MASK 0x81ff
176	NvRegIrqMask = 0x004,	192	NvRegIrqMask = 0x004,
177	#define NVREG_IRQ_RX_ERROR 0x0001	193	#define NVREG_IRQ_RX_ERROR 0x0001
178	#define NVREG_IRQ_RX 0x0002	194	#define NVREG_IRQ_RX 0x0002
Lines 183-197 Link Here
183	#define NVREG_IRQ_LINK 0x0040	199	#define NVREG_IRQ_LINK 0x0040
184	#define NVREG_IRQ_RX_FORCED 0x0080	200	#define NVREG_IRQ_RX_FORCED 0x0080
185	#define NVREG_IRQ_TX_FORCED 0x0100	201	#define NVREG_IRQ_TX_FORCED 0x0100
		202	#define NVREG_IRQ_RECOVER_ERROR 0x8000
186	#define NVREG_IRQMASK_THROUGHPUT 0x00df	203	#define NVREG_IRQMASK_THROUGHPUT 0x00df
187	#define NVREG_IRQMASK_CPU 0x0040	204	#define NVREG_IRQMASK_CPU 0x0040
188	#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR\|NVREG_IRQ_TX_OK\|NVREG_IRQ_TX_FORCED)	205	#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR\|NVREG_IRQ_TX_OK\|NVREG_IRQ_TX_FORCED)
189	#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR\|NVREG_IRQ_RX\|NVREG_IRQ_RX_NOBUF\|NVREG_IRQ_RX_FORCED)	206	#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR\|NVREG_IRQ_RX\|NVREG_IRQ_RX_NOBUF\|NVREG_IRQ_RX_FORCED)
190	#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER\|NVREG_IRQ_LINK)	207	#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER\|NVREG_IRQ_LINK\|NVREG_IRQ_RECOVER_ERROR)
191		208
192	#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR\|NVREG_IRQ_RX\|NVREG_IRQ_RX_NOBUF\|NVREG_IRQ_TX_ERR\| \	209	#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR\|NVREG_IRQ_RX\|NVREG_IRQ_RX_NOBUF\|NVREG_IRQ_TX_ERR\| \
193	NVREG_IRQ_TX_OK\|NVREG_IRQ_TIMER\|NVREG_IRQ_LINK\|NVREG_IRQ_RX_FORCED\| \	210	NVREG_IRQ_TX_OK\|NVREG_IRQ_TIMER\|NVREG_IRQ_LINK\|NVREG_IRQ_RX_FORCED\| \
194	NVREG_IRQ_TX_FORCED))	211	NVREG_IRQ_TX_FORCED\|NVREG_IRQ_RECOVER_ERROR))
195		212
196	NvRegUnknownSetupReg6 = 0x008,	213	NvRegUnknownSetupReg6 = 0x008,
197	#define NVREG_UNKSETUP6_VAL 3	214	#define NVREG_UNKSETUP6_VAL 3
Lines 216-221 Link Here
216	#define NVREG_MAC_RESET_ASSERT 0x0F3	233	#define NVREG_MAC_RESET_ASSERT 0x0F3
217	NvRegTransmitterControl = 0x084,	234	NvRegTransmitterControl = 0x084,
218	#define NVREG_XMITCTL_START 0x01	235	#define NVREG_XMITCTL_START 0x01
		236	#define NVREG_XMITCTL_MGMT_ST 0x40000000
		237	#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
		238	#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
		239	#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
		240	#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
		241	#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
		242	#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
		243	#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
		244	#define NVREG_XMITCTL_HOST_LOADED 0x00004000
		245	#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
219	NvRegTransmitterStatus = 0x088,	246	NvRegTransmitterStatus = 0x088,
220	#define NVREG_XMITSTAT_BUSY 0x01	247	#define NVREG_XMITSTAT_BUSY 0x01
221		248
Lines 231-236 Link Here
231	#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE	258	#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
232	NvRegReceiverControl = 0x094,	259	NvRegReceiverControl = 0x094,
233	#define NVREG_RCVCTL_START 0x01	260	#define NVREG_RCVCTL_START 0x01
		261	#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
234	NvRegReceiverStatus = 0x98,	262	NvRegReceiverStatus = 0x98,
235	#define NVREG_RCVSTAT_BUSY 0x01	263	#define NVREG_RCVSTAT_BUSY 0x01
236		264
Lines 241-247 Link Here
241	#define NVREG_RNDSEED_FORCE3 0x7400	269	#define NVREG_RNDSEED_FORCE3 0x7400
242		270
243	NvRegTxDeferral = 0xA0,	271	NvRegTxDeferral = 0xA0,
244	#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f	272	#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
245	#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f	273	#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
246	#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f	274	#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
247	NvRegRxDeferral = 0xA4,	275	NvRegRxDeferral = 0xA4,
Lines 262-268 Link Here
262	NvRegRingSizes = 0x108,	290	NvRegRingSizes = 0x108,
263	#define NVREG_RINGSZ_TXSHIFT 0	291	#define NVREG_RINGSZ_TXSHIFT 0
264	#define NVREG_RINGSZ_RXSHIFT 16	292	#define NVREG_RINGSZ_RXSHIFT 16
265	NvRegUnknownTransmitterReg = 0x10c,	293	NvRegTransmitPoll = 0x10c,
		294	#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
266	NvRegLinkSpeed = 0x110,	295	NvRegLinkSpeed = 0x110,
267	#define NVREG_LINKSPEED_FORCE 0x10000	296	#define NVREG_LINKSPEED_FORCE 0x10000
268	#define NVREG_LINKSPEED_10 1000	297	#define NVREG_LINKSPEED_10 1000
Lines 283-290 Link Here
283	#define NVREG_TXRXCTL_RESET 0x0010	312	#define NVREG_TXRXCTL_RESET 0x0010
284	#define NVREG_TXRXCTL_RXCHECK 0x0400	313	#define NVREG_TXRXCTL_RXCHECK 0x0400
285	#define NVREG_TXRXCTL_DESC_1 0	314	#define NVREG_TXRXCTL_DESC_1 0
286	#define NVREG_TXRXCTL_DESC_2 0x02100	315	#define NVREG_TXRXCTL_DESC_2 0x002100
287	#define NVREG_TXRXCTL_DESC_3 0x02200	316	#define NVREG_TXRXCTL_DESC_3 0xc02200
288	#define NVREG_TXRXCTL_VLANSTRIP 0x00040	317	#define NVREG_TXRXCTL_VLANSTRIP 0x00040
289	#define NVREG_TXRXCTL_VLANINS 0x00080	318	#define NVREG_TXRXCTL_VLANINS 0x00080
290	NvRegTxRingPhysAddrHigh = 0x148,	319	NvRegTxRingPhysAddrHigh = 0x148,
Lines 297-304 Link Here
297	#define NVREG_MIISTAT_LINKCHANGE 0x0008	326	#define NVREG_MIISTAT_LINKCHANGE 0x0008
298	#define NVREG_MIISTAT_MASK 0x000f	327	#define NVREG_MIISTAT_MASK 0x000f
299	#define NVREG_MIISTAT_MASK2 0x000f	328	#define NVREG_MIISTAT_MASK2 0x000f
300	NvRegUnknownSetupReg4 = 0x184,	329	NvRegMIIMask = 0x184,
301	#define NVREG_UNKSETUP4_VAL 8	330	#define NVREG_MII_LINKCHANGE 0x0008
302		331
303	NvRegAdapterControl = 0x188,	332	NvRegAdapterControl = 0x188,
304	#define NVREG_ADAPTCTL_START 0x02	333	#define NVREG_ADAPTCTL_START 0x02
Lines 328-333 Link Here
328	#define NVREG_WAKEUPFLAGS_ENABLE 0x1111	357	#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
329		358
330	NvRegPatternCRC = 0x204,	359	NvRegPatternCRC = 0x204,
		360	#define NV_UNKNOWN_VAL 0x01
331	NvRegPatternMask = 0x208,	361	NvRegPatternMask = 0x208,
332	NvRegPowerCap = 0x268,	362	NvRegPowerCap = 0x268,
333	#define NVREG_POWERCAP_D3SUPP (1<<30)	363	#define NVREG_POWERCAP_D3SUPP (1<<30)
Lines 368-373 Link Here
368	NvRegTxPause = 0x2e0,	398	NvRegTxPause = 0x2e0,
369	NvRegRxPause = 0x2e4,	399	NvRegRxPause = 0x2e4,
370	NvRegRxDropFrame = 0x2e8,	400	NvRegRxDropFrame = 0x2e8,
		401
371	NvRegVlanControl = 0x300,	402	NvRegVlanControl = 0x300,
372	#define NVREG_VLANCONTROL_ENABLE 0x2000	403	#define NVREG_VLANCONTROL_ENABLE 0x2000
373	NvRegMSIXMap0 = 0x3e0,	404	NvRegMSIXMap0 = 0x3e0,
Lines 409-415 Link Here
409	#define NV_TX_CARRIERLOST (1<<27)	440	#define NV_TX_CARRIERLOST (1<<27)
410	#define NV_TX_LATECOLLISION (1<<28)	441	#define NV_TX_LATECOLLISION (1<<28)
411	#define NV_TX_UNDERFLOW (1<<29)	442	#define NV_TX_UNDERFLOW (1<<29)
412	#define NV_TX_ERROR (1<<30)	443	#define NV_TX_ERROR (1<<30) /* logical OR of all errors */
413	#define NV_TX_VALID (1<<31)	444	#define NV_TX_VALID (1<<31)
414		445
415	#define NV_TX2_LASTPACKET (1<<29)	446	#define NV_TX2_LASTPACKET (1<<29)
Lines 420-426 Link Here
420	#define NV_TX2_LATECOLLISION (1<<27)	451	#define NV_TX2_LATECOLLISION (1<<27)
421	#define NV_TX2_UNDERFLOW (1<<28)	452	#define NV_TX2_UNDERFLOW (1<<28)
422	/* error and valid are the same for both */	453	/* error and valid are the same for both */
423	#define NV_TX2_ERROR (1<<30)	454	#define NV_TX2_ERROR (1<<30) /* logical OR of all errors */
424	#define NV_TX2_VALID (1<<31)	455	#define NV_TX2_VALID (1<<31)
425	#define NV_TX2_TSO (1<<28)	456	#define NV_TX2_TSO (1<<28)
426	#define NV_TX2_TSO_SHIFT 14	457	#define NV_TX2_TSO_SHIFT 14
Lines 441-447 Link Here
441	#define NV_RX_CRCERR (1<<27)	472	#define NV_RX_CRCERR (1<<27)
442	#define NV_RX_OVERFLOW (1<<28)	473	#define NV_RX_OVERFLOW (1<<28)
443	#define NV_RX_FRAMINGERR (1<<29)	474	#define NV_RX_FRAMINGERR (1<<29)
444	#define NV_RX_ERROR (1<<30)	475	#define NV_RX_ERROR (1<<30) /* logical OR of all errors */
445	#define NV_RX_AVAIL (1<<31)	476	#define NV_RX_AVAIL (1<<31)
446		477
447	#define NV_RX2_CHECKSUMMASK (0x1C000000)	478	#define NV_RX2_CHECKSUMMASK (0x1C000000)
Lines 458-464 Link Here
458	#define NV_RX2_OVERFLOW (1<<23)	489	#define NV_RX2_OVERFLOW (1<<23)
459	#define NV_RX2_FRAMINGERR (1<<24)	490	#define NV_RX2_FRAMINGERR (1<<24)
460	/* error and avail are the same for both */	491	/* error and avail are the same for both */
461	#define NV_RX2_ERROR (1<<30)	492	#define NV_RX2_ERROR (1<<30) /* logical OR of all errors */
462	#define NV_RX2_AVAIL (1<<31)	493	#define NV_RX2_AVAIL (1<<31)
463		494
464	#define NV_RX3_VLAN_TAG_PRESENT (1<<16)	495	#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
Lines 492-503 Link Here
492	#define NV_WATCHDOG_TIMEO (5*HZ)	523	#define NV_WATCHDOG_TIMEO (5*HZ)
493		524
494	#define RX_RING_DEFAULT 128	525	#define RX_RING_DEFAULT 128
495	#define TX_RING_DEFAULT 256	526	#define TX_RING_DEFAULT 64
496	#define RX_RING_MIN 128	527	#define RX_RING_MIN RX_RING_DEFAULT
497	#define TX_RING_MIN 64	528	#define TX_RING_MIN TX_RING_DEFAULT
498	#define RING_MAX_DESC_VER_1 1024	529	#define RING_MAX_DESC_VER_1 1024
499	#define RING_MAX_DESC_VER_2_3 16384	530	#define RING_MAX_DESC_VER_2_3 16384
500	/*	531	/*
501	* Difference between the get and put pointers for the tx ring.	532	* Difference between the get and put pointers for the tx ring.
502	* This is used to throttle the amount of data outstanding in the	533	* This is used to throttle the amount of data outstanding in the
503	* tx ring.	534	* tx ring.
Lines 518-524 Link Here
518	#define LINK_TIMEOUT (3*HZ)	549	#define LINK_TIMEOUT (3*HZ)
519	#define STATS_INTERVAL (10*HZ)	550	#define STATS_INTERVAL (10*HZ)
520		551
521	/*	552	/*
522	* desc_ver values:	553	* desc_ver values:
523	* The nic supports three different descriptor types:	554	* The nic supports three different descriptor types:
524	* - DESC_VER_1: Original	555	* - DESC_VER_1: Original
Lines 532-547 Link Here
532	/* PHY defines */	563	/* PHY defines */
533	#define PHY_OUI_MARVELL 0x5043	564	#define PHY_OUI_MARVELL 0x5043
534	#define PHY_OUI_CICADA 0x03f1	565	#define PHY_OUI_CICADA 0x03f1
		566	#define PHY_OUI_VITESSE 0x01c1
535	#define PHYID1_OUI_MASK 0x03ff	567	#define PHYID1_OUI_MASK 0x03ff
536	#define PHYID1_OUI_SHFT 6	568	#define PHYID1_OUI_SHFT 6
537	#define PHYID2_OUI_MASK 0xfc00	569	#define PHYID2_OUI_MASK 0xfc00
538	#define PHYID2_OUI_SHFT 10	570	#define PHYID2_OUI_SHFT 10
539	#define PHY_INIT1 0x0f000	571	#define PHYID2_MODEL_MASK 0x03f0
540	#define PHY_INIT2 0x0e00	572	#define PHY_MODEL_MARVELL_E3016 0x220
541	#define PHY_INIT3 0x01000	573	#define PHY_MARVELL_E3016_INITMASK 0x0300
542	#define PHY_INIT4 0x0200	574	#define PHY_CICADA_INIT1 0x0f000
543	#define PHY_INIT5 0x0004	575	#define PHY_CICADA_INIT2 0x0e00
544	#define PHY_INIT6 0x02000	576	#define PHY_CICADA_INIT3 0x01000
		577	#define PHY_CICADA_INIT4 0x0200
		578	#define PHY_CICADA_INIT5 0x0004
		579	#define PHY_CICADA_INIT6 0x02000
		580	#define PHY_VITESSE_INIT_REG1 0x1f
		581	#define PHY_VITESSE_INIT_REG2 0x10
		582	#define PHY_VITESSE_INIT_REG3 0x11
		583	#define PHY_VITESSE_INIT_REG4 0x12
		584	#define PHY_VITESSE_INIT_MSK1 0xc
		585	#define PHY_VITESSE_INIT_MSK2 0x0180
		586	#define PHY_VITESSE_INIT1 0x52b5
		587	#define PHY_VITESSE_INIT2 0xaf8a
		588	#define PHY_VITESSE_INIT3 0x8
		589	#define PHY_VITESSE_INIT4 0x8f8a
		590	#define PHY_VITESSE_INIT5 0xaf86
		591	#define PHY_VITESSE_INIT6 0x8f86
		592	#define PHY_VITESSE_INIT7 0xaf82
		593	#define PHY_VITESSE_INIT8 0x0100
		594	#define PHY_VITESSE_INIT9 0x8f82
		595	#define PHY_VITESSE_INIT10 0x0
		596
545	#define PHY_GIGABIT 0x0100	597	#define PHY_GIGABIT 0x0100
546		598
547	#define PHY_TIMEOUT 0x1	599	#define PHY_TIMEOUT 0x1
Lines 573-644 Link Here
573	#define NV_MSI_X_VECTOR_OTHER 0x2	625	#define NV_MSI_X_VECTOR_OTHER 0x2
574		626
575	/* statistics */	627	/* statistics */
		628	#define NV_STATS_COUNT_SW 10
		629
		630	#define NVLAN_DISABLE_ALL_FEATURES do { \
		631	msi = NV_MSI_INT_DISABLED; \
		632	msix = NV_MSIX_INT_DISABLED; \
		633	scatter_gather = NV_SCATTER_GATHER_DISABLED; \
		634	tso_offload = NV_TSO_DISABLED; \
		635	tx_checksum_offload = NV_TX_CHECKSUM_DISABLED; \
		636	rx_checksum_offload = NV_RX_CHECKSUM_DISABLED; \
		637	tx_flow_control = NV_TX_FLOW_CONTROL_DISABLED; \
		638	rx_flow_control = NV_RX_FLOW_CONTROL_DISABLED; \
		639	wol = NV_WOL_DISABLED; \
		640	tagging_8021pq = NV_8021PQ_DISABLED; \
		641	} while (0)
		642
576	struct nv_ethtool_str {	643	struct nv_ethtool_str {
577	char name[ETH_GSTRING_LEN];	644	char name[ETH_GSTRING_LEN];
578	};	645	};
579		646
580	static const struct nv_ethtool_str nv_estats_str[] = {	647	static const struct nv_ethtool_str nv_estats_str[] = {
		648	{ "tx_dropped" },
		649	{ "tx_fifo_errors" },
		650	{ "tx_carrier_errors" },
		651	{ "tx_packets" },
581	{ "tx_bytes" },	652	{ "tx_bytes" },
		653	{ "rx_crc_errors" },
		654	{ "rx_over_errors" },
		655	{ "rx_errors_total" },
		656	{ "rx_packets" },
		657	{ "rx_bytes" },
		658
		659	/* hardware counters */
582	{ "tx_zero_rexmt" },	660	{ "tx_zero_rexmt" },
583	{ "tx_one_rexmt" },	661	{ "tx_one_rexmt" },
584	{ "tx_many_rexmt" },	662	{ "tx_many_rexmt" },
585	{ "tx_late_collision" },	663	{ "tx_late_collision" },
586	{ "tx_fifo_errors" },
587	{ "tx_carrier_errors" },
588	{ "tx_excess_deferral" },	664	{ "tx_excess_deferral" },
589	{ "tx_retry_error" },	665	{ "tx_retry_error" },
590	{ "tx_deferral" },
591	{ "tx_packets" },
592	{ "tx_pause" },
593	{ "rx_frame_error" },	666	{ "rx_frame_error" },
594	{ "rx_extra_byte" },	667	{ "rx_extra_byte" },
595	{ "rx_late_collision" },	668	{ "rx_late_collision" },
596	{ "rx_runt" },	669	{ "rx_runt" },
597	{ "rx_frame_too_long" },	670	{ "rx_frame_too_long" },
598	{ "rx_over_errors" },
599	{ "rx_crc_errors" },
600	{ "rx_frame_align_error" },	671	{ "rx_frame_align_error" },
601	{ "rx_length_error" },	672	{ "rx_length_error" },
602	{ "rx_unicast" },	673	{ "rx_unicast" },
603	{ "rx_multicast" },	674	{ "rx_multicast" },
604	{ "rx_broadcast" },	675	{ "rx_broadcast" },
605	{ "rx_bytes" },	676	{ "tx_deferral" },
		677	{ "tx_pause" },
606	{ "rx_pause" },	678	{ "rx_pause" },
607	{ "rx_drop_frame" },	679	{ "rx_drop_frame" }
608	{ "rx_packets" },
609	{ "rx_errors_total" }
610	};	680	};
611		681
612	struct nv_ethtool_stats {	682	struct nv_ethtool_stats {
		683	u64 tx_dropped;
		684	u64 tx_fifo_errors;
		685	u64 tx_carrier_errors;
		686	u64 tx_packets;
613	u64 tx_bytes;	687	u64 tx_bytes;
		688	u64 rx_crc_errors;
		689	u64 rx_over_errors;
		690	u64 rx_errors_total;
		691	u64 rx_packets;
		692	u64 rx_bytes;
		693
		694	/* hardware counters */
614	u64 tx_zero_rexmt;	695	u64 tx_zero_rexmt;
615	u64 tx_one_rexmt;	696	u64 tx_one_rexmt;
616	u64 tx_many_rexmt;	697	u64 tx_many_rexmt;
617	u64 tx_late_collision;	698	u64 tx_late_collision;
618	u64 tx_fifo_errors;
619	u64 tx_carrier_errors;
620	u64 tx_excess_deferral;	699	u64 tx_excess_deferral;
621	u64 tx_retry_error;	700	u64 tx_retry_error;
622	u64 tx_deferral;
623	u64 tx_packets;
624	u64 tx_pause;
625	u64 rx_frame_error;	701	u64 rx_frame_error;
626	u64 rx_extra_byte;	702	u64 rx_extra_byte;
627	u64 rx_late_collision;	703	u64 rx_late_collision;
628	u64 rx_runt;	704	u64 rx_runt;
629	u64 rx_frame_too_long;	705	u64 rx_frame_too_long;
630	u64 rx_over_errors;
631	u64 rx_crc_errors;
632	u64 rx_frame_align_error;	706	u64 rx_frame_align_error;
633	u64 rx_length_error;	707	u64 rx_length_error;
634	u64 rx_unicast;	708	u64 rx_unicast;
635	u64 rx_multicast;	709	u64 rx_multicast;
636	u64 rx_broadcast;	710	u64 rx_broadcast;
637	u64 rx_bytes;	711	u64 tx_deferral;
		712	u64 tx_pause;
638	u64 rx_pause;	713	u64 rx_pause;
639	u64 rx_drop_frame;	714	u64 rx_drop_frame;
640	u64 rx_packets;
641	u64 rx_errors_total;
642	};	715	};
643		716
644	/* diagnostics */	717	/* diagnostics */
Lines 667-686 Link Here
667	{ 0,0 }	740	{ 0,0 }
668	};	741	};
669		742
		743	struct nv_skb_map {
		744	struct sk_buff *skb;
		745	dma_addr_t dma;
		746	unsigned int dma_len;
		747	};
		748
670	/*	749	/*
671	* SMP locking:	750	* SMP locking:
672	* All hardware access under dev->priv->lock, except the performance	751	* All hardware access under dev->priv->lock, except the performance
673	* critical parts:	752	* critical parts:
674	* - rx is (pseudo-) lockless: it relies on the single-threading provided	753	* - rx is (pseudo-) lockless: it relies on the single-threading provided
675	* by the arch code for interrupts.	754	* by the arch code for interrupts.
676	* - tx setup is lockless: it relies on netif_tx_lock. Actual submission	755	* - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
677	* needs dev->priv->lock :-(	756	* needs dev->priv->lock :-(
678	* - set_multicast_list: preparation lockless, relies on netif_tx_lock.	757	* - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
679	*/	758	*/
680		759
681	/* in dev: base, irq */	760	/* in dev: base, irq */
682	struct fe_priv {	761	struct fe_priv {
		762
		763	/* fields used in fast path are grouped together
		764	for better cache performance
		765	*/
683	spinlock_t lock;	766	spinlock_t lock;
		767	void __iomem *base;
		768	struct pci_dev *pci_dev;
		769	u32 txrxctl_bits;
		770	int stop_tx;
		771	int need_linktimer;
		772	unsigned long link_timeout;
		773	u32 irqmask;
		774	u32 msi_flags;
		775
		776	unsigned int rx_buf_sz;
		777	struct vlan_group *vlangrp;
		778	int tx_ring_size;
		779	int rx_csum;
		780
		781	/*
		782	* rx specific fields in fast path
		783	*/
		784	ring_type get_rx __attribute__((aligned(L1_CACHE_BYTES)));
		785	ring_type put_rx, first_rx, last_rx;
		786	struct nv_skb_map get_rx_ctx, put_rx_ctx;
		787	struct nv_skb_map first_rx_ctx, last_rx_ctx;
		788
		789	/*
		790	* tx specific fields in fast path
		791	*/
		792	ring_type get_tx __attribute__((aligned(L1_CACHE_BYTES)));
		793	ring_type put_tx, first_tx, last_tx;
		794	struct nv_skb_map get_tx_ctx, put_tx_ctx;
		795	struct nv_skb_map first_tx_ctx, last_tx_ctx;
		796
		797	struct nv_skb_map *rx_skb;
		798	struct nv_skb_map *tx_skb;
684		799
685	/* General data:	800	/* General data:
686	* Locking: spin_lock(&np->lock); */	801	* Locking: spin_lock(&np->lock); */
Lines 694-757 Link Here
694	int phyaddr;	809	int phyaddr;
695	int wolenabled;	810	int wolenabled;
696	unsigned int phy_oui;	811	unsigned int phy_oui;
		812	unsigned int phy_model;
697	u16 gigabit;	813	u16 gigabit;
698	int intr_test;	814	int intr_test;
		815	int recover_error;
699		816
700	/* General data: RO fields */	817	/* General data: RO fields */
701	dma_addr_t ring_addr;	818	dma_addr_t ring_addr;
702	struct pci_dev *pci_dev;
703	u32 orig_mac[2];	819	u32 orig_mac[2];
704	u32 irqmask;
705	u32 desc_ver;	820	u32 desc_ver;
706	u32 txrxctl_bits;
707	u32 vlanctl_bits;	821	u32 vlanctl_bits;
708	u32 driver_data;	822	u32 driver_data;
709	u32 register_size;	823	u32 register_size;
710		824	u32 mac_in_use;
711	void __iomem *base;
712		825
713	/* rx specific fields.	826	/* rx specific fields.
714	* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);	827	* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
715	*/	828	*/
716	ring_type rx_ring;	829	ring_type rx_ring;
717	unsigned int cur_rx, refill_rx;
718	struct sk_buff **rx_skbuff;
719	dma_addr_t *rx_dma;
720	unsigned int rx_buf_sz;
721	unsigned int pkt_limit;	830	unsigned int pkt_limit;
722	struct timer_list oom_kick;	831	struct timer_list oom_kick;
723	struct timer_list nic_poll;	832	struct timer_list nic_poll;
724	struct timer_list stats_poll;	833	struct timer_list stats_poll;
725	u32 nic_poll_irq;	834	u32 nic_poll_irq;
726	int rx_ring_size;	835	int rx_ring_size;
727		836	u32 rx_len_errors;
728	/* media detection workaround.
729	* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
730	*/
731	int need_linktimer;
732	unsigned long link_timeout;
733	/*	837	/*
734	* tx specific fields.	838	* tx specific fields.
735	*/	839	*/
736	ring_type tx_ring;	840	ring_type tx_ring;
737	unsigned int next_tx, nic_tx;
738	struct sk_buff **tx_skbuff;
739	dma_addr_t *tx_dma;
740	unsigned int *tx_dma_len;
741	u32 tx_flags;	841	u32 tx_flags;
742	int tx_ring_size;
743	int tx_limit_start;	842	int tx_limit_start;
744	int tx_limit_stop;	843	int tx_limit_stop;
745		844
746	/* vlan fields */
747	struct vlan_group *vlangrp;
748		845
749	/* msi/msi-x fields */	846	/* msi/msi-x fields */
750	u32 msi_flags;
751	struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];	847	struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
752		848
753	/* flow control */	849	/* flow control */
754	u32 pause_flags;	850	u32 pause_flags;
		851	u32 led_stats[3];
755	};	852	};
756		853
757	/*	854	/*
Lines 762-773 Link Here
762		859
763	/*	860	/*
764	* Optimization can be either throuput mode or cpu mode	861	* Optimization can be either throuput mode or cpu mode
765	*	862	*
766	* Throughput Mode: Every tx and rx packet will generate an interrupt.	863	* Throughput Mode: Every tx and rx packet will generate an interrupt.
767	* CPU Mode: Interrupts are controlled by a timer.	864	* CPU Mode: Interrupts are controlled by a timer.
768	*/	865	*/
769	enum {	866	enum {
770	NV_OPTIMIZATION_MODE_THROUGHPUT,	867	NV_OPTIMIZATION_MODE_THROUGHPUT,
771	NV_OPTIMIZATION_MODE_CPU	868	NV_OPTIMIZATION_MODE_CPU
772	};	869	};
773	static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;	870	static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
Lines 788-803 Link Here
788	NV_MSI_INT_DISABLED,	885	NV_MSI_INT_DISABLED,
789	NV_MSI_INT_ENABLED	886	NV_MSI_INT_ENABLED
790	};	887	};
		888
		889	#ifdef CONFIG_PCI_MSI
791	static int msi = NV_MSI_INT_ENABLED;	890	static int msi = NV_MSI_INT_ENABLED;
		891	#else
		892	static int msi = NV_MSI_INT_DISABLED;
		893	#endif
792		894
793	/*	895	/*
794	* MSIX interrupts	896	* MSIX interrupts
795	*/	897	*/
796	enum {	898	enum {
797	NV_MSIX_INT_DISABLED,	899	NV_MSIX_INT_DISABLED,
798	NV_MSIX_INT_ENABLED	900	NV_MSIX_INT_ENABLED
799	};	901	};
		902
		903	#ifdef CONFIG_PCI_MSI
800	static int msix = NV_MSIX_INT_ENABLED;	904	static int msix = NV_MSIX_INT_ENABLED;
		905	#else
		906	static int msix = NV_MSIX_INT_DISABLED;
		907	#endif
		908	/*
		909	* PHY Speed and Duplex
		910	*/
		911	enum {
		912	NV_SPEED_DUPLEX_AUTO,
		913	NV_SPEED_DUPLEX_10_HALF_DUPLEX,
		914	NV_SPEED_DUPLEX_10_FULL_DUPLEX,
		915	NV_SPEED_DUPLEX_100_HALF_DUPLEX,
		916	NV_SPEED_DUPLEX_100_FULL_DUPLEX,
		917	NV_SPEED_DUPLEX_1000_FULL_DUPLEX
		918	};
		919	static int speed_duplex = NV_SPEED_DUPLEX_AUTO;
		920
		921	/*
		922	* PHY autonegotiation
		923	*/
		924	static int autoneg = AUTONEG_ENABLE;
		925
		926	/*
		927	* Scatter gather
		928	*/
		929	enum {
		930	NV_SCATTER_GATHER_DISABLED,
		931	NV_SCATTER_GATHER_ENABLED
		932	};
		933	static int scatter_gather = NV_SCATTER_GATHER_ENABLED;
		934
		935	/*
		936	* TCP Segmentation Offload (TSO)
		937	*/
		938	enum {
		939	NV_TSO_DISABLED,
		940	NV_TSO_ENABLED
		941	};
		942	static int tso_offload = NV_TSO_ENABLED;
		943
		944	/*
		945	* MTU settings
		946	*/
		947	static int mtu = ETH_DATA_LEN;
		948
		949	/*
		950	* Tx checksum offload
		951	*/
		952	enum {
		953	NV_TX_CHECKSUM_DISABLED,
		954	NV_TX_CHECKSUM_ENABLED
		955	};
		956	static int tx_checksum_offload = NV_TX_CHECKSUM_ENABLED;
		957
		958	/*
		959	* Rx checksum offload
		960	*/
		961	enum {
		962	NV_RX_CHECKSUM_DISABLED,
		963	NV_RX_CHECKSUM_ENABLED
		964	};
		965	static int rx_checksum_offload = NV_RX_CHECKSUM_ENABLED;
		966
		967	/*
		968	* Tx ring size
969	*/
970	static int tx_ring_size = TX_RING_DEFAULT;
971
972	/*
973	* Rx ring size
974	*/
975	static int rx_ring_size = RX_RING_DEFAULT;
976
977	/*
978	* Tx flow control
979	*/
980	enum {
981	NV_TX_FLOW_CONTROL_DISABLED,
982	NV_TX_FLOW_CONTROL_ENABLED
983	};
984	static int tx_flow_control = NV_TX_FLOW_CONTROL_ENABLED;
985
986	/*
987	* Rx flow control
988	*/
989	enum {
990	NV_RX_FLOW_CONTROL_DISABLED,
991	NV_RX_FLOW_CONTROL_ENABLED
992	};
993	static int rx_flow_control = NV_RX_FLOW_CONTROL_ENABLED;
801		994
802	/*	995	/*
803	* DMA 64bit	996	* DMA 64bit
Lines 808-821 Link Here
808	};	1001	};
809	static int dma_64bit = NV_DMA_64BIT_ENABLED;	1002	static int dma_64bit = NV_DMA_64BIT_ENABLED;
810		1003
		1004	/*
		1005	* Wake On Lan
		1006	*/
		1007	enum {
		1008	NV_WOL_DISABLED,
		1009	NV_WOL_ENABLED
		1010	};
		1011	static int wol = NV_WOL_DISABLED;
		1012
		1013	/*
		1014	* Tagging 802.1pq
		1015	*/
		1016	enum {
		1017	NV_8021PQ_DISABLED,
		1018	NV_8021PQ_ENABLED
		1019	};
		1020	static int tagging_8021pq = NV_8021PQ_ENABLED;
		1021
		1022	static void nv_msleep(unsigned int msecs)
		1023	{
		1024	msleep(msecs);
		1025	}
		1026
811	static inline struct fe_priv get_nvpriv(struct net_device dev)	1027	static inline struct fe_priv get_nvpriv(struct net_device dev)
812	{	1028	{
813	return netdev_priv(dev);	1029	return netdev_priv(dev);
814	}	1030	}
815		1031
		1032	static void __init quirk_nforce_network_class(struct pci_dev *pdev)
		1033	{
		1034	/* Some implementations of the nVidia network controllers
		1035	* show up as bridges, when we need to see them as network
		1036	* devices.
		1037	*/
		1038
		1039	/* If this is already known as a network ctlr, do nothing. */
		1040	if ((pdev->class >> 8) == PCI_CLASS_NETWORK_ETHERNET)
		1041	return;
		1042
		1043	if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_OTHER) {
		1044	char c;
		1045
		1046	/* Clearing bit 6 of the register at 0xf8
		1047	* selects Ethernet device class
		1048	*/
		1049	pci_read_config_byte(pdev, 0xf8, &c);
		1050	c &= 0xbf;
		1051	pci_write_config_byte(pdev, 0xf8, c);
		1052
		1053	/* sysfs needs pdev->class to be set correctly */
		1054	pdev->class &= 0x0000ff;
		1055	pdev->class \|= (PCI_CLASS_NETWORK_ETHERNET << 8);
		1056	}
		1057	}
		1058
816	static inline u8 __iomem get_hwbase(struct net_device dev)	1059	static inline u8 __iomem get_hwbase(struct net_device dev)
817	{	1060	{
818	return ((struct fe_priv *)netdev_priv(dev))->base;	1061	return ((struct fe_priv *)get_nvpriv(dev))->base;
819	}	1062	}
820		1063
821	static inline void pci_push(u8 __iomem *base)	1064	static inline void pci_push(u8 __iomem *base)
Lines 893-908 Link Here
893	pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),	1136	pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
894	np->rx_ring.ex, np->ring_addr);	1137	np->rx_ring.ex, np->ring_addr);
895	}	1138	}
896	if (np->rx_skbuff)	1139	if (np->rx_skb)
897	kfree(np->rx_skbuff);	1140	kfree(np->rx_skb);
898	if (np->rx_dma)	1141	if (np->tx_skb)
899	kfree(np->rx_dma);	1142	kfree(np->tx_skb);
900	if (np->tx_skbuff)
901	kfree(np->tx_skbuff);
902	if (np->tx_dma)
903	kfree(np->tx_dma);
904	if (np->tx_dma_len)
905	kfree(np->tx_dma_len);
906	}	1143	}
907		1144
908	static int using_multi_irqs(struct net_device *dev)	1145	static int using_multi_irqs(struct net_device *dev)
Lines 910-916 Link Here
910	struct fe_priv *np = get_nvpriv(dev);	1147	struct fe_priv *np = get_nvpriv(dev);
911		1148
912	if (!(np->msi_flags & NV_MSI_X_ENABLED) \|\|	1149	if (!(np->msi_flags & NV_MSI_X_ENABLED) \|\|
913	((np->msi_flags & NV_MSI_X_ENABLED) &&	1150	((np->msi_flags & NV_MSI_X_ENABLED) &&
914	((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))	1151	((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
915	return 0;	1152	return 0;
916	else	1153	else
Lines 921-926 Link Here
921	{	1158	{
922	struct fe_priv *np = get_nvpriv(dev);	1159	struct fe_priv *np = get_nvpriv(dev);
923		1160
		1161	dprintk(KERN_DEBUG "%s: nv_enable_irq: begin\n",dev->name);
		1162	/* modify network device class id */
924	if (!using_multi_irqs(dev)) {	1163	if (!using_multi_irqs(dev)) {
925	if (np->msi_flags & NV_MSI_X_ENABLED)	1164	if (np->msi_flags & NV_MSI_X_ENABLED)
926	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);	1165	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Lines 937-942 Link Here
937	{	1176	{
938	struct fe_priv *np = get_nvpriv(dev);	1177	struct fe_priv *np = get_nvpriv(dev);
939		1178
		1179	dprintk(KERN_DEBUG "%s: nv_disable_irq: begin\n",dev->name);
940	if (!using_multi_irqs(dev)) {	1180	if (!using_multi_irqs(dev)) {
941	if (np->msi_flags & NV_MSI_X_ENABLED)	1181	if (np->msi_flags & NV_MSI_X_ENABLED)
942	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);	1182	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Lines 1020-1048 Link Here
1020	return retval;	1260	return retval;
1021	}	1261	}
1022		1262
1023	static int phy_reset(struct net_device *dev)	1263	static void nv_save_LED_stats(struct net_device *dev)
		1264	{
		1265	struct fe_priv *np = get_nvpriv(dev);
		1266	u32 reg=0;
		1267	u32 value=0;
		1268	int i=0;
		1269
		1270	reg = Mv_Page_Address;
		1271	value = 3;
		1272	mii_rw(dev,np->phyaddr,reg,value);
		1273	udelay(5);
		1274
		1275	reg = Mv_LED_Control;
		1276	for(i=0;i<3;i++){
		1277	np->led_stats[i]=mii_rw(dev,np->phyaddr,reg+i,MII_READ);
		1278	dprintk(KERN_DEBUG "%s: save LED reg%d: value=0x%x\n",dev->name,reg+i,np->led_stats[i]);
		1279	}
		1280
		1281	reg = Mv_Page_Address;
		1282	value = 0;
		1283	mii_rw(dev,np->phyaddr,reg,value);
		1284	udelay(5);
		1285	}
		1286
		1287	static void nv_restore_LED_stats(struct net_device *dev)
		1288	{
		1289
		1290	struct fe_priv *np = get_nvpriv(dev);
		1291	u32 reg=0;
		1292	u32 value=0;
		1293	int i=0;
		1294
		1295	reg = Mv_Page_Address;
		1296	value = 3;
		1297	mii_rw(dev,np->phyaddr,reg,value);
		1298	udelay(5);
		1299
		1300	reg = Mv_LED_Control;
		1301	for(i=0;i<3;i++){
		1302	mii_rw(dev,np->phyaddr,reg+i,np->led_stats[i]);
		1303	udelay(1);
		1304	dprintk(KERN_DEBUG "%s: restore LED reg%d: value=0x%x\n",dev->name,reg+i,np->led_stats[i]);
		1305	}
		1306
		1307	reg = Mv_Page_Address;
		1308	value = 0;
		1309	mii_rw(dev,np->phyaddr,reg,value);
		1310	udelay(5);
		1311	}
		1312
		1313	static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1024	{	1314	{
1025	struct fe_priv *np = netdev_priv(dev);	1315	struct fe_priv *np = get_nvpriv(dev);
1026	u32 miicontrol;	1316	u32 miicontrol;
1027	unsigned int tries = 0;	1317	unsigned int tries = 0;
1028		1318
1029	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);	1319	dprintk(KERN_DEBUG "%s: phy_reset: begin\n",dev->name);
1030	miicontrol \|= BMCR_RESET;	1320	/**/
		1321	nv_save_LED_stats(dev);
		1322	miicontrol = BMCR_RESET \| bmcr_setup;
1031	if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {	1323	if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1032	return -1;	1324	return -1;
1033	}	1325	}
1034		1326
1035	/* wait for 500ms */	1327	/* wait for 500ms */
1036	msleep(500);	1328	nv_msleep(500);
1037		1329
1038	/* must wait till reset is deasserted */	1330	/* must wait till reset is deasserted */
1039	while (miicontrol & BMCR_RESET) {	1331	while (miicontrol & BMCR_RESET) {
1040	msleep(10);	1332	nv_msleep(10);
1041	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);	1333	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1042	/* FIXME: 100 tries seem excessive */	1334	/* FIXME: 100 tries seem excessive */
1043	if (tries++ > 100)	1335	if (tries++ > 100)
1044	return -1;	1336	return -1;
1045	}	1337	}
		1338	nv_restore_LED_stats(dev);
		1339
1046	return 0;	1340	return 0;
1047	}	1341	}
1048		1342
Lines 1052-1060 Link Here
1052	u8 __iomem *base = get_hwbase(dev);	1346	u8 __iomem *base = get_hwbase(dev);
1053	u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;	1347	u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1054		1348
		1349	dprintk(KERN_DEBUG "%s: phy_init: begin\n",dev->name);
		1350	/* phy errata for E3016 phy */
		1351	if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
		1352	reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
		1353	reg &= ~PHY_MARVELL_E3016_INITMASK;
		1354	if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
		1355	printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
		1356	return PHY_ERROR;
		1357	}
		1358	}
		1359
1055	/* set advertise register */	1360	/* set advertise register */
1056	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);	1361	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1057	reg \|= (ADVERTISE_10HALF\|ADVERTISE_10FULL\|ADVERTISE_100HALF\|ADVERTISE_100FULL\|ADVERTISE_PAUSE_ASYM\|ADVERTISE_PAUSE_CAP);	1362	reg &= ~(ADVERTISE_ALL \| ADVERTISE_100BASE4 \| ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM);
		1363	if (speed_duplex == NV_SPEED_DUPLEX_AUTO)
		1364	reg \|= (ADVERTISE_10HALF\|ADVERTISE_10FULL\|ADVERTISE_100HALF\|ADVERTISE_100FULL);
		1365	if (speed_duplex == NV_SPEED_DUPLEX_10_HALF_DUPLEX)
		1366	reg \|= ADVERTISE_10HALF;
		1367	if (speed_duplex == NV_SPEED_DUPLEX_10_FULL_DUPLEX)
		1368	reg \|= ADVERTISE_10FULL;
		1369	if (speed_duplex == NV_SPEED_DUPLEX_100_HALF_DUPLEX)
		1370	reg \|= ADVERTISE_100HALF;
		1371	if (speed_duplex == NV_SPEED_DUPLEX_100_FULL_DUPLEX)
		1372	reg \|= ADVERTISE_100FULL;
		1373	if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
		1374	reg \|= ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM;
		1375	if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
		1376	reg \|= ADVERTISE_PAUSE_ASYM;
		1377	np->fixed_mode = reg;
		1378
1058	if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {	1379	if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1059	printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));	1380	printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1060	return PHY_ERROR;	1381	return PHY_ERROR;
Lines 1069-1079 Link Here
1069	np->gigabit = PHY_GIGABIT;	1390	np->gigabit = PHY_GIGABIT;
1070	mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);	1391	mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1071	mii_control_1000 &= ~ADVERTISE_1000HALF;	1392	mii_control_1000 &= ~ADVERTISE_1000HALF;
1072	if (phyinterface & PHY_RGMII)	1393	if (phyinterface & PHY_RGMII &&
		1394	(speed_duplex == NV_SPEED_DUPLEX_AUTO \|\|
		1395	(speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX && autoneg == AUTONEG_ENABLE)))
1073	mii_control_1000 \|= ADVERTISE_1000FULL;	1396	mii_control_1000 \|= ADVERTISE_1000FULL;
1074	else	1397	else {
		1398	if (speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX && autoneg == AUTONEG_DISABLE)
		1399	printk(KERN_INFO "%s: 1000mpbs full only allowed with autoneg\n", pci_name(np->pci_dev));
1075	mii_control_1000 &= ~ADVERTISE_1000FULL;	1400	mii_control_1000 &= ~ADVERTISE_1000FULL;
1076		1401	}
1077	if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {	1402	if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1078	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));	1403	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1079	return PHY_ERROR;	1404	return PHY_ERROR;
Lines 1082-1089 Link Here
1082	else	1407	else
1083	np->gigabit = 0;	1408	np->gigabit = 0;
1084		1409
1085	/* reset the phy */	1410	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1086	if (phy_reset(dev)) {	1411	if (autoneg == AUTONEG_DISABLE){
		1412	np->pause_flags &= ~(NV_PAUSEFRAME_RX_ENABLE \| NV_PAUSEFRAME_TX_ENABLE);
		1413	if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)
		1414	np->pause_flags \|= NV_PAUSEFRAME_RX_ENABLE;
		1415	if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
		1416	np->pause_flags \|= NV_PAUSEFRAME_TX_ENABLE;
		1417	mii_control &= ~(BMCR_ANENABLE\|BMCR_SPEED100\|BMCR_SPEED1000\|BMCR_FULLDPLX);
		1418	if (reg & (ADVERTISE_10FULL\|ADVERTISE_100FULL))
		1419	mii_control \|= BMCR_FULLDPLX;
		1420	if (reg & (ADVERTISE_100HALF\|ADVERTISE_100FULL))
		1421	mii_control \|= BMCR_SPEED100;
		1422	} else {
		1423	mii_control \|= BMCR_ANENABLE;
		1424	}
		1425
		1426	/* reset the phy and setup BMCR
		1427	* (certain phys need reset at same time new values are set) */
		1428	if (phy_reset(dev, mii_control)) {
1087	printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));	1429	printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1088	return PHY_ERROR;	1430	return PHY_ERROR;
1089	}	1431	}
Lines 1091-1104 Link Here
1091	/* phy vendor specific configuration */	1433	/* phy vendor specific configuration */
1092	if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {	1434	if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1093	phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);	1435	phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1094	phy_reserved &= ~(PHY_INIT1 \| PHY_INIT2);	1436	phy_reserved &= ~(PHY_CICADA_INIT1 \| PHY_CICADA_INIT2);
1095	phy_reserved \|= (PHY_INIT3 \| PHY_INIT4);	1437	phy_reserved \|= (PHY_CICADA_INIT3 \| PHY_CICADA_INIT4);
1096	if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {	1438	if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1097	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));	1439	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1098	return PHY_ERROR;	1440	return PHY_ERROR;
1099	}	1441	}
1100	phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);	1442	phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1101	phy_reserved \|= PHY_INIT5;	1443	phy_reserved \|= PHY_CICADA_INIT5;
1102	if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {	1444	if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1103	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));	1445	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1104	return PHY_ERROR;	1446	return PHY_ERROR;
Lines 1106-1125 Link Here
1106	}	1448	}
1107	if (np->phy_oui == PHY_OUI_CICADA) {	1449	if (np->phy_oui == PHY_OUI_CICADA) {
1108	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);	1450	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1109	phy_reserved \|= PHY_INIT6;	1451	phy_reserved \|= PHY_CICADA_INIT6;
1110	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {	1452	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1111	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));	1453	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1112	return PHY_ERROR;	1454	return PHY_ERROR;
1113	}	1455	}
1114	}	1456	}
		1457	if (np->phy_oui == PHY_OUI_VITESSE) {
		1458	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
		1459	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1460	return PHY_ERROR;
		1461	}
		1462	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
		1463	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1464	return PHY_ERROR;
		1465	}
		1466	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
		1467	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
		1468	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1469	return PHY_ERROR;
		1470	}
		1471	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
		1472	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
		1473	phy_reserved \|= PHY_VITESSE_INIT3;
		1474	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
		1475	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1476	return PHY_ERROR;
		1477	}
		1478	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
		1479	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1480	return PHY_ERROR;
		1481	}
		1482	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
		1483	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1484	return PHY_ERROR;
		1485	}
		1486	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
		1487	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
		1488	phy_reserved \|= PHY_VITESSE_INIT3;
		1489	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
		1490	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1491	return PHY_ERROR;
		1492	}
		1493	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
		1494	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
		1495	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1496	return PHY_ERROR;
		1497	}
		1498	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
		1499	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1500	return PHY_ERROR;
		1501	}
		1502	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
		1503	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1504	return PHY_ERROR;
		1505	}
		1506	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
		1507	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
		1508	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1509	return PHY_ERROR;
		1510	}
		1511	phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
		1512	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
		1513	phy_reserved \|= PHY_VITESSE_INIT8;
		1514	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
		1515	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1516	return PHY_ERROR;
		1517	}
		1518	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
		1519	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
		1520	return PHY_ERROR;
1521	}
1522	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1523	printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1524	return PHY_ERROR;
1525	}
1526	}
1115	/* some phys clear out pause advertisment on reset, set it back */	1527	/* some phys clear out pause advertisment on reset, set it back */
1116	mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);	1528	mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1117		1529
1118	/* restart auto negotiation */	1530	/* restart auto negotiation */
1119	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);	1531	if (autoneg == AUTONEG_ENABLE) {
1120	mii_control \|= (BMCR_ANRESTART \| BMCR_ANENABLE);	1532	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1121	if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {	1533	mii_control \|= (BMCR_ANRESTART \| BMCR_ANENABLE);
1122	return PHY_ERROR;	1534	if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
		1535	return PHY_ERROR;
		1536	}
1123	}	1537	}
1124		1538
1125	return 0;	1539	return 0;
Lines 1127-1144 Link Here
1127		1541
1128	static void nv_start_rx(struct net_device *dev)	1542	static void nv_start_rx(struct net_device *dev)
1129	{	1543	{
1130	struct fe_priv *np = netdev_priv(dev);	1544	struct fe_priv *np = get_nvpriv(dev);
1131	u8 __iomem *base = get_hwbase(dev);	1545	u8 __iomem *base = get_hwbase(dev);
		1546	u32 rx_ctrl = readl(base + NvRegReceiverControl);
1132		1547
1133	dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);	1548	dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1134	/* Already running? Stop it. */	1549	/* Already running? Stop it. */
1135	if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {	1550	if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1136	writel(0, base + NvRegReceiverControl);	1551	rx_ctrl &= ~NVREG_RCVCTL_START;
		1552	writel(rx_ctrl, base + NvRegReceiverControl);
1137	pci_push(base);	1553	pci_push(base);
1138	}	1554	}
1139	writel(np->linkspeed, base + NvRegLinkSpeed);	1555	writel(np->linkspeed, base + NvRegLinkSpeed);
1140	pci_push(base);	1556	pci_push(base);
1141	writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);	1557	rx_ctrl \|= NVREG_RCVCTL_START;
		1558	if (np->mac_in_use)
		1559	rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
		1560	writel(rx_ctrl, base + NvRegReceiverControl);
1142	dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",	1561	dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1143	dev->name, np->duplex, np->linkspeed);	1562	dev->name, np->duplex, np->linkspeed);
1144	pci_push(base);	1563	pci_push(base);
Lines 1146-1189 Link Here
1146		1565
1147	static void nv_stop_rx(struct net_device *dev)	1566	static void nv_stop_rx(struct net_device *dev)
1148	{	1567	{
		1568	struct fe_priv *np = get_nvpriv(dev);
1149	u8 __iomem *base = get_hwbase(dev);	1569	u8 __iomem *base = get_hwbase(dev);
		1570	u32 rx_ctrl = readl(base + NvRegReceiverControl);
1150		1571
1151	dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);	1572	dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1152	writel(0, base + NvRegReceiverControl);	1573	if (!np->mac_in_use)
		1574	rx_ctrl &= ~NVREG_RCVCTL_START;
		1575	else
		1576	rx_ctrl \|= NVREG_RCVCTL_RX_PATH_EN;
		1577	writel(rx_ctrl, base + NvRegReceiverControl);
1153	reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,	1578	reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1154	NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,	1579	NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1155	KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");	1580	KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1156		1581
1157	udelay(NV_RXSTOP_DELAY2);	1582	udelay(NV_RXSTOP_DELAY2);
		1583	if (!np->mac_in_use)
1158	writel(0, base + NvRegLinkSpeed);	1584	writel(0, base + NvRegLinkSpeed);
1159	}	1585	}
1160		1586
1161	static void nv_start_tx(struct net_device *dev)	1587	static void nv_start_tx(struct net_device *dev)
1162	{	1588	{
		1589	struct fe_priv *np = get_nvpriv(dev);
1163	u8 __iomem *base = get_hwbase(dev);	1590	u8 __iomem *base = get_hwbase(dev);
		1591	u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1164		1592
1165	dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);	1593	dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1166	writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);	1594	tx_ctrl \|= NVREG_XMITCTL_START;
		1595	if (np->mac_in_use)
		1596	tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
		1597	writel(tx_ctrl, base + NvRegTransmitterControl);
1167	pci_push(base);	1598	pci_push(base);
1168	}	1599	}
1169		1600
1170	static void nv_stop_tx(struct net_device *dev)	1601	static void nv_stop_tx(struct net_device *dev)
1171	{	1602	{
		1603	struct fe_priv *np = get_nvpriv(dev);
1172	u8 __iomem *base = get_hwbase(dev);	1604	u8 __iomem *base = get_hwbase(dev);
		1605	u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1173		1606
1174	dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);	1607	dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1175	writel(0, base + NvRegTransmitterControl);	1608	if (!np->mac_in_use)
		1609	tx_ctrl &= ~NVREG_XMITCTL_START;
		1610	else
		1611	tx_ctrl \|= NVREG_XMITCTL_TX_PATH_EN;
		1612	writel(tx_ctrl, base + NvRegTransmitterControl);
1176	reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,	1613	reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1177	NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,	1614	NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1178	KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");	1615	KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1179		1616
1180	udelay(NV_TXSTOP_DELAY2);	1617	udelay(NV_TXSTOP_DELAY2);
1181	writel(0, base + NvRegUnknownTransmitterReg);	1618	if (!np->mac_in_use)
		1619	writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1182	}	1620	}
1183		1621
1184	static void nv_txrx_reset(struct net_device *dev)	1622	static void nv_txrx_reset(struct net_device *dev)
1185	{	1623	{
1186	struct fe_priv *np = netdev_priv(dev);	1624	struct fe_priv *np = get_nvpriv(dev);
1187	u8 __iomem *base = get_hwbase(dev);	1625	u8 __iomem *base = get_hwbase(dev);
1188		1626
1189	dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);	1627	dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Lines 1196-1202 Link Here
1196		1634
1197	static void nv_mac_reset(struct net_device *dev)	1635	static void nv_mac_reset(struct net_device *dev)
1198	{	1636	{
1199	struct fe_priv *np = netdev_priv(dev);	1637	struct fe_priv *np = get_nvpriv(dev);
1200	u8 __iomem *base = get_hwbase(dev);	1638	u8 __iomem *base = get_hwbase(dev);
1201		1639
1202	dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);	1640	dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
Lines 1213-1286 Link Here
1213	}	1651	}
1214		1652
1215	/*	1653	/*
1216	* nv_get_stats: dev->get_stats function
1217	* Get latest stats value from the nic.
1218	* Called with read_lock(&dev_base_lock) held for read -
1219	* only synchronized against unregister_netdevice.
1220	*/
1221	static struct net_device_stats nv_get_stats(struct net_device dev)
1222	{
1223	struct fe_priv *np = netdev_priv(dev);
1224
1225	/* It seems that the nic always generates interrupts and doesn't
1226	* accumulate errors internally. Thus the current values in np->stats
1227	* are already up to date.
1228	*/
1229	return &np->stats;
1230	}
1231
1232	/*
1233	* nv_alloc_rx: fill rx ring entries.	1654	* nv_alloc_rx: fill rx ring entries.
1234	* Return 1 if the allocations for the skbs failed and the	1655	* Return 1 if the allocations for the skbs failed and the
1235	* rx engine is without Available descriptors	1656	* rx engine is without Available descriptors
1236	*/	1657	*/
1237	static int nv_alloc_rx(struct net_device *dev)	1658	static inline int nv_alloc_rx(struct net_device *dev)
1238	{	1659	{
1239	struct fe_priv *np = netdev_priv(dev);	1660	struct fe_priv *np = get_nvpriv(dev);
1240	unsigned int refill_rx = np->refill_rx;	1661	struct ring_desc* less_rx;
1241	int nr;	1662	struct sk_buff *skb;
1242
1243	while (np->cur_rx != refill_rx) {
1244	struct sk_buff *skb;
1245
1246	nr = refill_rx % np->rx_ring_size;
1247	if (np->rx_skbuff[nr] == NULL) {
1248
1249	skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1250	if (!skb)
1251	break;
1252		1663
		1664	less_rx = np->get_rx.orig;
		1665	if (less_rx-- == np->first_rx.orig)
		1666	less_rx = np->last_rx.orig;
		1667
		1668	while (np->put_rx.orig != less_rx) {
		1669	skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
		1670	if (skb) {
1253	skb->dev = dev;	1671	skb->dev = dev;
1254	np->rx_skbuff[nr] = skb;	1672	np->put_rx_ctx->skb = skb;
1255	} else {	1673	np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1256	skb = np->rx_skbuff[nr];	1674	skb->end-skb->data, PCI_DMA_FROMDEVICE);
1257	}	1675	np->put_rx_ctx->dma_len = skb->end-skb->data;
1258	np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,	1676	np->put_rx.orig->PacketBuffer = cpu_to_le32(np->put_rx_ctx->dma);
1259	skb->end-skb->data, PCI_DMA_FROMDEVICE);
1260	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1261	np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1262	wmb();	1677	wmb();
1263	np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz \| NV_RX_AVAIL);	1678	np->put_rx.orig->FlagLen = cpu_to_le32(np->rx_buf_sz \| NV_RX_AVAIL);
		1679	if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
		1680	np->put_rx.orig = np->first_rx.orig;
		1681	if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
		1682	np->put_rx_ctx = np->first_rx_ctx;
1264	} else {	1683	} else {
1265	np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;	1684	return 1;
1266	np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;	1685	}
1267	wmb();	1686	}
1268	np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz \| NV_RX2_AVAIL);	1687	return 0;
		1688	}
		1689
		1690	static inline int nv_alloc_rx_optimized(struct net_device *dev)
		1691	{
		1692	struct fe_priv *np = get_nvpriv(dev);
		1693	struct ring_desc_ex* less_rx;
		1694	struct sk_buff *skb;
		1695
		1696	less_rx = np->get_rx.ex;
		1697	if (less_rx-- == np->first_rx.ex)
		1698	less_rx = np->last_rx.ex;
		1699
		1700	while (np->put_rx.ex != less_rx) {
		1701	skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
		1702	if (skb) {
		1703	skb->dev = dev;
		1704	np->put_rx_ctx->skb = skb;
		1705	np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
		1706	skb->end-skb->data, PCI_DMA_FROMDEVICE);
		1707	np->put_rx_ctx->dma_len = skb->end-skb->data;
		1708	np->put_rx.ex->PacketBufferHigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
		1709	np->put_rx.ex->PacketBufferLow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
		1710	wmb();
		1711	np->put_rx.ex->FlagLen = cpu_to_le32(np->rx_buf_sz \| NV_RX2_AVAIL);
		1712	if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
		1713	np->put_rx.ex = np->first_rx.ex;
		1714	if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
		1715	np->put_rx_ctx = np->first_rx_ctx;
		1716	} else {
		1717	return 1;
1269	}	1718	}
1270	dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1271	dev->name, refill_rx);
1272	refill_rx++;
1273	}	1719	}
1274	np->refill_rx = refill_rx;
1275	if (np->cur_rx - refill_rx == np->rx_ring_size)
1276	return 1;
1277	return 0;	1720	return 0;
		1721
1278	}	1722	}
1279		1723
1280	static void nv_do_rx_refill(unsigned long data)	1724	static void nv_do_rx_refill(unsigned long data)
1281	{	1725	{
1282	struct net_device dev = (struct net_device ) data;	1726	struct net_device dev = (struct net_device ) data;
1283	struct fe_priv *np = netdev_priv(dev);	1727	struct fe_priv *np = get_nvpriv(dev);
		1728	int retcode;
1284		1729
1285	if (!using_multi_irqs(dev)) {	1730	if (!using_multi_irqs(dev)) {
1286	if (np->msi_flags & NV_MSI_X_ENABLED)	1731	if (np->msi_flags & NV_MSI_X_ENABLED)
Lines 1290-1296 Link Here
1290	} else {	1735	} else {
1291	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);	1736	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1292	}	1737	}
1293	if (nv_alloc_rx(dev)) {	1738
		1739	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		1740	retcode = nv_alloc_rx(dev);
		1741	else
		1742	retcode = nv_alloc_rx_optimized(dev);
		1743	if (retcode) {
1294	spin_lock_irq(&np->lock);	1744	spin_lock_irq(&np->lock);
1295	if (!np->in_shutdown)	1745	if (!np->in_shutdown)
1296	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	1746	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Lines 1306-1365 Link Here
1306	}	1756	}
1307	}	1757	}
1308		1758
1309	static void nv_init_rx(struct net_device *dev)	1759	static void nv_init_rx(struct net_device *dev)
1310	{	1760	{
1311	struct fe_priv *np = netdev_priv(dev);	1761	struct fe_priv *np = get_nvpriv(dev);
1312	int i;	1762	int i;
1313		1763
1314	np->cur_rx = np->rx_ring_size;	1764	np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1315	np->refill_rx = 0;
1316	for (i = 0; i < np->rx_ring_size; i++)
1317	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)	1765	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		1766	np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
		1767	else
		1768	np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
		1769	np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
		1770	np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
		1771
		1772	for (i = 0; i < np->rx_ring_size; i++) {
		1773	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1318	np->rx_ring.orig[i].FlagLen = 0;	1774	np->rx_ring.orig[i].FlagLen = 0;
1319	else	1775	np->rx_ring.orig[i].PacketBuffer = 0;
		1776	} else {
1320	np->rx_ring.ex[i].FlagLen = 0;	1777	np->rx_ring.ex[i].FlagLen = 0;
		1778	np->rx_ring.ex[i].TxVlan = 0;
		1779	np->rx_ring.ex[i].PacketBufferHigh = 0;
		1780	np->rx_ring.ex[i].PacketBufferLow = 0;
		1781	}
		1782	np->rx_skb[i].skb = NULL;
		1783	np->rx_skb[i].dma = 0;
		1784	}
1321	}	1785	}
1322		1786
1323	static void nv_init_tx(struct net_device *dev)	1787	static void nv_init_tx(struct net_device *dev)
1324	{	1788	{
1325	struct fe_priv *np = netdev_priv(dev);	1789	struct fe_priv *np = get_nvpriv(dev);
1326	int i;	1790	int i;
1327		1791
1328	np->next_tx = np->nic_tx = 0;	1792	np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
		1793	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		1794	np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
		1795	else
		1796	np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
		1797	np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
		1798	np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
		1799
1329	for (i = 0; i < np->tx_ring_size; i++) {	1800	for (i = 0; i < np->tx_ring_size; i++) {
1330	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)	1801	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1331	np->tx_ring.orig[i].FlagLen = 0;	1802	np->tx_ring.orig[i].FlagLen = 0;
1332	else	1803	np->tx_ring.orig[i].PacketBuffer = 0;
		1804	} else {
1333	np->tx_ring.ex[i].FlagLen = 0;	1805	np->tx_ring.ex[i].FlagLen = 0;
1334	np->tx_skbuff[i] = NULL;	1806	np->tx_ring.ex[i].TxVlan = 0;
1335	np->tx_dma[i] = 0;	1807	np->tx_ring.ex[i].PacketBufferHigh = 0;
		1808	np->tx_ring.ex[i].PacketBufferLow = 0;
		1809	}
		1810	np->tx_skb[i].skb = NULL;
		1811	np->tx_skb[i].dma = 0;
1336	}	1812	}
1337	}	1813	}
1338		1814
1339	static int nv_init_ring(struct net_device *dev)	1815	static int nv_init_ring(struct net_device *dev)
1340	{	1816	{
		1817	struct fe_priv *np = get_nvpriv(dev);
1341	nv_init_tx(dev);	1818	nv_init_tx(dev);
1342	nv_init_rx(dev);	1819	nv_init_rx(dev);
1343	return nv_alloc_rx(dev);	1820	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		1821	return nv_alloc_rx(dev);
		1822	else
		1823	return nv_alloc_rx_optimized(dev);
1344	}	1824	}
1345		1825
1346	static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)	1826	static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1347	{	1827	{
1348	struct fe_priv *np = netdev_priv(dev);	1828	struct fe_priv *np = get_nvpriv(dev);
1349		1829
1350	dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",	1830	dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1351	dev->name, skbnr);	1831	dev->name, skbnr);
1352		1832
1353	if (np->tx_dma[skbnr]) {	1833	if (np->tx_skb[skbnr].dma) {
1354	pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],	1834	pci_unmap_page(np->pci_dev, np->tx_skb[skbnr].dma,
1355	np->tx_dma_len[skbnr],	1835	np->tx_skb[skbnr].dma_len,
1356	PCI_DMA_TODEVICE);	1836	PCI_DMA_TODEVICE);
1357	np->tx_dma[skbnr] = 0;	1837	np->tx_skb[skbnr].dma = 0;
1358	}	1838	}
1359		1839	if (np->tx_skb[skbnr].skb) {
1360	if (np->tx_skbuff[skbnr]) {	1840	dev_kfree_skb_any(np->tx_skb[skbnr].skb);
1361	dev_kfree_skb_any(np->tx_skbuff[skbnr]);	1841	np->tx_skb[skbnr].skb = NULL;
1362	np->tx_skbuff[skbnr] = NULL;
1363	return 1;	1842	return 1;
1364	} else {	1843	} else {
1365	return 0;	1844	return 0;
Lines 1368-1381 Link Here
1368		1847
1369	static void nv_drain_tx(struct net_device *dev)	1848	static void nv_drain_tx(struct net_device *dev)
1370	{	1849	{
1371	struct fe_priv *np = netdev_priv(dev);	1850	struct fe_priv *np = get_nvpriv(dev);
1372	unsigned int i;	1851	unsigned int i;
1373		1852
1374	for (i = 0; i < np->tx_ring_size; i++) {	1853	for (i = 0; i < np->tx_ring_size; i++) {
1375	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)	1854	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1376	np->tx_ring.orig[i].FlagLen = 0;	1855	np->tx_ring.orig[i].FlagLen = 0;
1377	else	1856	np->tx_ring.orig[i].PacketBuffer = 0;
		1857	} else {
1378	np->tx_ring.ex[i].FlagLen = 0;	1858	np->tx_ring.ex[i].FlagLen = 0;
		1859	np->tx_ring.ex[i].TxVlan = 0;
		1860	np->tx_ring.ex[i].PacketBufferHigh = 0;
		1861	np->tx_ring.ex[i].PacketBufferLow = 0;
		1862	}
1379	if (nv_release_txskb(dev, i))	1863	if (nv_release_txskb(dev, i))
1380	np->stats.tx_dropped++;	1864	np->stats.tx_dropped++;
1381	}	1865	}
Lines 1383-1402 Link Here
1383		1867
1384	static void nv_drain_rx(struct net_device *dev)	1868	static void nv_drain_rx(struct net_device *dev)
1385	{	1869	{
1386	struct fe_priv *np = netdev_priv(dev);	1870	struct fe_priv *np = get_nvpriv(dev);
1387	int i;	1871	int i;
1388	for (i = 0; i < np->rx_ring_size; i++) {	1872	for (i = 0; i < np->rx_ring_size; i++) {
1389	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)	1873	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1390	np->rx_ring.orig[i].FlagLen = 0;	1874	np->rx_ring.orig[i].FlagLen = 0;
1391	else	1875	np->rx_ring.orig[i].PacketBuffer = 0;
		1876	} else {
1392	np->rx_ring.ex[i].FlagLen = 0;	1877	np->rx_ring.ex[i].FlagLen = 0;
		1878	np->rx_ring.ex[i].TxVlan = 0;
		1879	np->rx_ring.ex[i].PacketBufferHigh = 0;
		1880	np->rx_ring.ex[i].PacketBufferLow = 0;
		1881	}
1393	wmb();	1882	wmb();
1394	if (np->rx_skbuff[i]) {	1883	if (np->rx_skb[i].skb) {
1395	pci_unmap_single(np->pci_dev, np->rx_dma[i],	1884	pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1396	np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,	1885	np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1397	PCI_DMA_FROMDEVICE);	1886	PCI_DMA_FROMDEVICE);
1398	dev_kfree_skb(np->rx_skbuff[i]);	1887	dev_kfree_skb(np->rx_skb[i].skb);
1399	np->rx_skbuff[i] = NULL;	1888	np->rx_skb[i].skb = NULL;
1400	}	1889	}
1401	}	1890	}
1402	}	1891	}
Lines 1409-1465 Link Here
1409		1898
1410	/*	1899	/*
1411	* nv_start_xmit: dev->hard_start_xmit function	1900	* nv_start_xmit: dev->hard_start_xmit function
1412	* Called with netif_tx_lock held.	1901	* Called with dev->xmit_lock held.
1413	*/	1902	*/
1414	static int nv_start_xmit(struct sk_buff skb, struct net_device dev)	1903	static int nv_start_xmit(struct sk_buff skb, struct net_device dev)
1415	{	1904	{
1416	struct fe_priv *np = netdev_priv(dev);	1905	struct fe_priv *np = get_nvpriv(dev);
1417	u32 tx_flags = 0;	1906	u32 tx_flags = 0;
1418	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);	1907	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1419	unsigned int fragments = skb_shinfo(skb)->nr_frags;	1908	unsigned int fragments = skb_shinfo(skb)->nr_frags;
1420	unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1421	unsigned int start_nr = np->next_tx % np->tx_ring_size;
1422	unsigned int i;	1909	unsigned int i;
1423	u32 offset = 0;	1910	u32 offset = 0;
1424	u32 bcnt;	1911	u32 bcnt;
1425	u32 size = skb->len-skb->data_len;	1912	u32 size = skb->len-skb->data_len;
1426	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);	1913	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1427	u32 tx_flags_vlan = 0;	1914	u32 empty_slots;
		1915	struct ring_desc* put_tx;
		1916	struct ring_desc* start_tx;
		1917	struct ring_desc* prev_tx;
		1918	struct nv_skb_map* prev_tx_ctx;
1428		1919
		1920	//dprintk(KERN_DEBUG "%s: nv_start_xmit \n", dev->name);
1429	/* add fragments to entries count */	1921	/* add fragments to entries count */
1430	for (i = 0; i < fragments; i++) {	1922	for (i = 0; i < fragments; i++) {
1431	entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +	1923	entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1432	((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);	1924	((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1433	}	1925	}
1434		1926
1435	spin_lock_irq(&np->lock);	1927	empty_slots = (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
		1928	if (likely(empty_slots > entries)) {
1436		1929
1437	if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {	1930	start_tx = put_tx = np->put_tx.orig;
1438	spin_unlock_irq(&np->lock);
1439	netif_stop_queue(dev);
1440	return NETDEV_TX_BUSY;
1441	}
1442		1931
1443	/* setup the header buffer */	1932	/* setup the header buffer */
1444	do {	1933	do {
		1934	prev_tx = put_tx;
		1935	prev_tx_ctx = np->put_tx_ctx;
1445	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;	1936	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1446	nr = (nr + 1) % np->tx_ring_size;	1937	np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1447
1448	np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1449	PCI_DMA_TODEVICE);	1938	PCI_DMA_TODEVICE);
1450	np->tx_dma_len[nr] = bcnt;	1939	np->put_tx_ctx->dma_len = bcnt;
		1940	put_tx->PacketBuffer = cpu_to_le32(np->put_tx_ctx->dma);
		1941	put_tx->FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1451		1942
1452	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1453	np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1454	np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1455	} else {
1456	np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1457	np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1458	np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1459	}
1460	tx_flags = np->tx_flags;	1943	tx_flags = np->tx_flags;
1461	offset += bcnt;	1944	offset += bcnt;
1462	size -= bcnt;	1945	size -= bcnt;
		1946	if (unlikely(put_tx++ == np->last_tx.orig))
		1947	put_tx = np->first_tx.orig;
		1948	if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
		1949	np->put_tx_ctx = np->first_tx_ctx;
1463	} while(size);	1950	} while(size);
1464		1951
1465	/* setup the fragments */	1952	/* setup the fragments */
Lines 1469-1502 Link Here
1469	offset = 0;	1956	offset = 0;
1470		1957
1471	do {	1958	do {
		1959	prev_tx = put_tx;
		1960	prev_tx_ctx = np->put_tx_ctx;
1472	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;	1961	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1473	nr = (nr + 1) % np->tx_ring_size;
1474		1962
1475	np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,	1963	np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1476	PCI_DMA_TODEVICE);	1964	PCI_DMA_TODEVICE);
1477	np->tx_dma_len[nr] = bcnt;	1965	np->put_tx_ctx->dma_len = bcnt;
1478		1966
1479	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	1967	put_tx->PacketBuffer = cpu_to_le32(np->put_tx_ctx->dma);
1480	np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);	1968	put_tx->FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1481	np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1482	} else {
1483	np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1484	np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1485	np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
1486	}
1487	offset += bcnt;	1969	offset += bcnt;
1488	size -= bcnt;	1970	size -= bcnt;
		1971	if (unlikely(put_tx++ == np->last_tx.orig))
		1972	put_tx = np->first_tx.orig;
		1973	if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
		1974	np->put_tx_ctx = np->first_tx_ctx;
1489	} while (size);	1975	} while (size);
1490	}	1976	}
1491		1977
1492	/* set last fragment flag */	1978	/* set last fragment flag */
1493	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	1979	prev_tx->FlagLen \|= cpu_to_le32(tx_flags_extra);
1494	np->tx_ring.orig[nr].FlagLen \|= cpu_to_le32(tx_flags_extra);
1495	} else {
1496	np->tx_ring.ex[nr].FlagLen \|= cpu_to_le32(tx_flags_extra);
1497	}
1498		1980
1499	np->tx_skbuff[nr] = skb;	1981	/* save skb in this slot's context area */
		1982	prev_tx_ctx->skb = skb;
1500		1983
1501	#ifdef NETIF_F_TSO	1984	#ifdef NETIF_F_TSO
1502	if (skb_is_gso(skb))	1985	if (skb_is_gso(skb))
Lines 1505-1542 Link Here
1505	#endif	1988	#endif
1506	tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3\|NV_TX2_CHECKSUM_L4) : 0);	1989	tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3\|NV_TX2_CHECKSUM_L4) : 0);
1507		1990
1508	/* vlan tag */	1991	start_tx->FlagLen \|= cpu_to_le32(tx_flags \| tx_flags_extra);
1509	if (np->vlangrp && vlan_tx_tag_present(skb)) {	1992	np->put_tx.orig = put_tx;
1510	tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT \| vlan_tx_tag_get(skb);
1511	}
1512		1993
1513	/* set tx flags */	1994	dev->trans_start = jiffies;
1514	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	1995	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1515	np->tx_ring.orig[start_nr].FlagLen \|= cpu_to_le32(tx_flags \| tx_flags_extra);	1996	return NETDEV_TX_OK;
1516	} else {	1997	} else {
1517	np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);	1998	netif_stop_queue(dev);
1518	np->tx_ring.ex[start_nr].FlagLen \|= cpu_to_le32(tx_flags \| tx_flags_extra);	1999	np->stop_tx = 1;
		2000	return NETDEV_TX_BUSY;
1519	}	2001	}
		2002	}
1520		2003
1521	dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",	2004	static int nv_start_xmit_optimized(struct sk_buff skb, struct net_device dev)
1522	dev->name, np->next_tx, entries, tx_flags_extra);	2005	{
1523	{	2006	struct fe_priv *np = get_nvpriv(dev);
1524	int j;	2007	u32 tx_flags = 0;
1525	for (j=0; j<64; j++) {	2008	u32 tx_flags_extra;
1526	if ((j%16) == 0)	2009	unsigned int fragments = skb_shinfo(skb)->nr_frags;
1527	dprintk("\n%03x:", j);	2010	unsigned int i;
1528	dprintk(" %02x", ((unsigned char*)skb->data)[j]);	2011	u32 offset = 0;
1529	}	2012	u32 bcnt;
1530	dprintk("\n");	2013	u32 size = skb->len-skb->data_len;
		2014	u32 empty_slots;
		2015	struct ring_desc_ex* put_tx;
		2016	struct ring_desc_ex* start_tx;
		2017	struct ring_desc_ex* prev_tx;
		2018	struct nv_skb_map* prev_tx_ctx;
		2019
		2020	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
		2021
		2022	//dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized \n", dev->name);
		2023	/* add fragments to entries count */
		2024	for (i = 0; i < fragments; i++) {
		2025	entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
		2026	((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1531	}	2027	}
1532		2028
1533	np->next_tx += entries;	2029	empty_slots = (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
		2030	if (likely(empty_slots > entries)) {
		2031
		2032	start_tx = put_tx = np->put_tx.ex;
		2033
		2034	/* setup the header buffer */
		2035	do {
		2036	prev_tx = put_tx;
		2037	prev_tx_ctx = np->put_tx_ctx;
		2038	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
		2039	np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
		2040	PCI_DMA_TODEVICE);
		2041	np->put_tx_ctx->dma_len = bcnt;
		2042	put_tx->PacketBufferHigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
		2043	put_tx->PacketBufferLow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
		2044	put_tx->FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
		2045
		2046	tx_flags = NV_TX2_VALID;
		2047	offset += bcnt;
		2048	size -= bcnt;
		2049	if (unlikely(put_tx++ == np->last_tx.ex))
		2050	put_tx = np->first_tx.ex;
		2051	if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
		2052	np->put_tx_ctx = np->first_tx_ctx;
		2053	} while(size);
		2054	/* setup the fragments */
		2055	for (i = 0; i < fragments; i++) {
		2056	skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
		2057	u32 size = frag->size;
		2058	offset = 0;
		2059
		2060	do {
		2061	prev_tx = put_tx;
		2062	prev_tx_ctx = np->put_tx_ctx;
		2063	bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
		2064
		2065	np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
		2066	PCI_DMA_TODEVICE);
		2067	np->put_tx_ctx->dma_len = bcnt;
		2068
		2069	put_tx->PacketBufferHigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
		2070	put_tx->PacketBufferLow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
		2071	put_tx->FlagLen = cpu_to_le32((bcnt-1) \| tx_flags);
		2072	offset += bcnt;
		2073	size -= bcnt;
		2074	if (unlikely(put_tx++ == np->last_tx.ex))
		2075	put_tx = np->first_tx.ex;
		2076	if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
		2077	np->put_tx_ctx = np->first_tx_ctx;
		2078	} while (size);
		2079	}
		2080
		2081	/* set last fragment flag */
		2082	prev_tx->FlagLen \|= cpu_to_le32(NV_TX2_LASTPACKET);
		2083
		2084	/* save skb in this slot's context area */
		2085	prev_tx_ctx->skb = skb;
		2086
		2087	#ifdef NETIF_F_TSO
		2088	if (skb_is_gso(skb))
		2089	tx_flags_extra = NV_TX2_TSO \| (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
		2090	else
		2091	#endif
		2092	tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3\|NV_TX2_CHECKSUM_L4) : 0);
		2093
2094	/* vlan tag */
2095	if (likely(!np->vlangrp)) {
2096	start_tx->TxVlan = 0;
2097	} else {
2098	if (vlan_tx_tag_present(skb))
2099	start_tx->TxVlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT \| vlan_tx_tag_get(skb));
2100	else
2101	start_tx->TxVlan = 0;
2102	}
2103
2104	/* set tx flags */
2105	start_tx->FlagLen \|= cpu_to_le32(tx_flags \| tx_flags_extra);
2106	np->put_tx.ex = put_tx;
1534		2107
1535	dev->trans_start = jiffies;	2108	dev->trans_start = jiffies;
1536	spin_unlock_irq(&np->lock);
1537	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);	2109	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1538	pci_push(get_hwbase(dev));
1539	return NETDEV_TX_OK;	2110	return NETDEV_TX_OK;
		2111
		2112	} else {
		2113	netif_stop_queue(dev);
		2114	np->stop_tx = 1;
		2115	return NETDEV_TX_BUSY;
		2116	}
1540	}	2117	}
1541		2118
1542	/*	2119	/*
Lines 1544-1573 Link Here
1544	*	2121	*
1545	* Caller must own np->lock.	2122	* Caller must own np->lock.
1546	*/	2123	*/
1547	static void nv_tx_done(struct net_device *dev)	2124	static inline void nv_tx_done(struct net_device *dev)
1548	{	2125	{
1549	struct fe_priv *np = netdev_priv(dev);	2126	struct fe_priv *np = get_nvpriv(dev);
1550	u32 Flags;	2127	u32 Flags;
1551	unsigned int i;	2128	struct ring_desc* orig_get_tx = np->get_tx.orig;
1552	struct sk_buff *skb;	2129	struct ring_desc* put_tx = np->put_tx.orig;
1553		2130
1554	while (np->nic_tx != np->next_tx) {	2131	//dprintk(KERN_DEBUG "%s: nv_tx_done \n", dev->name);
1555	i = np->nic_tx % np->tx_ring_size;	2132	while ((np->get_tx.orig != put_tx) &&
		2133	!((Flags = le32_to_cpu(np->get_tx.orig->FlagLen)) & NV_TX_VALID)) {
		2134	dprintk(KERN_DEBUG "%s: nv_tx_done:NVLAN tx done\n", dev->name);
1556		2135
1557	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)	2136	pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1558	Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);	2137	np->get_tx_ctx->dma_len,
1559	else	2138	PCI_DMA_TODEVICE);
1560	Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);	2139	np->get_tx_ctx->dma = 0;
1561		2140
1562	dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1563	dev->name, np->nic_tx, Flags);
1564	if (Flags & NV_TX_VALID)
1565	break;
1566	if (np->desc_ver == DESC_VER_1) {	2141	if (np->desc_ver == DESC_VER_1) {
1567	if (Flags & NV_TX_LASTPACKET) {	2142	if (Flags & NV_TX_LASTPACKET) {
1568	skb = np->tx_skbuff[i];	2143	if (Flags & NV_TX_ERROR) {
1569	if (Flags & (NV_TX_RETRYERROR\|NV_TX_CARRIERLOST\|NV_TX_LATECOLLISION\|
1570	NV_TX_UNDERFLOW\|NV_TX_ERROR)) {
1571	if (Flags & NV_TX_UNDERFLOW)	2144	if (Flags & NV_TX_UNDERFLOW)
1572	np->stats.tx_fifo_errors++;	2145	np->stats.tx_fifo_errors++;
1573	if (Flags & NV_TX_CARRIERLOST)	2146	if (Flags & NV_TX_CARRIERLOST)
Lines 1575-1588 Link Here
1575	np->stats.tx_errors++;	2148	np->stats.tx_errors++;
1576	} else {	2149	} else {
1577	np->stats.tx_packets++;	2150	np->stats.tx_packets++;
1578	np->stats.tx_bytes += skb->len;	2151	np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1579	}	2152	}
		2153	dev_kfree_skb_any(np->get_tx_ctx->skb);
		2154	np->get_tx_ctx->skb = NULL;
		2155
1580	}	2156	}
1581	} else {	2157	} else {
1582	if (Flags & NV_TX2_LASTPACKET) {	2158	if (Flags & NV_TX2_LASTPACKET) {
1583	skb = np->tx_skbuff[i];	2159	if (Flags & NV_TX2_ERROR) {
1584	if (Flags & (NV_TX2_RETRYERROR\|NV_TX2_CARRIERLOST\|NV_TX2_LATECOLLISION\|
1585	NV_TX2_UNDERFLOW\|NV_TX2_ERROR)) {
1586	if (Flags & NV_TX2_UNDERFLOW)	2160	if (Flags & NV_TX2_UNDERFLOW)
1587	np->stats.tx_fifo_errors++;	2161	np->stats.tx_fifo_errors++;
1588	if (Flags & NV_TX2_CARRIERLOST)	2162	if (Flags & NV_TX2_CARRIERLOST)
Lines 1590-1616 Link Here
1590	np->stats.tx_errors++;	2164	np->stats.tx_errors++;
1591	} else {	2165	} else {
1592	np->stats.tx_packets++;	2166	np->stats.tx_packets++;
1593	np->stats.tx_bytes += skb->len;	2167	np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1594	}	2168	}
		2169	dev_kfree_skb_any(np->get_tx_ctx->skb);
		2170	np->get_tx_ctx->skb = NULL;
		2171	}
		2172	}
		2173
		2174	if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
		2175	np->get_tx.orig = np->first_tx.orig;
		2176	if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
		2177	np->get_tx_ctx = np->first_tx_ctx;
		2178	}
		2179	if (unlikely((np->stop_tx == 1) && (np->get_tx.orig != orig_get_tx))) {
		2180	np->stop_tx = 0;
		2181	netif_wake_queue(dev);
		2182	}
		2183	}
		2184
		2185	static inline void nv_tx_done_optimized(struct net_device *dev, int max_work)
		2186	{
		2187	struct fe_priv *np = get_nvpriv(dev);
		2188	u32 Flags;
		2189	struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
		2190	struct ring_desc_ex* put_tx = np->put_tx.ex;
		2191
		2192	//dprintk(KERN_DEBUG "%s: nv_tx_done_optimized \n", dev->name);
		2193	while ((np->get_tx.ex != put_tx) &&
		2194	!((Flags = le32_to_cpu(np->get_tx.ex->FlagLen)) & NV_TX_VALID) &&
		2195	(max_work-- > 0)) {
		2196	dprintk(KERN_DEBUG "%s: nv_tx_done_optimized:NVLAN tx done\n", dev->name);
		2197
		2198	pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
		2199	np->get_tx_ctx->dma_len,
		2200	PCI_DMA_TODEVICE);
		2201	np->get_tx_ctx->dma = 0;
		2202
		2203	if (Flags & NV_TX2_LASTPACKET) {
		2204	if (!(Flags & NV_TX2_ERROR)) {
		2205	np->stats.tx_packets++;
1595	}	2206	}
		2207	dev_kfree_skb_any(np->get_tx_ctx->skb);
		2208	np->get_tx_ctx->skb = NULL;
1596	}	2209	}
1597	nv_release_txskb(dev, i);	2210
1598	np->nic_tx++;	2211	if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
		2212	np->get_tx.ex = np->first_tx.ex;
		2213	if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
		2214	np->get_tx_ctx = np->first_tx_ctx;
1599	}	2215	}
1600	if (np->next_tx - np->nic_tx < np->tx_limit_start)	2216	if (unlikely((np->stop_tx == 1) && (np->get_tx.ex != orig_get_tx))) {
		2217	np->stop_tx = 0;
1601	netif_wake_queue(dev);	2218	netif_wake_queue(dev);
		2219	}
1602	}	2220	}
1603		2221
1604	/*	2222	/*
1605	* nv_tx_timeout: dev->tx_timeout function	2223	* nv_tx_timeout: dev->tx_timeout function
1606	* Called with netif_tx_lock held.	2224	* Called with dev->xmit_lock held.
1607	*/	2225	*/
1608	static void nv_tx_timeout(struct net_device *dev)	2226	static void nv_tx_timeout(struct net_device *dev)
1609	{	2227	{
1610	struct fe_priv *np = netdev_priv(dev);	2228	struct fe_priv *np = get_nvpriv(dev);
1611	u8 __iomem *base = get_hwbase(dev);	2229	u8 __iomem *base = get_hwbase(dev);
1612	u32 status;	2230	u32 status;
1613		2231
		2232	if (!netif_running(dev))
		2233	return;
		2234
1614	if (np->msi_flags & NV_MSI_X_ENABLED)	2235	if (np->msi_flags & NV_MSI_X_ENABLED)
1615	status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;	2236	status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1616	else	2237	else
Lines 1621-1629 Link Here
1621	{	2242	{
1622	int i;	2243	int i;
1623		2244
1624	printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",	2245	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1625	dev->name, (unsigned long)np->ring_addr,	2246	printk(KERN_INFO "%s: Ring at %lx: get %lx put %lx\n",
1626	np->next_tx, np->nic_tx);	2247	dev->name, (unsigned long)np->tx_ring.orig,
		2248	(unsigned long)np->get_tx.orig, (unsigned long)np->put_tx.orig);
		2249	} else {
		2250	printk(KERN_INFO "%s: Ring at %lx: get %lx put %lx\n",
		2251	dev->name, (unsigned long)np->tx_ring.ex,
		2252	(unsigned long)np->get_tx.ex, (unsigned long)np->put_tx.ex);
		2253	}
1627	printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);	2254	printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1628	for (i=0;i<=np->register_size;i+= 32) {	2255	for (i=0;i<=np->register_size;i+= 32) {
1629	printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",	2256	printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
Lines 1637-1643 Link Here
1637	for (i=0;i<np->tx_ring_size;i+= 4) {	2264	for (i=0;i<np->tx_ring_size;i+= 4) {
1638	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	2265	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1639	printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",	2266	printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1640	i,	2267	i,
1641	le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),	2268	le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1642	le32_to_cpu(np->tx_ring.orig[i].FlagLen),	2269	le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1643	le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),	2270	le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
Lines 1648-1654 Link Here
1648	le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));	2275	le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1649	} else {	2276	} else {
1650	printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",	2277	printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1651	i,	2278	i,
1652	le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),	2279	le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1653	le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),	2280	le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1654	le32_to_cpu(np->tx_ring.ex[i].FlagLen),	2281	le32_to_cpu(np->tx_ring.ex[i].FlagLen),
Lines 1665-1683 Link Here
1665	}	2292	}
1666	}	2293	}
1667		2294
		2295	nv_disable_irq(dev);
1668	spin_lock_irq(&np->lock);	2296	spin_lock_irq(&np->lock);
1669		2297
1670	/* 1) stop tx engine */	2298	/* 1) stop tx engine */
1671	nv_stop_tx(dev);	2299	nv_stop_tx(dev);
1672		2300
1673	/* 2) check that the packets were not sent already: */	2301	/* 2) check that the packets were not sent already: */
		2302	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
1674	nv_tx_done(dev);	2303	nv_tx_done(dev);
		2304	else
		2305	nv_tx_done_optimized(dev, np->tx_ring_size);
1675		2306
1676	/* 3) if there are dead entries: clear everything */	2307	/* 3) if there are dead entries: clear everything */
1677	if (np->next_tx != np->nic_tx) {	2308	if (np->get_tx_ctx != np->put_tx_ctx) {
1678	printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);	2309	printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1679	nv_drain_tx(dev);	2310	nv_drain_tx(dev);
1680	np->next_tx = np->nic_tx = 0;	2311	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		2312	np->get_tx.orig = np->put_tx.orig = np->first_tx.orig;
		2313	else
		2314	np->get_tx.ex = np->put_tx.ex = np->first_tx.ex;
		2315	np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx;
1681	setup_hw_rings(dev, NV_SETUP_TX_RING);	2316	setup_hw_rings(dev, NV_SETUP_TX_RING);
1682	netif_wake_queue(dev);	2317	netif_wake_queue(dev);
1683	}	2318	}
Lines 1685-1690 Link Here
1685	/* 4) restart tx engine */	2320	/* 4) restart tx engine */
1686	nv_start_tx(dev);	2321	nv_start_tx(dev);
1687	spin_unlock_irq(&np->lock);	2322	spin_unlock_irq(&np->lock);
		2323	nv_enable_irq(dev);
1688	}	2324	}
1689		2325
1690	/*	2326	/*
Lines 1740-1782 Link Here
1740	}	2376	}
1741	}	2377	}
1742		2378
1743	static void nv_rx_process(struct net_device *dev)	2379	static inline void nv_rx_process(struct net_device *dev)
1744	{	2380	{
1745	struct fe_priv *np = netdev_priv(dev);	2381	struct fe_priv *np = get_nvpriv(dev);
1746	u32 Flags;	2382	u32 Flags;
1747	u32 vlanflags = 0;	2383	struct sk_buff *skb;
1748		2384	int len;
1749	for (;;) {
1750	struct sk_buff *skb;
1751	int len;
1752	int i;
1753	if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1754	break; /* we scanned the whole ring - do not continue */
1755
1756	i = np->cur_rx % np->rx_ring_size;
1757	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
1758	Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1759	len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1760	} else {
1761	Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1762	len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1763	vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1764	}
1765
1766	dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1767	dev->name, np->cur_rx, Flags);
1768		2385
1769	if (Flags & NV_RX_AVAIL)	2386	//dprintk(KERN_DEBUG "%s: nv_rx_process \n", dev->name);
1770	break; /* still owned by hardware, */	2387	while((np->get_rx.orig != np->put_rx.orig) &&
		2388	!((Flags = le32_to_cpu(np->get_rx.orig->FlagLen)) & NV_RX_AVAIL)) {
		2389
		2390	pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
		2391	np->get_rx_ctx->dma_len,
		2392	PCI_DMA_FROMDEVICE);
1771		2393
1772	/*	2394	skb = np->get_rx_ctx->skb;
1773	* the packet is for us - immediately tear down the pci mapping.	2395	np->get_rx_ctx->skb = NULL;
1774	* TODO: check if a prefetch of the first cacheline improves
1775	* the performance.
1776	*/
1777	pci_unmap_single(np->pci_dev, np->rx_dma[i],
1778	np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1779	PCI_DMA_FROMDEVICE);
1780		2396
1781	{	2397	{
1782	int j;	2398	int j;
Lines 1784-1901 Link Here
1784	for (j=0; j<64; j++) {	2400	for (j=0; j<64; j++) {
1785	if ((j%16) == 0)	2401	if ((j%16) == 0)
1786	dprintk("\n%03x:", j);	2402	dprintk("\n%03x:", j);
1787	dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);	2403	dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1788	}	2404	}
1789	dprintk("\n");	2405	dprintk("\n");
1790	}	2406	}
1791	/* look at what we actually got: */	2407
1792	if (np->desc_ver == DESC_VER_1) {	2408	if (np->desc_ver == DESC_VER_1) {
1793	if (!(Flags & NV_RX_DESCRIPTORVALID))
1794	goto next_pkt;
1795		2409
1796	if (Flags & NV_RX_ERROR) {	2410	if (likely(Flags & NV_RX_DESCRIPTORVALID)) {
1797	if (Flags & NV_RX_MISSEDFRAME) {	2411	len = Flags & LEN_MASK_V1;
1798	np->stats.rx_missed_errors++;	2412	if (unlikely(Flags & NV_RX_ERROR)) {
1799	np->stats.rx_errors++;	2413	if (Flags & NV_RX_ERROR4) {
1800	goto next_pkt;	2414	len = nv_getlen(dev, skb->data, len);
1801	}	2415	if (len < 0) {
1802	if (Flags & (NV_RX_ERROR1\|NV_RX_ERROR2\|NV_RX_ERROR3)) {	2416	np->stats.rx_errors++;
1803	np->stats.rx_errors++;	2417	dev_kfree_skb(skb);
1804	goto next_pkt;	2418	goto next_pkt;
1805	}	2419	}
1806	if (Flags & NV_RX_CRCERR) {	2420	}
1807	np->stats.rx_crc_errors++;	2421	/* framing errors are soft errors */
1808	np->stats.rx_errors++;	2422	else if (Flags & NV_RX_FRAMINGERR) {
1809	goto next_pkt;	2423	if (Flags & NV_RX_SUBSTRACT1) {
1810	}	2424	len--;
1811	if (Flags & NV_RX_OVERFLOW) {	2425	}
1812	np->stats.rx_over_errors++;	2426	}
1813	np->stats.rx_errors++;	2427	/* the rest are hard errors */
1814	goto next_pkt;	2428	else {
		2429	if (Flags & NV_RX_MISSEDFRAME)
		2430	np->stats.rx_missed_errors++;
		2431	if (Flags & NV_RX_CRCERR)
		2432	np->stats.rx_crc_errors++;
		2433	if (Flags & NV_RX_OVERFLOW)
		2434	np->stats.rx_over_errors++;
		2435	np->stats.rx_errors++;
		2436	dev_kfree_skb(skb);
		2437	goto next_pkt;
		2438	}
1815	}	2439	}
1816	if (Flags & NV_RX_ERROR4) {	2440	} else {
1817	len = nv_getlen(dev, np->rx_skbuff[i]->data, len);	2441	dev_kfree_skb(skb);
1818	if (len < 0) {	2442	goto next_pkt;
		2443	}
		2444	} else {
		2445	if (likely(Flags & NV_RX2_DESCRIPTORVALID)) {
		2446	len = Flags & LEN_MASK_V2;
		2447	if (unlikely(Flags & NV_RX2_ERROR)) {
		2448	if (Flags & NV_RX2_ERROR4) {
		2449	len = nv_getlen(dev, skb->data, len);
		2450	if (len < 0) {
		2451	np->stats.rx_errors++;
		2452	dev_kfree_skb(skb);
		2453	goto next_pkt;
		2454	}
		2455	}
		2456	/* framing errors are soft errors */
		2457	else if (Flags & NV_RX2_FRAMINGERR) {
		2458	if (Flags & NV_RX2_SUBSTRACT1) {
		2459	len--;
		2460	}
		2461	}
		2462	/* the rest are hard errors */
		2463	else {
		2464	if (Flags & NV_RX2_CRCERR)
		2465	np->stats.rx_crc_errors++;
		2466	if (Flags & NV_RX2_OVERFLOW)
		2467	np->stats.rx_over_errors++;
1819	np->stats.rx_errors++;	2468	np->stats.rx_errors++;
		2469	dev_kfree_skb(skb);
1820	goto next_pkt;	2470	goto next_pkt;
1821	}	2471	}
1822	}	2472	}
1823	/* framing errors are soft errors. */	2473	if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/ip and tcp / {
1824	if (Flags & NV_RX_FRAMINGERR) {	2474	skb->ip_summed = CHECKSUM_UNNECESSARY;
1825	if (Flags & NV_RX_SUBSTRACT1) {	2475	} else {
1826	len--;	2476	if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 \|\|
		2477	(Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
		2478	skb->ip_summed = CHECKSUM_UNNECESSARY;
1827	}	2479	}
1828	}	2480	}
1829	}	2481	} else {
1830	} else {	2482	dev_kfree_skb(skb);
1831	if (!(Flags & NV_RX2_DESCRIPTORVALID))
1832	goto next_pkt;	2483	goto next_pkt;
		2484	}
		2485	}
1833		2486
1834	if (Flags & NV_RX2_ERROR) {	2487	/* got a valid packet - forward it to the network core */
1835	if (Flags & (NV_RX2_ERROR1\|NV_RX2_ERROR2\|NV_RX2_ERROR3)) {	2488	dprintk(KERN_DEBUG "%s: nv_rx_process:NVLAN rx done\n", dev->name);
1836	np->stats.rx_errors++;	2489	skb_put(skb, len);
1837	goto next_pkt;	2490	skb->protocol = eth_type_trans(skb, dev);
1838	}	2491	netif_rx(skb);
1839	if (Flags & NV_RX2_CRCERR) {	2492	dev->last_rx = jiffies;
1840	np->stats.rx_crc_errors++;	2493	np->stats.rx_packets++;
1841	np->stats.rx_errors++;	2494	np->stats.rx_bytes += len;
1842	goto next_pkt;	2495	next_pkt:
1843	}	2496	if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
1844	if (Flags & NV_RX2_OVERFLOW) {	2497	np->get_rx.orig = np->first_rx.orig;
1845	np->stats.rx_over_errors++;	2498	if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
1846	np->stats.rx_errors++;	2499	np->get_rx_ctx = np->first_rx_ctx;
1847	goto next_pkt;	2500	}
1848	}	2501	}
		2502
		2503	static inline int nv_rx_process_optimized(struct net_device *dev, int max_work)
		2504	{
		2505	struct fe_priv *np = get_nvpriv(dev);
		2506	u32 Flags;
		2507	u32 vlanflags = 0;
		2508	u32 rx_processed_cnt = 0;
		2509	struct sk_buff *skb;
		2510	int len;
		2511
		2512	// dprintk(KERN_DEBUG "%s: nv_rx_process_optimized \n", dev->name);
		2513	while((np->get_rx.ex != np->put_rx.ex) &&
		2514	!((Flags = le32_to_cpu(np->get_rx.ex->FlagLen)) & NV_RX2_AVAIL) &&
		2515	(rx_processed_cnt++ < max_work)) {
		2516
		2517	pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
		2518	np->get_rx_ctx->dma_len,
		2519	PCI_DMA_FROMDEVICE);
		2520
		2521	skb = np->get_rx_ctx->skb;
		2522	np->get_rx_ctx->skb = NULL;
		2523
		2524	/* look at what we actually got: */
		2525	if (likely(Flags & NV_RX2_DESCRIPTORVALID)) {
		2526	len = Flags & LEN_MASK_V2;
		2527	if (unlikely(Flags & NV_RX2_ERROR)) {
1849	if (Flags & NV_RX2_ERROR4) {	2528	if (Flags & NV_RX2_ERROR4) {
1850	len = nv_getlen(dev, np->rx_skbuff[i]->data, len);	2529	len = nv_getlen(dev, skb->data, len);
1851	if (len < 0) {	2530	if (len < 0) {
1852	np->stats.rx_errors++;	2531	np->rx_len_errors++;
		2532	dev_kfree_skb(skb);
1853	goto next_pkt;	2533	goto next_pkt;
1854	}	2534	}
1855	}	2535	}
1856	/* framing errors are soft errors */	2536	/* framing errors are soft errors */
1857	if (Flags & NV_RX2_FRAMINGERR) {	2537	else if (Flags & NV_RX2_FRAMINGERR) {
1858	if (Flags & NV_RX2_SUBSTRACT1) {	2538	if (Flags & NV_RX2_SUBSTRACT1) {
1859	len--;	2539	len--;
1860	}	2540	}
1861	}	2541	}
		2542	/* the rest are hard errors */
		2543	else {
		2544	dev_kfree_skb(skb);
		2545	goto next_pkt;
		2546	}
1862	}	2547	}
1863	if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {	2548
1864	Flags &= NV_RX2_CHECKSUMMASK;	2549	if (likely(np->rx_csum)) {
1865	if (Flags == NV_RX2_CHECKSUMOK1 \|\|	2550	if (likely((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)) {
1866	Flags == NV_RX2_CHECKSUMOK2 \|\|	2551	/ip and tcp /
1867	Flags == NV_RX2_CHECKSUMOK3) {	2552	skb->ip_summed = CHECKSUM_UNNECESSARY;
1868	dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1869	np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1870	} else {	2553	} else {
1871	dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);	2554	if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 \|\|
		2555	(Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
		2556	skb->ip_summed = CHECKSUM_UNNECESSARY;
		2557	}
1872	}	2558	}
1873	}	2559	}
1874	}	2560	dprintk(KERN_DEBUG "%s: nv_rx_process_optimized:NVLAN rx done\n", dev->name);
1875	/* got a valid packet - forward it to the network core */
1876	skb = np->rx_skbuff[i];
1877	np->rx_skbuff[i] = NULL;
1878		2561
1879	skb_put(skb, len);	2562	/* got a valid packet - forward it to the network core */
1880	skb->protocol = eth_type_trans(skb, dev);	2563	skb_put(skb, len);
1881	dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",	2564	skb->protocol = eth_type_trans(skb, dev);
1882	dev->name, np->cur_rx, len, skb->protocol);	2565	prefetch(skb->data);
1883	if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {	2566
1884	vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);	2567	if (likely(!np->vlangrp)) {
		2568	netif_rx(skb);
		2569	} else {
		2570	vlanflags = le32_to_cpu(np->get_rx.ex->PacketBufferLow);
		2571	if (vlanflags & NV_RX3_VLAN_TAG_PRESENT)
		2572	vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
		2573	else
		2574	netif_rx(skb);
		2575	}
		2576
		2577	dev->last_rx = jiffies;
		2578	np->stats.rx_packets++;
		2579	np->stats.rx_bytes += len;
1885	} else {	2580	} else {
1886	netif_rx(skb);	2581	dev_kfree_skb(skb);
1887	}	2582	}
1888	dev->last_rx = jiffies;
1889	np->stats.rx_packets++;
1890	np->stats.rx_bytes += len;
1891	next_pkt:	2583	next_pkt:
1892	np->cur_rx++;	2584	if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
		2585	np->get_rx.ex = np->first_rx.ex;
		2586	if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
		2587	np->get_rx_ctx = np->first_rx_ctx;
1893	}	2588	}
		2589	return rx_processed_cnt;
1894	}	2590	}
1895		2591
1896	static void set_bufsize(struct net_device *dev)	2592	static void set_bufsize(struct net_device *dev)
1897	{	2593	{
1898	struct fe_priv *np = netdev_priv(dev);	2594	struct fe_priv *np = get_nvpriv(dev);
1899		2595
1900	if (dev->mtu <= ETH_DATA_LEN)	2596	if (dev->mtu <= ETH_DATA_LEN)
1901	np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;	2597	np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
Lines 1909-1915 Link Here
1909	*/	2605	*/
1910	static int nv_change_mtu(struct net_device *dev, int new_mtu)	2606	static int nv_change_mtu(struct net_device *dev, int new_mtu)
1911	{	2607	{
1912	struct fe_priv *np = netdev_priv(dev);	2608	struct fe_priv *np = get_nvpriv(dev);
1913	int old_mtu;	2609	int old_mtu;
1914		2610
1915	if (new_mtu < 64 \|\| new_mtu > np->pkt_limit)	2611	if (new_mtu < 64 \|\| new_mtu > np->pkt_limit)
Lines 1987-1998 Link Here
1987	*/	2683	*/
1988	static int nv_set_mac_address(struct net_device dev, void addr)	2684	static int nv_set_mac_address(struct net_device dev, void addr)
1989	{	2685	{
1990	struct fe_priv *np = netdev_priv(dev);	2686	struct fe_priv *np = get_nvpriv(dev);
1991	struct sockaddr macaddr = (struct sockaddr)addr;	2687	struct sockaddr macaddr = (struct sockaddr)addr;
1992		2688
1993	if(!is_valid_ether_addr(macaddr->sa_data))	2689	if(!is_valid_ether_addr(macaddr->sa_data))
1994	return -EADDRNOTAVAIL;	2690	return -EADDRNOTAVAIL;
1995		2691
		2692	dprintk(KERN_DEBUG "%s: nv_set_mac_address \n", dev->name);
1996	/* synchronized against open : rtnl_lock() held by caller */	2693	/* synchronized against open : rtnl_lock() held by caller */
1997	memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);	2694	memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1998		2695
Lines 2018-2028 Link Here
2018		2715
2019	/*	2716	/*
2020	* nv_set_multicast: dev->set_multicast function	2717	* nv_set_multicast: dev->set_multicast function
2021	* Called with netif_tx_lock held.	2718	* Called with dev->xmit_lock held.
2022	*/	2719	*/
2023	static void nv_set_multicast(struct net_device *dev)	2720	static void nv_set_multicast(struct net_device *dev)
2024	{	2721	{
2025	struct fe_priv *np = netdev_priv(dev);	2722	struct fe_priv *np = get_nvpriv(dev);
2026	u8 __iomem *base = get_hwbase(dev);	2723	u8 __iomem *base = get_hwbase(dev);
2027	u32 addr[2];	2724	u32 addr[2];
2028	u32 mask[2];	2725	u32 mask[2];
Lines 2032-2038 Link Here
2032	memset(mask, 0, sizeof(mask));	2729	memset(mask, 0, sizeof(mask));
2033		2730
2034	if (dev->flags & IFF_PROMISC) {	2731	if (dev->flags & IFF_PROMISC) {
2035	printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);	2732	dprintk(KERN_DEBUG "%s: Promiscuous mode enabled.\n", dev->name);
2036	pff \|= NVREG_PFF_PROMISC;	2733	pff \|= NVREG_PFF_PROMISC;
2037	} else {	2734	} else {
2038	pff \|= NVREG_PFF_MYADDR;	2735	pff \|= NVREG_PFF_MYADDR;
Lines 2082-2088 Link Here
2082		2779
2083	static void nv_update_pause(struct net_device *dev, u32 pause_flags)	2780	static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2084	{	2781	{
2085	struct fe_priv *np = netdev_priv(dev);	2782	struct fe_priv *np = get_nvpriv(dev);
2086	u8 __iomem *base = get_hwbase(dev);	2783	u8 __iomem *base = get_hwbase(dev);
2087		2784
2088	np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE \| NV_PAUSEFRAME_RX_ENABLE);	2785	np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE \| NV_PAUSEFRAME_RX_ENABLE);
Lines 2104-2110 Link Here
2104	np->pause_flags \|= NV_PAUSEFRAME_TX_ENABLE;	2801	np->pause_flags \|= NV_PAUSEFRAME_TX_ENABLE;
2105	} else {	2802	} else {
2106	writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);	2803	writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2107	writel(regmisc, base + NvRegMisc1);	2804	writel(regmisc, base + NvRegMisc1);
2108	}	2805	}
2109	}	2806	}
2110	}	2807	}
Lines 2122-2128 Link Here
2122	*/	2819	*/
2123	static int nv_update_linkspeed(struct net_device *dev)	2820	static int nv_update_linkspeed(struct net_device *dev)
2124	{	2821	{
2125	struct fe_priv *np = netdev_priv(dev);	2822	struct fe_priv *np = get_nvpriv(dev);
2126	u8 __iomem *base = get_hwbase(dev);	2823	u8 __iomem *base = get_hwbase(dev);
2127	int adv = 0;	2824	int adv = 0;
2128	int lpa = 0;	2825	int lpa = 0;
Lines 2148-2154 Link Here
2148	goto set_speed;	2845	goto set_speed;
2149	}	2846	}
2150		2847
2151	if (np->autoneg == 0) {	2848	if (np->autoneg == AUTONEG_DISABLE) {
2152	dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",	2849	dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2153	dev->name, np->fixed_mode);	2850	dev->name, np->fixed_mode);
2154	if (np->fixed_mode & LPA_100FULL) {	2851	if (np->fixed_mode & LPA_100FULL) {
Lines 2181-2187 Link Here
2181	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);	2878	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2182	dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",	2879	dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2183	dev->name, adv, lpa);	2880	dev->name, adv, lpa);
2184
2185	retval = 1;	2881	retval = 1;
2186	if (np->gigabit == PHY_GIGABIT) {	2882	if (np->gigabit == PHY_GIGABIT) {
2187	control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);	2883	control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Lines 2268-2274 Link Here
2268	txreg = NVREG_TX_WM_DESC2_3_DEFAULT;	2964	txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2269	}	2965	}
2270	writel(txreg, base + NvRegTxWatermark);	2966	writel(txreg, base + NvRegTxWatermark);
2271
2272	writel(NVREG_MISC1_FORCE \| ( np->duplex ? 0 : NVREG_MISC1_HD),	2967	writel(NVREG_MISC1_FORCE \| ( np->duplex ? 0 : NVREG_MISC1_HD),
2273	base + NvRegMisc1);	2968	base + NvRegMisc1);
2274	pci_push(base);	2969	pci_push(base);
Lines 2306-2312 Link Here
2306	if (lpa_pause == LPA_PAUSE_ASYM)	3001	if (lpa_pause == LPA_PAUSE_ASYM)
2307	{	3002	{
2308	pause_flags \|= NV_PAUSEFRAME_RX_ENABLE;	3003	pause_flags \|= NV_PAUSEFRAME_RX_ENABLE;
2309	}	3004	}
2310	break;	3005	break;
2311	}	3006	}
2312	} else {	3007	} else {
Lines 2352-2358 Link Here
2352	static irqreturn_t nv_nic_irq(int foo, void data, struct pt_regs regs)	3047	static irqreturn_t nv_nic_irq(int foo, void data, struct pt_regs regs)
2353	{	3048	{
2354	struct net_device dev = (struct net_device ) data;	3049	struct net_device dev = (struct net_device ) data;
2355	struct fe_priv *np = netdev_priv(dev);	3050	struct fe_priv *np = get_nvpriv(dev);
2356	u8 __iomem *base = get_hwbase(dev);	3051	u8 __iomem *base = get_hwbase(dev);
2357	u32 events;	3052	u32 events;
2358	int i;	3053	int i;
Lines 2372-2381 Link Here
2372	if (!(events & np->irqmask))	3067	if (!(events & np->irqmask))
2373	break;	3068	break;
2374		3069
2375	spin_lock(&np->lock);
2376	nv_tx_done(dev);	3070	nv_tx_done(dev);
2377	spin_unlock(&np->lock);	3071
2378
2379	nv_rx_process(dev);	3072	nv_rx_process(dev);
2380	if (nv_alloc_rx(dev)) {	3073	if (nv_alloc_rx(dev)) {
2381	spin_lock(&np->lock);	3074	spin_lock(&np->lock);
Lines 2383-2389 Link Here
2383	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	3076	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2384	spin_unlock(&np->lock);	3077	spin_unlock(&np->lock);
2385	}	3078	}
2386		3079
2387	if (events & NVREG_IRQ_LINK) {	3080	if (events & NVREG_IRQ_LINK) {
2388	spin_lock(&np->lock);	3081	spin_lock(&np->lock);
2389	nv_link_irq(dev);	3082	nv_link_irq(dev);
Lines 2427-2436 Link Here
2427	return IRQ_RETVAL(i);	3120	return IRQ_RETVAL(i);
2428	}	3121	}
2429		3122
		3123	#define TX_WORK_PER_LOOP 64
		3124	#define RX_WORK_PER_LOOP 64
		3125	static irqreturn_t nv_nic_irq_optimized(int foo, void data, struct pt_regs regs)
		3126	{
		3127	struct net_device dev = (struct net_device ) data;
		3128	struct fe_priv *np = get_nvpriv(dev);
		3129	u8 __iomem *base = get_hwbase(dev);
		3130	u32 events;
		3131	int i = 1;
		3132
		3133	do {
		3134	if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
		3135	events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
		3136	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
		3137	} else {
		3138	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
		3139	writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
		3140	}
		3141	if (events & np->irqmask) {
		3142
		3143	nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
		3144
		3145	if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
		3146	if (unlikely(nv_alloc_rx_optimized(dev))) {
		3147	spin_lock(&np->lock);
		3148	if (!np->in_shutdown)
		3149	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
		3150	spin_unlock(&np->lock);
		3151	}
		3152	}
		3153	if (unlikely(events & NVREG_IRQ_LINK)) {
		3154	spin_lock(&np->lock);
		3155	nv_link_irq(dev);
		3156	spin_unlock(&np->lock);
		3157	}
		3158	if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
		3159	spin_lock(&np->lock);
		3160	nv_linkchange(dev);
		3161	spin_unlock(&np->lock);
		3162	np->link_timeout = jiffies + LINK_TIMEOUT;
		3163	}
		3164	if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
		3165	spin_lock(&np->lock);
		3166	/* disable interrupts on the nic */
		3167	if (!(np->msi_flags & NV_MSI_X_ENABLED))
		3168	writel(0, base + NvRegIrqMask);
		3169	else
		3170	writel(np->irqmask, base + NvRegIrqMask);
		3171	pci_push(base);
		3172
		3173	if (!np->in_shutdown) {
		3174	np->nic_poll_irq = np->irqmask;
		3175	np->recover_error = 1;
		3176	mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
		3177	}
		3178	spin_unlock(&np->lock);
		3179	break;
		3180	}
		3181	} else
		3182	break;
		3183	}
		3184	while (i++ <= max_interrupt_work);
		3185
		3186	return IRQ_RETVAL(i);
3187	}
3188
2430	static irqreturn_t nv_nic_irq_tx(int foo, void data, struct pt_regs regs)	3189	static irqreturn_t nv_nic_irq_tx(int foo, void data, struct pt_regs regs)
2431	{	3190	{
2432	struct net_device dev = (struct net_device ) data;	3191	struct net_device dev = (struct net_device ) data;
2433	struct fe_priv *np = netdev_priv(dev);	3192	struct fe_priv *np = get_nvpriv(dev);
2434	u8 __iomem *base = get_hwbase(dev);	3193	u8 __iomem *base = get_hwbase(dev);
2435	u32 events;	3194	u32 events;
2436	int i;	3195	int i;
Lines 2440-2454 Link Here
2440	for (i=0; ; i++) {	3199	for (i=0; ; i++) {
2441	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;	3200	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2442	writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);	3201	writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2443	pci_push(base);
2444	dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);	3202	dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2445	if (!(events & np->irqmask))	3203	if (!(events & np->irqmask))
2446	break;	3204	break;
2447		3205
2448	spin_lock_irq(&np->lock);	3206	nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2449	nv_tx_done(dev);	3207
2450	spin_unlock_irq(&np->lock);
2451
2452	if (events & (NVREG_IRQ_TX_ERR)) {	3208	if (events & (NVREG_IRQ_TX_ERR)) {
2453	dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",	3209	dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2454	dev->name, events);	3210	dev->name, events);
Lines 2477-2483 Link Here
2477	static irqreturn_t nv_nic_irq_rx(int foo, void data, struct pt_regs regs)	3233	static irqreturn_t nv_nic_irq_rx(int foo, void data, struct pt_regs regs)
2478	{	3234	{
2479	struct net_device dev = (struct net_device ) data;	3235	struct net_device dev = (struct net_device ) data;
2480	struct fe_priv *np = netdev_priv(dev);	3236	struct fe_priv *np = get_nvpriv(dev);
2481	u8 __iomem *base = get_hwbase(dev);	3237	u8 __iomem *base = get_hwbase(dev);
2482	u32 events;	3238	u32 events;
2483	int i;	3239	int i;
Lines 2487-2505 Link Here
2487	for (i=0; ; i++) {	3243	for (i=0; ; i++) {
2488	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;	3244	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2489	writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);	3245	writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2490	pci_push(base);
2491	dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);	3246	dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2492	if (!(events & np->irqmask))	3247	if (!(events & np->irqmask))
2493	break;	3248	break;
2494		3249
2495	nv_rx_process(dev);	3250	if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
2496	if (nv_alloc_rx(dev)) {	3251	if (unlikely(nv_alloc_rx_optimized(dev))) {
2497	spin_lock_irq(&np->lock);	3252	spin_lock_irq(&np->lock);
2498	if (!np->in_shutdown)	3253	if (!np->in_shutdown)
2499	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	3254	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2500	spin_unlock_irq(&np->lock);	3255	spin_unlock_irq(&np->lock);
		3256	}
2501	}	3257	}
2502		3258
2503	if (i > max_interrupt_work) {	3259	if (i > max_interrupt_work) {
2504	spin_lock_irq(&np->lock);	3260	spin_lock_irq(&np->lock);
2505	/* disable interrupts on the nic */	3261	/* disable interrupts on the nic */
Lines 2524-2530 Link Here
2524	static irqreturn_t nv_nic_irq_other(int foo, void data, struct pt_regs regs)	3280	static irqreturn_t nv_nic_irq_other(int foo, void data, struct pt_regs regs)
2525	{	3281	{
2526	struct net_device dev = (struct net_device ) data;	3282	struct net_device dev = (struct net_device ) data;
2527	struct fe_priv *np = netdev_priv(dev);	3283	struct fe_priv *np = get_nvpriv(dev);
2528	u8 __iomem *base = get_hwbase(dev);	3284	u8 __iomem *base = get_hwbase(dev);
2529	u32 events;	3285	u32 events;
2530	int i;	3286	int i;
Lines 2534-2544 Link Here
2534	for (i=0; ; i++) {	3290	for (i=0; ; i++) {
2535	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;	3291	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2536	writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);	3292	writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2537	pci_push(base);
2538	dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);	3293	dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2539	if (!(events & np->irqmask))	3294	if (!(events & np->irqmask))
2540	break;	3295	break;
2541		3296
2542	if (events & NVREG_IRQ_LINK) {	3297	if (events & NVREG_IRQ_LINK) {
2543	spin_lock_irq(&np->lock);	3298	spin_lock_irq(&np->lock);
2544	nv_link_irq(dev);	3299	nv_link_irq(dev);
Lines 2550-2555 Link Here
2550	spin_unlock_irq(&np->lock);	3305	spin_unlock_irq(&np->lock);
2551	np->link_timeout = jiffies + LINK_TIMEOUT;	3306	np->link_timeout = jiffies + LINK_TIMEOUT;
2552	}	3307	}
		3308	if (events & NVREG_IRQ_RECOVER_ERROR) {
		3309	spin_lock_irq(&np->lock);
		3310	/* disable interrupts on the nic */
		3311	writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
		3312	pci_push(base);
		3313
		3314	if (!np->in_shutdown) {
		3315	np->nic_poll_irq \|= NVREG_IRQ_OTHER;
		3316	np->recover_error = 1;
		3317	mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
		3318	}
		3319	spin_unlock_irq(&np->lock);
		3320	break;
		3321	}
2553	if (events & (NVREG_IRQ_UNKNOWN)) {	3322	if (events & (NVREG_IRQ_UNKNOWN)) {
2554	printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",	3323	printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2555	dev->name, events);	3324	dev->name, events);
Lines 2578-2584 Link Here
2578	static irqreturn_t nv_nic_irq_test(int foo, void data, struct pt_regs regs)	3347	static irqreturn_t nv_nic_irq_test(int foo, void data, struct pt_regs regs)
2579	{	3348	{
2580	struct net_device dev = (struct net_device ) data;	3349	struct net_device dev = (struct net_device ) data;
2581	struct fe_priv *np = netdev_priv(dev);	3350	struct fe_priv *np = get_nvpriv(dev);
2582	u8 __iomem *base = get_hwbase(dev);	3351	u8 __iomem *base = get_hwbase(dev);
2583	u32 events;	3352	u32 events;
2584		3353
Lines 2595-2610 Link Here
2595	dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);	3364	dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2596	if (!(events & NVREG_IRQ_TIMER))	3365	if (!(events & NVREG_IRQ_TIMER))
2597	return IRQ_RETVAL(0);	3366	return IRQ_RETVAL(0);
2598		3367
2599	spin_lock(&np->lock);	3368	spin_lock(&np->lock);
2600	np->intr_test = 1;	3369	np->intr_test = 1;
2601	spin_unlock(&np->lock);	3370	spin_unlock(&np->lock);
2602		3371
2603	dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);	3372	dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2604		3373
2605	return IRQ_RETVAL(1);	3374	return IRQ_RETVAL(1);
2606	}	3375	}
2607		3376
		3377	#ifdef CONFIG_PCI_MSI
2608	static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)	3378	static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2609	{	3379	{
2610	u8 __iomem *base = get_hwbase(dev);	3380	u8 __iomem *base = get_hwbase(dev);
Lines 2630-2641 Link Here
2630	}	3400	}
2631	writel(readl(base + NvRegMSIXMap1) \| msixmap, base + NvRegMSIXMap1);	3401	writel(readl(base + NvRegMSIXMap1) \| msixmap, base + NvRegMSIXMap1);
2632	}	3402	}
		3403	#endif
2633		3404
2634	static int nv_request_irq(struct net_device *dev, int intr_test)	3405	static int nv_request_irq(struct net_device *dev, int intr_test)
2635	{	3406	{
2636	struct fe_priv *np = get_nvpriv(dev);	3407	struct fe_priv *np = get_nvpriv(dev);
2637	u8 __iomem *base = get_hwbase(dev);
2638	int ret = 1;	3408	int ret = 1;
		3409
		3410	u8 __iomem *base = get_hwbase(dev);
2639	int i;	3411	int i;
2640		3412
2641	if (np->msi_flags & NV_MSI_X_CAPABLE) {	3413	if (np->msi_flags & NV_MSI_X_CAPABLE) {
Lines 2646-2666 Link Here
2646	np->msi_flags \|= NV_MSI_X_ENABLED;	3418	np->msi_flags \|= NV_MSI_X_ENABLED;
2647	if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {	3419	if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2648	/* Request irq for rx handling */	3420	/* Request irq for rx handling */
2649	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {	3421	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
2650	printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);	3422	printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2651	pci_disable_msix(np->pci_dev);	3423	pci_disable_msix(np->pci_dev);
2652	np->msi_flags &= ~NV_MSI_X_ENABLED;	3424	np->msi_flags &= ~NV_MSI_X_ENABLED;
2653	goto out_err;	3425	goto out_err;
2654	}	3426	}
2655	/* Request irq for tx handling */	3427	/* Request irq for tx handling */
2656	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {	3428	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
2657	printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);	3429	printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2658	pci_disable_msix(np->pci_dev);	3430	pci_disable_msix(np->pci_dev);
2659	np->msi_flags &= ~NV_MSI_X_ENABLED;	3431	np->msi_flags &= ~NV_MSI_X_ENABLED;
2660	goto out_free_rx;	3432	goto out_free_rx;
2661	}	3433	}
2662	/* Request irq for link and timer handling */	3434	/* Request irq for link and timer handling */
2663	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {	3435	if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
2664	printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);	3436	printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2665	pci_disable_msix(np->pci_dev);	3437	pci_disable_msix(np->pci_dev);
2666	np->msi_flags &= ~NV_MSI_X_ENABLED;	3438	np->msi_flags &= ~NV_MSI_X_ENABLED;
Lines 2669-2683 Link Here
2669	/* map interrupts to their respective vector */	3441	/* map interrupts to their respective vector */
2670	writel(0, base + NvRegMSIXMap0);	3442	writel(0, base + NvRegMSIXMap0);
2671	writel(0, base + NvRegMSIXMap1);	3443	writel(0, base + NvRegMSIXMap1);
		3444	#ifdef CONFIG_PCI_MSI
2672	set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);	3445	set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2673	set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);	3446	set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2674	set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);	3447	set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
		3448	#endif
2675	} else {	3449	} else {
2676	/* Request irq for all interrupts */	3450	/* Request irq for all interrupts */
2677	if ((!intr_test &&	3451	if ((!intr_test && np->desc_ver == DESC_VER_3 &&
2678	request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) \|\|	3452	request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) \|\|
		3453	(!intr_test && np->desc_ver != DESC_VER_3 &&
		3454	request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) \|\|
2679	(intr_test &&	3455	(intr_test &&
2680	request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {	3456	request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
2681	printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);	3457	printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2682	pci_disable_msix(np->pci_dev);	3458	pci_disable_msix(np->pci_dev);
2683	np->msi_flags &= ~NV_MSI_X_ENABLED;	3459	np->msi_flags &= ~NV_MSI_X_ENABLED;
Lines 2693-2700 Link Here
2693	if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {	3469	if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2694	if ((ret = pci_enable_msi(np->pci_dev)) == 0) {	3470	if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2695	np->msi_flags \|= NV_MSI_ENABLED;	3471	np->msi_flags \|= NV_MSI_ENABLED;
2696	if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) \|\|	3472	if ((!intr_test && np->desc_ver == DESC_VER_3 &&
2697	(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {	3473	request_irq(np->pci_dev->irq, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) \|\|
		3474	(!intr_test && np->desc_ver != DESC_VER_3 &&
		3475	request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) \|\|
		3476	(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
2698	printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);	3477	printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2699	pci_disable_msi(np->pci_dev);	3478	pci_disable_msi(np->pci_dev);
2700	np->msi_flags &= ~NV_MSI_ENABLED;	3479	np->msi_flags &= ~NV_MSI_ENABLED;
Lines 2709-2721 Link Here
2709	}	3488	}
2710	}	3489	}
2711	if (ret != 0) {	3490	if (ret != 0) {
2712	if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) \|\|	3491	if ((!intr_test && np->desc_ver == DESC_VER_3 &&
2713	(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))	3492	request_irq(np->pci_dev->irq, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) \|\|
		3493	(!intr_test && np->desc_ver != DESC_VER_3 &&
		3494	request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) \|\|
		3495	(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0))
2714	goto out_err;	3496	goto out_err;
2715		3497
2716	}	3498	}
2717		3499
2718	return 0;	3500	return 0;
		3501
2719	out_free_tx:	3502	out_free_tx:
2720	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);	3503	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2721	out_free_rx:	3504	out_free_rx:
Lines 2728-2734 Link Here
2728	{	3511	{
2729	struct fe_priv *np = get_nvpriv(dev);	3512	struct fe_priv *np = get_nvpriv(dev);
2730	int i;	3513	int i;
2731		3514
2732	if (np->msi_flags & NV_MSI_X_ENABLED) {	3515	if (np->msi_flags & NV_MSI_X_ENABLED) {
2733	for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {	3516	for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2734	free_irq(np->msi_x_entry[i].vector, dev);	3517	free_irq(np->msi_x_entry[i].vector, dev);
Lines 2747-2753 Link Here
2747	static void nv_do_nic_poll(unsigned long data)	3530	static void nv_do_nic_poll(unsigned long data)
2748	{	3531	{
2749	struct net_device dev = (struct net_device ) data;	3532	struct net_device dev = (struct net_device ) data;
2750	struct fe_priv *np = netdev_priv(dev);	3533	struct fe_priv *np = get_nvpriv(dev);
2751	u8 __iomem *base = get_hwbase(dev);	3534	u8 __iomem *base = get_hwbase(dev);
2752	u32 mask = 0;	3535	u32 mask = 0;
2753		3536
Lines 2759-2807 Link Here
2759		3542
2760	if (!using_multi_irqs(dev)) {	3543	if (!using_multi_irqs(dev)) {
2761	if (np->msi_flags & NV_MSI_X_ENABLED)	3544	if (np->msi_flags & NV_MSI_X_ENABLED)
2762	disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);	3545	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2763	else	3546	else
2764	disable_irq_lockdep(dev->irq);	3547	disable_irq(dev->irq);
2765	mask = np->irqmask;	3548	mask = np->irqmask;
2766	} else {	3549	} else {
2767	if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {	3550	if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2768	disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);	3551	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2769	mask \|= NVREG_IRQ_RX_ALL;	3552	mask \|= NVREG_IRQ_RX_ALL;
2770	}	3553	}
2771	if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {	3554	if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2772	disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);	3555	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2773	mask \|= NVREG_IRQ_TX_ALL;	3556	mask \|= NVREG_IRQ_TX_ALL;
2774	}	3557	}
2775	if (np->nic_poll_irq & NVREG_IRQ_OTHER) {	3558	if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2776	disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);	3559	disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2777	mask \|= NVREG_IRQ_OTHER;	3560	mask \|= NVREG_IRQ_OTHER;
2778	}	3561	}
2779	}	3562	}
2780	np->nic_poll_irq = 0;	3563	np->nic_poll_irq = 0;
2781		3564
2782	/* FIXME: Do we need synchronize_irq(dev->irq) here? */	3565	if (np->recover_error) {
		3566	np->recover_error = 0;
		3567	printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
		3568	if (netif_running(dev)) {
		3569	netif_tx_lock_bh(dev);
		3570	spin_lock(&np->lock);
		3571	/* stop engines */
		3572	nv_stop_rx(dev);
		3573	nv_stop_tx(dev);
		3574	nv_txrx_reset(dev);
		3575	/* drain rx queue */
		3576	nv_drain_rx(dev);
		3577	nv_drain_tx(dev);
		3578	/* reinit driver view of the rx queue */
		3579	set_bufsize(dev);
		3580	if (nv_init_ring(dev)) {
		3581	if (!np->in_shutdown)
		3582	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
		3583	}
		3584	/* reinit nic view of the rx queue */
		3585	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
		3586	setup_hw_rings(dev, NV_SETUP_RX_RING \| NV_SETUP_TX_RING);
		3587	writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
		3588	base + NvRegRingSizes);
		3589	pci_push(base);
		3590	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
		3591	pci_push(base);
2783		3592
		3593	/* restart rx engine */
		3594	nv_start_rx(dev);
		3595	nv_start_tx(dev);
		3596	spin_unlock(&np->lock);
		3597	netif_tx_unlock_bh(dev);
		3598	}
		3599	}
		3600	/* FIXME: Do we need synchronize_irq(dev->irq) here? */
		3601
2784	writel(mask, base + NvRegIrqMask);	3602	writel(mask, base + NvRegIrqMask);
2785	pci_push(base);	3603	pci_push(base);
2786		3604
2787	if (!using_multi_irqs(dev)) {	3605	if (!using_multi_irqs(dev)) {
2788	nv_nic_irq(0, dev, NULL);	3606	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		3607	nv_nic_irq((int) 0, (void ) data, (struct pt_regs ) NULL);
		3608	else
		3609	nv_nic_irq_optimized((int) 0, (void ) data, (struct pt_regs ) NULL);
2789	if (np->msi_flags & NV_MSI_X_ENABLED)	3610	if (np->msi_flags & NV_MSI_X_ENABLED)
2790	enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);	3611	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2791	else	3612	else
2792	enable_irq_lockdep(dev->irq);	3613	enable_irq(dev->irq);
2793	} else {	3614	} else {
2794	if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {	3615	if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2795	nv_nic_irq_rx(0, dev, NULL);	3616	nv_nic_irq_rx((int) 0, (void ) data, (struct pt_regs ) NULL);
2796	enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);	3617	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2797	}	3618	}
2798	if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {	3619	if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2799	nv_nic_irq_tx(0, dev, NULL);	3620	nv_nic_irq_tx((int) 0, (void ) data, (struct pt_regs ) NULL);
2800	enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);	3621	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2801	}	3622	}
2802	if (np->nic_poll_irq & NVREG_IRQ_OTHER) {	3623	if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2803	nv_nic_irq_other(0, dev, NULL);	3624	nv_nic_irq_other((int) 0, (void ) data, (struct pt_regs ) NULL);
2804	enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);	3625	enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2805	}	3626	}
2806	}	3627	}
2807	}	3628	}
Lines 2816-2871 Link Here
2816	static void nv_do_stats_poll(unsigned long data)	3637	static void nv_do_stats_poll(unsigned long data)
2817	{	3638	{
2818	struct net_device dev = (struct net_device ) data;	3639	struct net_device dev = (struct net_device ) data;
2819	struct fe_priv *np = netdev_priv(dev);	3640	struct fe_priv *np = get_nvpriv(dev);
2820	u8 __iomem *base = get_hwbase(dev);	3641	u8 __iomem *base = get_hwbase(dev);
2821		3642
2822	np->estats.tx_bytes += readl(base + NvRegTxCnt);	3643	spin_lock_irq(&np->lock);
2823	np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);	3644
2824	np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);	3645	np->estats.tx_dropped = np->stats.tx_dropped;
2825	np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);	3646	if (np->driver_data & DEV_HAS_STATISTICS) {
2826	np->estats.tx_late_collision += readl(base + NvRegTxLateCol);	3647	np->estats.tx_packets += readl(base + NvRegTxFrame);
2827	np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);	3648	np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2828	np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);	3649	np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2829	np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);	3650	np->estats.tx_bytes += readl(base + NvRegTxCnt);
2830	np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);	3651	np->estats.rx_bytes += readl(base + NvRegRxCnt);
2831	np->estats.tx_deferral += readl(base + NvRegTxDef);	3652	np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2832	np->estats.tx_packets += readl(base + NvRegTxFrame);	3653	np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2833	np->estats.tx_pause += readl(base + NvRegTxPause);	3654
2834	np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);	3655	np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2835	np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);	3656	np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2836	np->estats.rx_late_collision += readl(base + NvRegRxLateCol);	3657	np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2837	np->estats.rx_runt += readl(base + NvRegRxRunt);	3658	np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2838	np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);	3659	np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2839	np->estats.rx_over_errors += readl(base + NvRegRxOverflow);	3660	np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2840	np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);	3661	np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2841	np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);	3662	np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2842	np->estats.rx_length_error += readl(base + NvRegRxLenErr);	3663	np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2843	np->estats.rx_unicast += readl(base + NvRegRxUnicast);	3664	np->estats.rx_runt += readl(base + NvRegRxRunt);
2844	np->estats.rx_multicast += readl(base + NvRegRxMulticast);	3665	np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2845	np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);	3666	np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2846	np->estats.rx_bytes += readl(base + NvRegRxCnt);	3667	np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2847	np->estats.rx_pause += readl(base + NvRegRxPause);	3668	np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2848	np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);	3669	np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2849	np->estats.rx_packets =	3670	np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2850	np->estats.rx_unicast +	3671	np->estats.tx_deferral += readl(base + NvRegTxDef);
2851	np->estats.rx_multicast +	3672	np->estats.tx_pause += readl(base + NvRegTxPause);
2852	np->estats.rx_broadcast;	3673	np->estats.rx_pause += readl(base + NvRegRxPause);
2853	np->estats.rx_errors_total =	3674	np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2854	np->estats.rx_crc_errors +	3675	np->estats.rx_packets =
2855	np->estats.rx_over_errors +	3676	np->estats.rx_unicast +
2856	np->estats.rx_frame_error +	3677	np->estats.rx_multicast +
2857	(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +	3678	np->estats.rx_broadcast;
2858	np->estats.rx_late_collision +	3679	np->estats.rx_errors_total =
2859	np->estats.rx_runt +	3680	np->estats.rx_crc_errors +
2860	np->estats.rx_frame_too_long;	3681	np->estats.rx_over_errors +
		3682	np->estats.rx_frame_error +
		3683	(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
		3684	np->estats.rx_late_collision +
		3685	np->estats.rx_runt +
		3686	np->estats.rx_frame_too_long +
		3687	np->rx_len_errors;
		3688
		3689	/* copy to net_device stats */
		3690	np->stats.tx_packets = np->estats.tx_packets;
		3691	np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
		3692	np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
		3693	np->stats.tx_bytes = np->estats.tx_bytes;
		3694	np->stats.rx_bytes = np->estats.rx_bytes;
		3695	np->stats.rx_crc_errors = np->estats.rx_crc_errors;
		3696	np->stats.rx_over_errors = np->estats.rx_over_errors;
		3697	np->stats.rx_packets = np->estats.rx_packets;
		3698	np->stats.rx_errors = np->estats.rx_errors_total;
		3699
		3700	} else {
		3701	np->estats.tx_packets = np->stats.tx_packets;
		3702	np->estats.tx_fifo_errors = np->stats.tx_fifo_errors;
		3703	np->estats.tx_carrier_errors = np->stats.tx_carrier_errors;
		3704	np->estats.tx_bytes = np->stats.tx_bytes;
		3705	np->estats.rx_bytes = np->stats.rx_bytes;
		3706	np->estats.rx_crc_errors = np->stats.rx_crc_errors;
		3707	np->estats.rx_over_errors = np->stats.rx_over_errors;
		3708	np->estats.rx_packets = np->stats.rx_packets;
		3709	np->estats.rx_errors_total = np->stats.rx_errors;
		3710	}
2861		3711
2862	if (!np->in_shutdown)	3712	if (!np->in_shutdown && netif_running(dev))
2863	mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);	3713	mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
		3714	spin_unlock_irq(&np->lock);
		3715	}
		3716
		3717	/*
		3718	* nv_get_stats: dev->get_stats function
		3719	* Get latest stats value from the nic.
		3720	* Called with read_lock(&dev_base_lock) held for read -
		3721	* only synchronized against unregister_netdevice.
		3722	*/
		3723	static struct net_device_stats nv_get_stats(struct net_device dev)
		3724	{
		3725	struct fe_priv *np = get_nvpriv(dev);
		3726
		3727	/* It seems that the nic always generates interrupts and doesn't
		3728	* accumulate errors internally. Thus the current values in np->stats
		3729	* are already up to date.
		3730	*/
		3731	nv_do_stats_poll((unsigned long)dev);
		3732	return &np->stats;
2864	}	3733	}
2865		3734
2866	static void nv_get_drvinfo(struct net_device dev, struct ethtool_drvinfo info)	3735	static void nv_get_drvinfo(struct net_device dev, struct ethtool_drvinfo info)
2867	{	3736	{
2868	struct fe_priv *np = netdev_priv(dev);	3737	struct fe_priv *np = get_nvpriv(dev);
2869	strcpy(info->driver, "forcedeth");	3738	strcpy(info->driver, "forcedeth");
2870	strcpy(info->version, FORCEDETH_VERSION);	3739	strcpy(info->version, FORCEDETH_VERSION);
2871	strcpy(info->bus_info, pci_name(np->pci_dev));	3740	strcpy(info->bus_info, pci_name(np->pci_dev));
Lines 2873-2879 Link Here
2873		3742
2874	static void nv_get_wol(struct net_device dev, struct ethtool_wolinfo wolinfo)	3743	static void nv_get_wol(struct net_device dev, struct ethtool_wolinfo wolinfo)
2875	{	3744	{
2876	struct fe_priv *np = netdev_priv(dev);	3745	struct fe_priv *np = get_nvpriv(dev);
2877	wolinfo->supported = WAKE_MAGIC;	3746	wolinfo->supported = WAKE_MAGIC;
2878		3747
2879	spin_lock_irq(&np->lock);	3748	spin_lock_irq(&np->lock);
Lines 2884-2890 Link Here
2884		3753
2885	static int nv_set_wol(struct net_device dev, struct ethtool_wolinfo wolinfo)	3754	static int nv_set_wol(struct net_device dev, struct ethtool_wolinfo wolinfo)
2886	{	3755	{
2887	struct fe_priv *np = netdev_priv(dev);	3756	struct fe_priv *np = get_nvpriv(dev);
2888	u8 __iomem *base = get_hwbase(dev);	3757	u8 __iomem *base = get_hwbase(dev);
2889	u32 flags = 0;	3758	u32 flags = 0;
2890		3759
Lines 2904-2910 Link Here
2904		3773
2905	static int nv_get_settings(struct net_device dev, struct ethtool_cmd ecmd)	3774	static int nv_get_settings(struct net_device dev, struct ethtool_cmd ecmd)
2906	{	3775	{
2907	struct fe_priv *np = netdev_priv(dev);	3776	struct fe_priv *np = get_nvpriv(dev);
2908	int adv;	3777	int adv;
2909		3778
2910	spin_lock_irq(&np->lock);	3779	spin_lock_irq(&np->lock);
Lines 2978-2985 Link Here
2978		3847
2979	static int nv_set_settings(struct net_device dev, struct ethtool_cmd ecmd)	3848	static int nv_set_settings(struct net_device dev, struct ethtool_cmd ecmd)
2980	{	3849	{
2981	struct fe_priv *np = netdev_priv(dev);	3850	struct fe_priv *np = get_nvpriv(dev);
2982		3851
		3852	dprintk(KERN_DEBUG "%s: nv_set_settings \n", dev->name);
2983	if (ecmd->port != PORT_MII)	3853	if (ecmd->port != PORT_MII)
2984	return -EINVAL;	3854	return -EINVAL;
2985	if (ecmd->transceiver != XCVR_EXTERNAL)	3855	if (ecmd->transceiver != XCVR_EXTERNAL)
Lines 3057-3065 Link Here
3057	if (netif_running(dev))	3927	if (netif_running(dev))
3058	printk(KERN_INFO "%s: link down.\n", dev->name);	3928	printk(KERN_INFO "%s: link down.\n", dev->name);
3059	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);	3929	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
		3930	if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
		3931	bmcr \|= BMCR_ANENABLE;
		3932	/* reset the phy in order for settings to stick,
		3933	* and cause autoneg to start */
		3934	if (phy_reset(dev, bmcr)) {
		3935	printk(KERN_INFO "%s: phy reset failed\n", dev->name);
		3936	return -EINVAL;
		3937	}
		3938	} else {
3060	bmcr \|= (BMCR_ANENABLE \| BMCR_ANRESTART);	3939	bmcr \|= (BMCR_ANENABLE \| BMCR_ANRESTART);
3061	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);	3940	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3062		3941	}
3063	} else {	3942	} else {
3064	int adv, bmcr;	3943	int adv, bmcr;
3065		3944
Lines 3099-3115 Link Here
3099	bmcr \|= BMCR_FULLDPLX;	3978	bmcr \|= BMCR_FULLDPLX;
3100	if (np->fixed_mode & (ADVERTISE_100HALF\|ADVERTISE_100FULL))	3979	if (np->fixed_mode & (ADVERTISE_100HALF\|ADVERTISE_100FULL))
3101	bmcr \|= BMCR_SPEED100;	3980	bmcr \|= BMCR_SPEED100;
3102	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3103	if (np->phy_oui == PHY_OUI_MARVELL) {	3981	if (np->phy_oui == PHY_OUI_MARVELL) {
3104	/* reset the phy */	3982	/* reset the phy in order for forced mode settings to stick */
3105	if (phy_reset(dev)) {	3983	if (phy_reset(dev, bmcr)) {
3106	printk(KERN_INFO "%s: phy reset failed\n", dev->name);	3984	printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3107	return -EINVAL;	3985	return -EINVAL;
3108	}	3986	}
3109	} else if (netif_running(dev)) {	3987	} else {
3110	/* Wait a bit and then reconfigure the nic. */	3988	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3111	udelay(10);	3989	if (netif_running(dev)) {
3112	nv_linkchange(dev);	3990	/* Wait a bit and then reconfigure the nic. */
		3991	udelay(10);
		3992	nv_linkchange(dev);
		3993	}
3113	}	3994	}
3114	}	3995	}
3115		3996
Lines 3126-3138 Link Here
3126		4007
3127	static int nv_get_regs_len(struct net_device *dev)	4008	static int nv_get_regs_len(struct net_device *dev)
3128	{	4009	{
3129	struct fe_priv *np = netdev_priv(dev);	4010	struct fe_priv *np = get_nvpriv(dev);
3130	return np->register_size;	4011	return np->register_size;
3131	}	4012	}
3132		4013
3133	static void nv_get_regs(struct net_device dev, struct ethtool_regs regs, void *buf)	4014	static void nv_get_regs(struct net_device dev, struct ethtool_regs regs, void *buf)
3134	{	4015	{
3135	struct fe_priv *np = netdev_priv(dev);	4016	struct fe_priv *np = get_nvpriv(dev);
3136	u8 __iomem *base = get_hwbase(dev);	4017	u8 __iomem *base = get_hwbase(dev);
3137	u32 *rbuf = buf;	4018	u32 *rbuf = buf;
3138	int i;	4019	int i;
Lines 3146-3152 Link Here
3146		4027
3147	static int nv_nway_reset(struct net_device *dev)	4028	static int nv_nway_reset(struct net_device *dev)
3148	{	4029	{
3149	struct fe_priv *np = netdev_priv(dev);	4030	struct fe_priv *np = get_nvpriv(dev);
3150	int ret;	4031	int ret;
3151		4032
3152	if (np->autoneg) {	4033	if (np->autoneg) {
Lines 3166-3173 Link Here
3166	}	4047	}
3167		4048
3168	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);	4049	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3169	bmcr \|= (BMCR_ANENABLE \| BMCR_ANRESTART);	4050	if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3170	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);	4051	bmcr \|= BMCR_ANENABLE;
		4052	/* reset the phy in order for settings to stick*/
		4053	if (phy_reset(dev, bmcr)) {
		4054	printk(KERN_INFO "%s: phy reset failed\n", dev->name);
		4055	return -EINVAL;
		4056	}
		4057	} else {
		4058	bmcr \|= (BMCR_ANENABLE \| BMCR_ANRESTART);
		4059	mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
		4060	}
3171		4061
3172	if (netif_running(dev)) {	4062	if (netif_running(dev)) {
3173	nv_start_rx(dev);	4063	nv_start_rx(dev);
Lines 3182-3200 Link Here
3182	return ret;	4072	return ret;
3183	}	4073	}
3184		4074
3185	static int nv_set_tso(struct net_device *dev, u32 value)
3186	{
3187	struct fe_priv *np = netdev_priv(dev);
3188
3189	if ((np->driver_data & DEV_HAS_CHECKSUM))
3190	return ethtool_op_set_tso(dev, value);
3191	else
3192	return -EOPNOTSUPP;
3193	}
3194
3195	static void nv_get_ringparam(struct net_device dev, struct ethtool_ringparam ring)	4075	static void nv_get_ringparam(struct net_device dev, struct ethtool_ringparam ring)
3196	{	4076	{
3197	struct fe_priv *np = netdev_priv(dev);	4077	struct fe_priv *np = get_nvpriv(dev);
3198		4078
3199	ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;	4079	ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3200	ring->rx_mini_max_pending = 0;	4080	ring->rx_mini_max_pending = 0;
Lines 3209-3228 Link Here
3209		4089
3210	static int nv_set_ringparam(struct net_device dev, struct ethtool_ringparam ring)	4090	static int nv_set_ringparam(struct net_device dev, struct ethtool_ringparam ring)
3211	{	4091	{
3212	struct fe_priv *np = netdev_priv(dev);	4092	struct fe_priv *np = get_nvpriv(dev);
3213	u8 __iomem *base = get_hwbase(dev);	4093	u8 __iomem *base = get_hwbase(dev);
3214	u8 rxtx_ring, rx_skbuff, tx_skbuff, rx_dma, tx_dma, tx_dma_len;	4094	u8 rxtx_ring, rx_skbuff, *tx_skbuff;
3215	dma_addr_t ring_addr;	4095	dma_addr_t ring_addr;
3216		4096
3217	if (ring->rx_pending < RX_RING_MIN \|\|	4097	if (ring->rx_pending < RX_RING_MIN \|\|
3218	ring->tx_pending < TX_RING_MIN \|\|	4098	ring->tx_pending < TX_RING_MIN \|\|
3219	ring->rx_mini_pending != 0 \|\|	4099	ring->rx_mini_pending != 0 \|\|
3220	ring->rx_jumbo_pending != 0 \|\|	4100	ring->rx_jumbo_pending != 0 \|\|
3221	(np->desc_ver == DESC_VER_1 &&	4101	(np->desc_ver == DESC_VER_1 &&
3222	(ring->rx_pending > RING_MAX_DESC_VER_1 \|\|	4102	(ring->rx_pending > RING_MAX_DESC_VER_1 \|\|
3223	ring->tx_pending > RING_MAX_DESC_VER_1)) \|\|	4103	ring->tx_pending > RING_MAX_DESC_VER_1)) \|\|
3224	(np->desc_ver != DESC_VER_1 &&	4104	(np->desc_ver != DESC_VER_1 &&
3225	(ring->rx_pending > RING_MAX_DESC_VER_2_3 \|\|	4105	(ring->rx_pending > RING_MAX_DESC_VER_2_3 \|\|
3226	ring->tx_pending > RING_MAX_DESC_VER_2_3))) {	4106	ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3227	return -EINVAL;	4107	return -EINVAL;
3228	}	4108	}
Lines 3237-3248 Link Here
3237	sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),	4117	sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3238	&ring_addr);	4118	&ring_addr);
3239	}	4119	}
3240	rx_skbuff = kmalloc(sizeof(struct sk_buff) ring->rx_pending, GFP_KERNEL);	4120	rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3241	rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);	4121	tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3242	tx_skbuff = kmalloc(sizeof(struct sk_buff) ring->tx_pending, GFP_KERNEL);	4122
3243	tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);	4123	if (!rxtx_ring \|\| !rx_skbuff \|\| !tx_skbuff) {
3244	tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3245	if (!rxtx_ring \|\| !rx_skbuff \|\| !rx_dma \|\| !tx_skbuff \|\| !tx_dma \|\| !tx_dma_len) {
3246	/* fall back to old rings */	4124	/* fall back to old rings */
3247	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	4125	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
3248	if(rxtx_ring)	4126	if(rxtx_ring)
Lines 3255-3268 Link Here
3255	}	4133	}
3256	if (rx_skbuff)	4134	if (rx_skbuff)
3257	kfree(rx_skbuff);	4135	kfree(rx_skbuff);
3258	if (rx_dma)
3259	kfree(rx_dma);
3260	if (tx_skbuff)	4136	if (tx_skbuff)
3261	kfree(tx_skbuff);	4137	kfree(tx_skbuff);
3262	if (tx_dma)
3263	kfree(tx_dma);
3264	if (tx_dma_len)
3265	kfree(tx_dma_len);
3266	goto exit;	4138	goto exit;
3267	}	4139	}
3268		4140
Lines 3280-3291 Link Here
3280	/* delete queues */	4152	/* delete queues */
3281	free_rings(dev);	4153	free_rings(dev);
3282	}	4154	}
3283		4155
3284	/* set new values */	4156	/* set new values */
3285	np->rx_ring_size = ring->rx_pending;	4157	np->rx_ring_size = ring->rx_pending;
3286	np->tx_ring_size = ring->tx_pending;	4158	np->tx_ring_size = ring->tx_pending;
3287	np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;	4159	np->tx_limit_stop =np->tx_ring_size - TX_LIMIT_DIFFERENCE;
3288	np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;	4160	np->tx_limit_start =np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
3289	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	4161	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
3290	np->rx_ring.orig = (struct ring_desc*)rxtx_ring;	4162	np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3291	np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];	4163	np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Lines 3293-3310 Link Here
3293	np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;	4165	np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3294	np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];	4166	np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3295	}	4167	}
3296	np->rx_skbuff = (struct sk_buff**)rx_skbuff;	4168	np->rx_skb = (struct nv_skb_map*)rx_skbuff;
3297	np->rx_dma = (dma_addr_t*)rx_dma;	4169	np->tx_skb = (struct nv_skb_map*)tx_skbuff;
3298	np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3299	np->tx_dma = (dma_addr_t*)tx_dma;
3300	np->tx_dma_len = (unsigned int*)tx_dma_len;
3301	np->ring_addr = ring_addr;	4170	np->ring_addr = ring_addr;
3302		4171
3303	memset(np->rx_skbuff, 0, sizeof(struct sk_buff) np->rx_ring_size);	4172	memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
3304	memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);	4173	memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
3305	memset(np->tx_skbuff, 0, sizeof(struct sk_buff) np->tx_ring_size);
3306	memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3307	memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3308		4174
3309	if (netif_running(dev)) {	4175	if (netif_running(dev)) {
3310	/* reinit driver view of the queues */	4176	/* reinit driver view of the queues */
Lines 3313-3319 Link Here
3313	if (!np->in_shutdown)	4179	if (!np->in_shutdown)
3314	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	4180	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3315	}	4181	}
3316		4182
3317	/* reinit nic view of the queues */	4183	/* reinit nic view of the queues */
3318	writel(np->rx_buf_sz, base + NvRegOffloadConfig);	4184	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3319	setup_hw_rings(dev, NV_SETUP_RX_RING \| NV_SETUP_TX_RING);	4185	setup_hw_rings(dev, NV_SETUP_RX_RING \| NV_SETUP_TX_RING);
Lines 3322-3328 Link Here
3322	pci_push(base);	4188	pci_push(base);
3323	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);	4189	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3324	pci_push(base);	4190	pci_push(base);
3325		4191
3326	/* restart engines */	4192	/* restart engines */
3327	nv_start_rx(dev);	4193	nv_start_rx(dev);
3328	nv_start_tx(dev);	4194	nv_start_tx(dev);
Lines 3337-3343 Link Here
3337		4203
3338	static void nv_get_pauseparam(struct net_device dev, struct ethtool_pauseparam pause)	4204	static void nv_get_pauseparam(struct net_device dev, struct ethtool_pauseparam pause)
3339	{	4205	{
3340	struct fe_priv *np = netdev_priv(dev);	4206	struct fe_priv *np = get_nvpriv(dev);
3341		4207
3342	pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;	4208	pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3343	pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;	4209	pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
Lines 3346-3357 Link Here
3346		4212
3347	static int nv_set_pauseparam(struct net_device dev, struct ethtool_pauseparam pause)	4213	static int nv_set_pauseparam(struct net_device dev, struct ethtool_pauseparam pause)
3348	{	4214	{
3349	struct fe_priv *np = netdev_priv(dev);	4215	struct fe_priv *np = get_nvpriv(dev);
3350	int adv, bmcr;	4216	int adv, bmcr;
3351		4217
3352	if ((!np->autoneg && np->duplex == 0) \|\|	4218	if ((!np->autoneg && np->duplex == 0) \|\|
3353	(np->autoneg && !pause->autoneg && np->duplex == 0)) {	4219	(np->autoneg && !pause->autoneg && np->duplex == 0)) {
3354	printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",	4220	printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3355	dev->name);	4221	dev->name);
3356	return -EINVAL;	4222	return -EINVAL;
3357	}	4223	}
Lines 3417-3447 Link Here
3417		4283
3418	static u32 nv_get_rx_csum(struct net_device *dev)	4284	static u32 nv_get_rx_csum(struct net_device *dev)
3419	{	4285	{
3420	struct fe_priv *np = netdev_priv(dev);	4286	struct fe_priv *np = get_nvpriv(dev);
3421	return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;	4287	return (np->rx_csum) != 0;
3422	}	4288	}
3423		4289
3424	static int nv_set_rx_csum(struct net_device *dev, u32 data)	4290	static int nv_set_rx_csum(struct net_device *dev, u32 data)
3425	{	4291	{
3426	struct fe_priv *np = netdev_priv(dev);	4292	struct fe_priv *np = get_nvpriv(dev);
3427	u8 __iomem *base = get_hwbase(dev);	4293	u8 __iomem *base = get_hwbase(dev);
3428	int retcode = 0;	4294	int retcode = 0;
3429		4295
3430	if (np->driver_data & DEV_HAS_CHECKSUM) {	4296	if (np->driver_data & DEV_HAS_CHECKSUM) {
3431		4297
3432	if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) \|\|
3433	(!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3434	/* already set or unset */
3435	return 0;
3436	}
3437
3438	if (data) {	4298	if (data) {
		4299	np->rx_csum = 1;
3439	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;	4300	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;
3440	} else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3441	np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3442	} else {	4301	} else {
3443	printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");	4302	np->rx_csum = 0;
3444	return -EINVAL;	4303	/* vlan is dependent on rx checksum offload */
		4304	if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
		4305	np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3445	}	4306	}
3446		4307
3447	if (netif_running(dev)) {	4308	if (netif_running(dev)) {
Lines 3456-3494 Link Here
3456	return retcode;	4317	return retcode;
3457	}	4318	}
3458		4319
3459	static int nv_set_tx_csum(struct net_device *dev, u32 data)	4320	#ifdef NETIF_F_TSO
		4321	static int nv_set_tso(struct net_device *dev, u32 data)
3460	{	4322	{
3461	struct fe_priv *np = netdev_priv(dev);	4323	struct fe_priv *np = get_nvpriv(dev);
3462		4324
3463	if (np->driver_data & DEV_HAS_CHECKSUM)	4325	if (np->driver_data & DEV_HAS_CHECKSUM){
3464	return ethtool_op_set_tx_hw_csum(dev, data);	4326	return ethtool_op_set_tso(dev, data);
3465	else	4327	}else
3466	return -EOPNOTSUPP;	4328	return -EINVAL;
3467	}	4329	}
		4330	#endif
3468		4331
3469	static int nv_set_sg(struct net_device *dev, u32 data)	4332	static int nv_set_sg(struct net_device *dev, u32 data)
3470	{	4333	{
3471	struct fe_priv *np = netdev_priv(dev);	4334	struct fe_priv *np = get_nvpriv(dev);
		4335
		4336	if (np->driver_data & DEV_HAS_CHECKSUM){
		4337	return ethtool_op_set_sg(dev, data);
		4338	}else
		4339	return -EINVAL;
		4340	}
		4341
		4342	static int nv_set_tx_csum(struct net_device *dev, u32 data)
		4343	{
		4344	struct fe_priv *np = get_nvpriv(dev);
3472		4345
3473	if (np->driver_data & DEV_HAS_CHECKSUM)	4346	if (np->driver_data & DEV_HAS_CHECKSUM)
3474	return ethtool_op_set_sg(dev, data);	4347	return ethtool_op_set_tx_hw_csum(dev, data);
3475	else	4348	else
3476	return -EOPNOTSUPP;	4349	return -EINVAL;
3477	}	4350	}
3478		4351
3479	static int nv_get_stats_count(struct net_device *dev)	4352	static int nv_get_stats_count(struct net_device *dev)
3480	{	4353	{
3481	struct fe_priv *np = netdev_priv(dev);	4354	struct fe_priv *np = get_nvpriv(dev);
3482		4355
3483	if (np->driver_data & DEV_HAS_STATISTICS)	4356	if (np->driver_data & DEV_HAS_STATISTICS)
3484	return (sizeof(struct nv_ethtool_stats)/sizeof(u64));	4357	return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3485	else	4358	else
3486	return 0;	4359	return NV_STATS_COUNT_SW;
3487	}	4360	}
3488		4361
3489	static void nv_get_ethtool_stats(struct net_device dev, struct ethtool_stats estats, u64 *buffer)	4362	static void nv_get_ethtool_stats(struct net_device dev, struct ethtool_stats estats, u64 *buffer)
3490	{	4363	{
3491	struct fe_priv *np = netdev_priv(dev);	4364	struct fe_priv *np = get_nvpriv(dev);
3492		4365
3493	/* update stats */	4366	/* update stats */
3494	nv_do_stats_poll((unsigned long)dev);	4367	nv_do_stats_poll((unsigned long)dev);
Lines 3498-3504 Link Here
3498		4371
3499	static int nv_self_test_count(struct net_device *dev)	4372	static int nv_self_test_count(struct net_device *dev)
3500	{	4373	{
3501	struct fe_priv *np = netdev_priv(dev);	4374	struct fe_priv *np = get_nvpriv(dev);
3502		4375
3503	if (np->driver_data & DEV_HAS_TEST_EXTENDED)	4376	if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3504	return NV_TEST_COUNT_EXTENDED;	4377	return NV_TEST_COUNT_EXTENDED;
Lines 3508-3514 Link Here
3508		4381
3509	static int nv_link_test(struct net_device *dev)	4382	static int nv_link_test(struct net_device *dev)
3510	{	4383	{
3511	struct fe_priv *np = netdev_priv(dev);	4384	struct fe_priv *np = get_nvpriv(dev);
3512	int mii_status;	4385	int mii_status;
3513		4386
3514	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);	4387	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
Lines 3551-3557 Link Here
3551		4424
3552	static int nv_interrupt_test(struct net_device *dev)	4425	static int nv_interrupt_test(struct net_device *dev)
3553	{	4426	{
3554	struct fe_priv *np = netdev_priv(dev);	4427	struct fe_priv *np = get_nvpriv(dev);
3555	u8 __iomem *base = get_hwbase(dev);	4428	u8 __iomem *base = get_hwbase(dev);
3556	int ret = 1;	4429	int ret = 1;
3557	int testcnt;	4430	int testcnt;
Lines 3580-3586 Link Here
3580	nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);	4453	nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3581		4454
3582	/* wait for at least one interrupt */	4455	/* wait for at least one interrupt */
3583	msleep(100);	4456	nv_msleep(100);
3584		4457
3585	spin_lock_irq(&np->lock);	4458	spin_lock_irq(&np->lock);
3586		4459
Lines 3614-3620 Link Here
3614		4487
3615	static int nv_loopback_test(struct net_device *dev)	4488	static int nv_loopback_test(struct net_device *dev)
3616	{	4489	{
3617	struct fe_priv *np = netdev_priv(dev);	4490	struct fe_priv *np = get_nvpriv(dev);
3618	u8 __iomem *base = get_hwbase(dev);	4491	u8 __iomem *base = get_hwbase(dev);
3619	struct sk_buff tx_skb, rx_skb;	4492	struct sk_buff tx_skb, rx_skb;
3620	dma_addr_t test_dma_addr;	4493	dma_addr_t test_dma_addr;
Lines 3673-3685 Link Here
3673	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);	4546	writel(NVREG_TXRXCTL_KICK\|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3674	pci_push(get_hwbase(dev));	4547	pci_push(get_hwbase(dev));
3675		4548
3676	msleep(500);	4549	nv_msleep(500);
3677		4550
3678	/* check for rx of the packet */	4551	/* check for rx of the packet */
3679	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	4552	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
3680	Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);	4553	Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3681	len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);	4554	len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3682		4555
3683	} else {	4556	} else {
3684	Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);	4557	Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3685	len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);	4558	len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
Lines 3696-3712 Link Here
3696	}	4569	}
3697	}	4570	}
3698		4571
3699	if (ret) {	4572	if (ret) {
3700	if (len != pkt_len) {	4573	if (len != pkt_len) {
3701	ret = 0;	4574	ret = 0;
3702	dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",	4575	dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3703	dev->name, len, pkt_len);	4576	dev->name, len, pkt_len);
3704	} else {	4577	} else {
3705	rx_skb = np->rx_skbuff[0];	4578	rx_skb = np->rx_skb[0].skb;
3706	for (i = 0; i < pkt_len; i++) {	4579	for (i = 0; i < pkt_len; i++) {
3707	if (rx_skb->data[i] != (u8)(i & 0xff)) {	4580	if (rx_skb->data[i] != (u8)(i & 0xff)) {
3708	ret = 0;	4581	ret = 0;
3709	dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",	4582	dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3710	dev->name, i);	4583	dev->name, i);
3711	break;	4584	break;
3712	}	4585	}
Lines 3720-3726 Link Here
3720	tx_skb->end-tx_skb->data,	4593	tx_skb->end-tx_skb->data,
3721	PCI_DMA_TODEVICE);	4594	PCI_DMA_TODEVICE);
3722	dev_kfree_skb_any(tx_skb);	4595	dev_kfree_skb_any(tx_skb);
3723		4596
3724	/* stop engines */	4597	/* stop engines */
3725	nv_stop_rx(dev);	4598	nv_stop_rx(dev);
3726	nv_stop_tx(dev);	4599	nv_stop_tx(dev);
Lines 3740-3746 Link Here
3740		4613
3741	static void nv_self_test(struct net_device dev, struct ethtool_test test, u64 *buffer)	4614	static void nv_self_test(struct net_device dev, struct ethtool_test test, u64 *buffer)
3742	{	4615	{
3743	struct fe_priv *np = netdev_priv(dev);	4616	struct fe_priv *np = get_nvpriv(dev);
3744	u8 __iomem *base = get_hwbase(dev);	4617	u8 __iomem *base = get_hwbase(dev);
3745	int result;	4618	int result;
3746	memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));	4619	memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
Lines 3839-3846 Link Here
3839	.get_regs = nv_get_regs,	4712	.get_regs = nv_get_regs,
3840	.nway_reset = nv_nway_reset,	4713	.nway_reset = nv_nway_reset,
3841	.get_perm_addr = ethtool_op_get_perm_addr,	4714	.get_perm_addr = ethtool_op_get_perm_addr,
3842	.get_tso = ethtool_op_get_tso,
3843	.set_tso = nv_set_tso,
3844	.get_ringparam = nv_get_ringparam,	4715	.get_ringparam = nv_get_ringparam,
3845	.set_ringparam = nv_set_ringparam,	4716	.set_ringparam = nv_set_ringparam,
3846	.get_pauseparam = nv_get_pauseparam,	4717	.get_pauseparam = nv_get_pauseparam,
Lines 3851-3856 Link Here
3851	.set_tx_csum = nv_set_tx_csum,	4722	.set_tx_csum = nv_set_tx_csum,
3852	.get_sg = ethtool_op_get_sg,	4723	.get_sg = ethtool_op_get_sg,
3853	.set_sg = nv_set_sg,	4724	.set_sg = nv_set_sg,
		4725	#ifdef NETIF_F_TSO
		4726	.get_tso = ethtool_op_get_tso,
		4727	.set_tso = nv_set_tso,
		4728	#endif
3854	.get_strings = nv_get_strings,	4729	.get_strings = nv_get_strings,
3855	.get_stats_count = nv_get_stats_count,	4730	.get_stats_count = nv_get_stats_count,
3856	.get_ethtool_stats = nv_get_ethtool_stats,	4731	.get_ethtool_stats = nv_get_ethtool_stats,
Lines 3870-3879 Link Here
3870	if (grp) {	4745	if (grp) {
3871	/* enable vlan on MAC */	4746	/* enable vlan on MAC */
3872	np->txrxctl_bits \|= NVREG_TXRXCTL_VLANSTRIP \| NVREG_TXRXCTL_VLANINS;	4747	np->txrxctl_bits \|= NVREG_TXRXCTL_VLANSTRIP \| NVREG_TXRXCTL_VLANINS;
		4748	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;
3873	} else {	4749	} else {
3874	/* disable vlan on MAC */	4750	/* disable vlan on MAC */
3875	np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;	4751	np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3876	np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;	4752	np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
		4753	if (!np->rx_csum)
		4754	np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3877	}	4755	}
3878		4756
3879	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);	4757	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Lines 3886-3938 Link Here
3886	/* nothing to do */	4764	/* nothing to do */
3887	};	4765	};
3888		4766
		4767	/* The mgmt unit and driver use a semaphore to access the phy during init */
		4768	static int nv_mgmt_acquire_sema(struct net_device *dev)
		4769	{
		4770	u8 __iomem *base = get_hwbase(dev);
		4771	int i;
		4772	u32 tx_ctrl, mgmt_sema;
		4773
		4774	for (i = 0; i < 10; i++) {
		4775	mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
		4776	if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) {
		4777	dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: sema is free\n");
		4778	break;
		4779	}
		4780	nv_msleep(500);
		4781	}
		4782
		4783	if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) {
		4784	dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: sema is not free\n");
		4785	return 0;
		4786	}
		4787
		4788	for (i = 0; i < 2; i++) {
		4789	tx_ctrl = readl(base + NvRegTransmitterControl);
		4790	tx_ctrl \|= NVREG_XMITCTL_HOST_SEMA_ACQ;
		4791	writel(tx_ctrl, base + NvRegTransmitterControl);
		4792
		4793	/* verify that semaphore was acquired */
		4794	tx_ctrl = readl(base + NvRegTransmitterControl);
		4795	if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
		4796	((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
		4797	dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: acquired sema\n");
		4798	return 1;
		4799	} else
		4800	udelay(50);
		4801	}
		4802
		4803	dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: exit\n");
		4804	return 0;
		4805	}
		4806
		4807	/* Indicate to mgmt unit whether driver is loaded or not */
		4808	static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
		4809	{
		4810	u8 __iomem *base = get_hwbase(dev);
		4811	u32 tx_ctrl;
		4812
		4813	tx_ctrl = readl(base + NvRegTransmitterControl);
		4814	if (loaded)
		4815	tx_ctrl \|= NVREG_XMITCTL_HOST_LOADED;
		4816	else
		4817	tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
		4818	writel(tx_ctrl, base + NvRegTransmitterControl);
		4819	}
		4820
3889	static int nv_open(struct net_device *dev)	4821	static int nv_open(struct net_device *dev)
3890	{	4822	{
3891	struct fe_priv *np = netdev_priv(dev);	4823	struct fe_priv *np = get_nvpriv(dev);
3892	u8 __iomem *base = get_hwbase(dev);	4824	u8 __iomem *base = get_hwbase(dev);
3893	int ret = 1;	4825	int ret = 1;
3894	int oom, i;	4826	int oom, i;
3895		4827
3896	dprintk(KERN_DEBUG "nv_open: begin\n");	4828	dprintk(KERN_DEBUG "nv_open: begin\n");
3897		4829
3898	/* 1) erase previous misconfiguration */	4830	/* erase previous misconfiguration */
3899	if (np->driver_data & DEV_HAS_POWER_CNTRL)	4831	if (np->driver_data & DEV_HAS_POWER_CNTRL)
3900	nv_mac_reset(dev);	4832	nv_mac_reset(dev);
3901	/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */	4833	/* stop adapter: ignored, 4.3 seems to be overkill */
3902	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);	4834	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3903	writel(0, base + NvRegMulticastAddrB);	4835	writel(0, base + NvRegMulticastAddrB);
3904	writel(0, base + NvRegMulticastMaskA);	4836	writel(0, base + NvRegMulticastMaskA);
3905	writel(0, base + NvRegMulticastMaskB);	4837	writel(0, base + NvRegMulticastMaskB);
3906	writel(0, base + NvRegPacketFilterFlags);	4838	writel(0, base + NvRegPacketFilterFlags);
3907		4839
3908	writel(0, base + NvRegTransmitterControl);	4840	nv_stop_tx(dev);
3909	writel(0, base + NvRegReceiverControl);	4841	nv_stop_rx(dev);
3910		4842
3911	writel(0, base + NvRegAdapterControl);	4843	writel(0, base + NvRegAdapterControl);
3912		4844
3913	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)	4845	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3914	writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);	4846	writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3915		4847
3916	/* 2) initialize descriptor rings */	4848	/* initialize descriptor rings */
3917	set_bufsize(dev);	4849	set_bufsize(dev);
3918	oom = nv_init_ring(dev);	4850	oom = nv_init_ring(dev);
3919		4851
3920	writel(0, base + NvRegLinkSpeed);
3921	writel(0, base + NvRegUnknownTransmitterReg);
3922	nv_txrx_reset(dev);	4852	nv_txrx_reset(dev);
3923	writel(0, base + NvRegUnknownSetupReg6);	4853	writel(0, base + NvRegUnknownSetupReg6);
3924		4854
3925	np->in_shutdown = 0;	4855	np->in_shutdown = 0;
3926		4856
3927	/* 3) set mac address */	4857	/* give hw rings */
3928	nv_copy_mac_to_hw(dev);
3929
3930	/* 4) give hw rings */
3931	setup_hw_rings(dev, NV_SETUP_RX_RING \| NV_SETUP_TX_RING);	4858	setup_hw_rings(dev, NV_SETUP_RX_RING \| NV_SETUP_TX_RING);
3932	writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),	4859	writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3933	base + NvRegRingSizes);	4860	base + NvRegRingSizes);
3934		4861
3935	/* 5) continue setup */	4862	/* continue setup */
3936	writel(np->linkspeed, base + NvRegLinkSpeed);	4863	writel(np->linkspeed, base + NvRegLinkSpeed);
3937	if (np->desc_ver == DESC_VER_1)	4864	if (np->desc_ver == DESC_VER_1)
3938	writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);	4865	writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
Lines 3946-3956 Link Here
3946	NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,	4873	NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3947	KERN_INFO "open: SetupReg5, Bit 31 remained off\n");	4874	KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3948		4875
3949	writel(0, base + NvRegUnknownSetupReg4);	4876	writel(0, base + NvRegMIIMask);
3950	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);	4877	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3951	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);	4878	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3952		4879
3953	/* 6) continue setup */	4880	/* continue setup */
3954	writel(NVREG_MISC1_FORCE \| NVREG_MISC1_HD, base + NvRegMisc1);	4881	writel(NVREG_MISC1_FORCE \| NVREG_MISC1_HD, base + NvRegMisc1);
3955	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);	4882	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3956	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);	4883	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Lines 3973-3979 Link Here
3973	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)\|NVREG_ADAPTCTL_PHYVALID\|NVREG_ADAPTCTL_RUNNING,	4900	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)\|NVREG_ADAPTCTL_PHYVALID\|NVREG_ADAPTCTL_RUNNING,
3974	base + NvRegAdapterControl);	4901	base + NvRegAdapterControl);
3975	writel(NVREG_MIISPEED_BIT8\|NVREG_MIIDELAY, base + NvRegMIISpeed);	4902	writel(NVREG_MIISPEED_BIT8\|NVREG_MIIDELAY, base + NvRegMIISpeed);
3976	writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);	4903	writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
3977	if (np->wolenabled)	4904	if (np->wolenabled)
3978	writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);	4905	writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3979		4906
Lines 4023-4037 Link Here
4023	if (ret) {	4950	if (ret) {
4024	netif_carrier_on(dev);	4951	netif_carrier_on(dev);
4025	} else {	4952	} else {
4026	printk("%s: no link during initialization.\n", dev->name);	4953	dprintk(KERN_DEBUG "%s: no link during initialization.\n", dev->name);
4027	netif_carrier_off(dev);	4954	netif_carrier_off(dev);
4028	}	4955	}
4029	if (oom)	4956	if (oom)
4030	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	4957	mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4031		4958
4032	/* start statistics timer */	4959	/* start statistics timer */
4033	if (np->driver_data & DEV_HAS_STATISTICS)	4960	mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4034	mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4035		4961
4036	spin_unlock_irq(&np->lock);	4962	spin_unlock_irq(&np->lock);
4037		4963
Lines 4043-4054 Link Here
4043		4969
4044	static int nv_close(struct net_device *dev)	4970	static int nv_close(struct net_device *dev)
4045	{	4971	{
4046	struct fe_priv *np = netdev_priv(dev);	4972	struct fe_priv *np = get_nvpriv(dev);
4047	u8 __iomem *base;	4973	u8 __iomem *base;
4048		4974
		4975	dprintk(KERN_DEBUG "nv_close: begin\n");
4049	spin_lock_irq(&np->lock);	4976	spin_lock_irq(&np->lock);
4050	np->in_shutdown = 1;	4977	np->in_shutdown = 1;
4051	spin_unlock_irq(&np->lock);	4978	spin_unlock_irq(&np->lock);
		4979
4052	synchronize_irq(dev->irq);	4980	synchronize_irq(dev->irq);
4053		4981
4054	del_timer_sync(&np->oom_kick);	4982	del_timer_sync(&np->oom_kick);
Lines 4076-4087 Link Here
4076	if (np->wolenabled)	5004	if (np->wolenabled)
4077	nv_start_rx(dev);	5005	nv_start_rx(dev);
4078		5006
4079	/* special op: write back the misordered MAC address - otherwise
4080	* the next nv_probe would see a wrong address.
4081	*/
4082	writel(np->orig_mac[0], base + NvRegMacAddrA);
4083	writel(np->orig_mac[1], base + NvRegMacAddrB);
4084
4085	/* FIXME: power down nic */	5007	/* FIXME: power down nic */
4086		5008
4087	return 0;	5009	return 0;
Lines 4094-4107 Link Here
4094	unsigned long addr;	5016	unsigned long addr;
4095	u8 __iomem *base;	5017	u8 __iomem *base;
4096	int err, i;	5018	int err, i;
4097	u32 powerstate;	5019	u32 powerstate, phystate_orig = 0, phystate, txreg;
		5020	int phyinitialized = 0;
4098		5021
		5022	//NVLAN_DISABLE_ALL_FEATURES ;
		5023	/* modify network device class id */
		5024	quirk_nforce_network_class(pci_dev);
4099	dev = alloc_etherdev(sizeof(struct fe_priv));	5025	dev = alloc_etherdev(sizeof(struct fe_priv));
4100	err = -ENOMEM;	5026	err = -ENOMEM;
4101	if (!dev)	5027	if (!dev)
4102	goto out;	5028	goto out;
4103		5029
4104	np = netdev_priv(dev);	5030	dprintk(KERN_DEBUG "%s:nv_probe: begin\n",dev->name);
		5031	np = get_nvpriv(dev);
4105	np->pci_dev = pci_dev;	5032	np->pci_dev = pci_dev;
4106	spin_lock_init(&np->lock);	5033	spin_lock_init(&np->lock);
4107	SET_MODULE_OWNER(dev);	5034	SET_MODULE_OWNER(dev);
Lines 4188-4208 Link Here
4188	np->pkt_limit = NV_PKTLIMIT_1;	5115	np->pkt_limit = NV_PKTLIMIT_1;
4189	if (id->driver_data & DEV_HAS_LARGEDESC)	5116	if (id->driver_data & DEV_HAS_LARGEDESC)
4190	np->pkt_limit = NV_PKTLIMIT_2;	5117	np->pkt_limit = NV_PKTLIMIT_2;
		5118	if (mtu > np->pkt_limit) {
		5119	printk(KERN_INFO "forcedeth: MTU value of %d is too large. Setting to maximum value of %d\n",
		5120	mtu, np->pkt_limit);
		5121	dev->mtu = np->pkt_limit;
		5122	} else {
		5123	dev->mtu = mtu;
		5124	}
4191		5125
4192	if (id->driver_data & DEV_HAS_CHECKSUM) {	5126	if (id->driver_data & DEV_HAS_CHECKSUM) {
4193	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;	5127	if (rx_checksum_offload) {
4194	dev->features \|= NETIF_F_HW_CSUM \| NETIF_F_SG;	5128	np->rx_csum = 1;
		5129	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;
		5130	}
		5131
		5132	if (tx_checksum_offload)
		5133	dev->features \|= NETIF_F_HW_CSUM;
		5134
		5135	if (scatter_gather)
		5136	dev->features \|= NETIF_F_SG;
4195	#ifdef NETIF_F_TSO	5137	#ifdef NETIF_F_TSO
4196	dev->features \|= NETIF_F_TSO;	5138	if (tso_offload)
		5139	dev->features \|= NETIF_F_TSO;
4197	#endif	5140	#endif
4198	}	5141	}
4199		5142
4200	np->vlanctl_bits = 0;	5143	np->vlanctl_bits = 0;
4201	if (id->driver_data & DEV_HAS_VLAN) {	5144	if (id->driver_data & DEV_HAS_VLAN && tagging_8021pq) {
4202	np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;	5145	np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4203	dev->features \|= NETIF_F_HW_VLAN_RX \| NETIF_F_HW_VLAN_TX;	5146	dev->features \|= NETIF_F_HW_VLAN_RX \| NETIF_F_HW_VLAN_TX;
4204	dev->vlan_rx_register = nv_vlan_rx_register;	5147	dev->vlan_rx_register = nv_vlan_rx_register;
4205	dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;	5148	dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
		5149	/* vlan needs rx checksum support, so force it */
		5150	np->txrxctl_bits \|= NVREG_TXRXCTL_RXCHECK;
4206	}	5151	}
4207		5152
4208	np->msi_flags = 0;	5153	np->msi_flags = 0;
Lines 4212-4223 Link Here
4212	if ((id->driver_data & DEV_HAS_MSI_X) && msix) {	5157	if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4213	np->msi_flags \|= NV_MSI_X_CAPABLE;	5158	np->msi_flags \|= NV_MSI_X_CAPABLE;
4214	}	5159	}
4215		5160
4216	np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE \| NV_PAUSEFRAME_RX_REQ \| NV_PAUSEFRAME_AUTONEG;	5161	np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE;
		5162	if (rx_flow_control == NV_RX_FLOW_CONTROL_ENABLED)
		5163	np->pause_flags \|= NV_PAUSEFRAME_RX_REQ;
4217	if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {	5164	if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4218	np->pause_flags \|= NV_PAUSEFRAME_TX_CAPABLE \| NV_PAUSEFRAME_TX_REQ;	5165	np->pause_flags \|= NV_PAUSEFRAME_TX_CAPABLE;
		5166	if (tx_flow_control == NV_TX_FLOW_CONTROL_ENABLED)
		5167	np->pause_flags \|= NV_PAUSEFRAME_TX_REQ;
		5168	}
		5169	if (autoneg == AUTONEG_ENABLE) {
		5170	np->pause_flags \|= NV_PAUSEFRAME_AUTONEG;
		5171	} else if (speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX) {
		5172	printk(KERN_INFO "forcedeth: speed_duplex of 1000 full can not enabled if autoneg is disabled\n");
		5173	goto out_relreg;
4219	}	5174	}
4220
4221		5175
4222	err = -ENOMEM;	5176	err = -ENOMEM;
4223	np->base = ioremap(addr, np->register_size);	5177	np->base = ioremap(addr, np->register_size);
Lines 4227-4236 Link Here
4227		5181
4228	dev->irq = pci_dev->irq;	5182	dev->irq = pci_dev->irq;
4229		5183
4230	np->rx_ring_size = RX_RING_DEFAULT;	5184	if (np->desc_ver == DESC_VER_1) {
4231	np->tx_ring_size = TX_RING_DEFAULT;	5185	if (rx_ring_size > RING_MAX_DESC_VER_1) {
4232	np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;	5186	printk(KERN_INFO "forcedeth: rx_ring_size of %d is too large. Setting to maximum of %d\n",
4233	np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;	5187	rx_ring_size, RING_MAX_DESC_VER_1);
		5188	rx_ring_size = RING_MAX_DESC_VER_1;
		5189	}
		5190	if (tx_ring_size > RING_MAX_DESC_VER_1) {
		5191	printk(KERN_INFO "forcedeth: tx_ring_size of %d is too large. Setting to maximum of %d\n",
		5192	tx_ring_size, RING_MAX_DESC_VER_1);
		5193	tx_ring_size = RING_MAX_DESC_VER_1;
		5194	}
		5195	} else {
		5196	if (rx_ring_size > RING_MAX_DESC_VER_2_3) {
		5197	printk(KERN_INFO "forcedeth: rx_ring_size of %d is too large. Setting to maximum of %d\n",
		5198	rx_ring_size, RING_MAX_DESC_VER_2_3);
		5199	rx_ring_size = RING_MAX_DESC_VER_2_3;
		5200	}
		5201	if (tx_ring_size > RING_MAX_DESC_VER_2_3) {
		5202	printk(KERN_INFO "forcedeth: tx_ring_size of %d is too large. Setting to maximum of %d\n",
		5203	tx_ring_size, RING_MAX_DESC_VER_2_3);
		5204	tx_ring_size = RING_MAX_DESC_VER_2_3;
		5205	}
		5206	}
		5207	np->rx_ring_size = rx_ring_size;
		5208	np->tx_ring_size = tx_ring_size;
		5209	np->tx_limit_stop = tx_ring_size - TX_LIMIT_DIFFERENCE;
		5210	np->tx_limit_start = tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4234		5211
4235	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {	5212	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2) {
4236	np->rx_ring.orig = pci_alloc_consistent(pci_dev,	5213	np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Lines 4247-4275 Link Here
4247	goto out_unmap;	5224	goto out_unmap;
4248	np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];	5225	np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4249	}	5226	}
4250	np->rx_skbuff = kmalloc(sizeof(struct sk_buff) np->rx_ring_size, GFP_KERNEL);	5227	np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4251	np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);	5228	np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4252	np->tx_skbuff = kmalloc(sizeof(struct sk_buff) np->tx_ring_size, GFP_KERNEL);	5229	if (!np->rx_skb \|\| !np->tx_skb)
4253	np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4254	np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4255	if (!np->rx_skbuff \|\| !np->rx_dma \|\| !np->tx_skbuff \|\| !np->tx_dma \|\| !np->tx_dma_len)
4256	goto out_freering;	5230	goto out_freering;
4257	memset(np->rx_skbuff, 0, sizeof(struct sk_buff) np->rx_ring_size);	5231	memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4258	memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);	5232	memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4259	memset(np->tx_skbuff, 0, sizeof(struct sk_buff) np->tx_ring_size);
4260	memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4261	memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4262		5233
4263	dev->open = nv_open;	5234	dev->open = nv_open;
4264	dev->stop = nv_close;	5235	dev->stop = nv_close;
4265	dev->hard_start_xmit = nv_start_xmit;	5236	if (np->desc_ver == DESC_VER_1 \|\| np->desc_ver == DESC_VER_2)
		5237	dev->hard_start_xmit = nv_start_xmit;
		5238	else
		5239	dev->hard_start_xmit = nv_start_xmit_optimized;
4266	dev->get_stats = nv_get_stats;	5240	dev->get_stats = nv_get_stats;
4267	dev->change_mtu = nv_change_mtu;	5241	dev->change_mtu = nv_change_mtu;
4268	dev->set_mac_address = nv_set_mac_address;	5242	dev->set_mac_address = nv_set_mac_address;
4269	dev->set_multicast_list = nv_set_multicast;	5243	dev->set_multicast_list = nv_set_multicast;
		5244
4270	#ifdef CONFIG_NET_POLL_CONTROLLER	5245	#ifdef CONFIG_NET_POLL_CONTROLLER
4271	dev->poll_controller = nv_poll_controller;	5246	dev->poll_controller = nv_poll_controller;
4272	#endif	5247	#endif
		5248
4273	SET_ETHTOOL_OPS(dev, &ops);	5249	SET_ETHTOOL_OPS(dev, &ops);
4274	dev->tx_timeout = nv_tx_timeout;	5250	dev->tx_timeout = nv_tx_timeout;
4275	dev->watchdog_timeo = NV_WATCHDOG_TIMEO;	5251	dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
Lines 4281-4292 Link Here
4281	np->orig_mac[0] = readl(base + NvRegMacAddrA);	5257	np->orig_mac[0] = readl(base + NvRegMacAddrA);
4282	np->orig_mac[1] = readl(base + NvRegMacAddrB);	5258	np->orig_mac[1] = readl(base + NvRegMacAddrB);
4283		5259
		5260	/* check the workaround bit for correct mac address order */
		5261	txreg = readl(base + NvRegTransmitPoll);
		5262	if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
		5263	/* mac address is already in correct order */
		5264	dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
		5265	dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
		5266	dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
		5267	dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
		5268	dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
		5269	dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
		5270	} else {
4284	dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;	5271	dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4285	dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;	5272	dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4286	dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;	5273	dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4287	dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;	5274	dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4288	dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;	5275	dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4289	dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;	5276	dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
		5277	/* set permanent address to be correct aswell */
		5278	np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
		5279	(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
		5280	np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
		5281	writel(txreg\|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
		5282	}
4290	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);	5283	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4291		5284
4292	if (!is_valid_ether_addr(dev->perm_addr)) {	5285	if (!is_valid_ether_addr(dev->perm_addr)) {
Lines 4308-4317 Link Here
4308	dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),	5301	dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4309	dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],	5302	dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4310	dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);	5303	dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
		5304	/* set mac address */
		5305	nv_copy_mac_to_hw(dev);
4311		5306
4312	/* disable WOL */	5307	/* disable WOL */
4313	writel(0, base + NvRegWakeUpFlags);	5308	writel(0, base + NvRegWakeUpFlags);
4314	np->wolenabled = 0;	5309	np->wolenabled = wol;
4315		5310
4316	if (id->driver_data & DEV_HAS_POWER_CNTRL) {	5311	if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4317	u8 revision_id;	5312	u8 revision_id;
Lines 4353-4358 Link Here
4353	np->need_linktimer = 0;	5348	np->need_linktimer = 0;
4354	}	5349	}
4355		5350
		5351	/* clear phy state and temporarily halt phy interrupts */
		5352	writel(0, base + NvRegMIIMask);
		5353	phystate = readl(base + NvRegAdapterControl);
		5354	if (phystate & NVREG_ADAPTCTL_RUNNING) {
		5355	phystate_orig = 1;
		5356	phystate &= ~NVREG_ADAPTCTL_RUNNING;
		5357	writel(phystate, base + NvRegAdapterControl);
		5358	}
		5359	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
		5360
		5361	if (id->driver_data & DEV_HAS_MGMT_UNIT) {
		5362	writel(NV_UNKNOWN_VAL, base + NvRegPatternCRC);
		5363	pci_push(base);
		5364	nv_msleep(500);
		5365	/* management unit running on the mac? */
		5366	np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
		5367	if (np->mac_in_use) {
		5368	u32 mgmt_sync;
		5369	dprintk(KERN_DEBUG "%s: probe: mac in use\n",dev->name);
		5370	/* management unit setup the phy already? */
		5371	mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
		5372	if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
		5373	dprintk(KERN_DEBUG"%s : probe: sync not ready\n",dev->name);
		5374	if (!nv_mgmt_acquire_sema(dev)) {
		5375	dprintk(KERN_DEBUG"%s: probe: could not acquire sema\n",dev->name);
		5376	for (i = 0; i < 5000; i++) {
		5377	nv_msleep(1);
		5378	mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
		5379	if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
		5380	continue;
		5381	if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
		5382	dprintk(KERN_DEBUG"%s: probe: phy inited by SMU 1\n",dev->name);
		5383	phyinitialized = 1;
		5384	}
		5385	break;
		5386	dprintk(KERN_DEBUG"%s: probe: breaking out of loop\n",dev->name);
		5387	}
		5388	} else {
		5389	/* we need to init the phy */
		5390	dprintk(KERN_DEBUG"%s: probe: we need to init phy 1\n",dev->name);
		5391	}
		5392	} else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
		5393	dprintk(KERN_DEBUG"%s: probe: phy inited by SMU 2\n",dev->name);
		5394	/* phy is inited by SMU */
		5395	phyinitialized = 1;
		5396	} else {
		5397	/* we need to init the phy */
		5398	dprintk(KERN_DEBUG"%s: probe: we need to init phy 2\n",dev->name);
		5399	}
		5400	} else
		5401	dprintk(KERN_DEBUG"%s: probe: mac not in use\n",dev->name);
		5402	}
		5403
4356	/* find a suitable phy */	5404	/* find a suitable phy */
4357	for (i = 1; i <= 32; i++) {	5405	for (i = 1; i <= 32; i++) {
4358	int id1, id2;	5406	int id1, id2;
Lines 4369-4374 Link Here
4369	if (id2 < 0 \|\| id2 == 0xffff)	5417	if (id2 < 0 \|\| id2 == 0xffff)
4370	continue;	5418	continue;
4371		5419
		5420	np->phy_model = id2 & PHYID2_MODEL_MASK;
4372	id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;	5421	id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4373	id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;	5422	id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4374	dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",	5423	dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
Lines 4382-4395 Link Here
4382	pci_name(pci_dev));	5431	pci_name(pci_dev));
4383	goto out_error;	5432	goto out_error;
4384	}	5433	}
4385		5434
		5435	if (!phyinitialized) {
4386	/* reset it */	5436	/* reset it */
4387	phy_init(dev);	5437	phy_init(dev);
		5438	} else {
		5439	/* see if gigabit phy */
		5440	u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
		5441	if (mii_status & PHY_GIGABIT) {
		5442	np->gigabit = PHY_GIGABIT;
		5443	}
		5444	}
		5445	if (id->driver_data & DEV_HAS_MGMT_UNIT) {
		5446	nv_mgmt_driver_loaded(dev, 1);
		5447	}
4388		5448
4389	/* set default link speed settings */	5449	/* set default link speed settings */
4390	np->linkspeed = NVREG_LINKSPEED_FORCE\|NVREG_LINKSPEED_10;	5450	np->linkspeed = NVREG_LINKSPEED_FORCE\|NVREG_LINKSPEED_10;
4391	np->duplex = 0;	5451	np->duplex = 0;
4392	np->autoneg = 1;	5452	np->autoneg = autoneg;
4393		5453
4394	err = register_netdev(dev);	5454	err = register_netdev(dev);
4395	if (err) {	5455	if (err) {
Lines 4403-4408 Link Here
4403	return 0;	5463	return 0;
4404		5464
4405	out_error:	5465	out_error:
		5466	if (phystate_orig)
		5467	writel(phystate\|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
		5468	if (np->mac_in_use)
		5469	nv_mgmt_driver_loaded(dev, 0);
4406	pci_set_drvdata(pci_dev, NULL);	5470	pci_set_drvdata(pci_dev, NULL);
4407	out_freering:	5471	out_freering:
4408	free_rings(dev);	5472	free_rings(dev);
Lines 4421-4428 Link Here
4421	static void __devexit nv_remove(struct pci_dev *pci_dev)	5485	static void __devexit nv_remove(struct pci_dev *pci_dev)
4422	{	5486	{
4423	struct net_device *dev = pci_get_drvdata(pci_dev);	5487	struct net_device *dev = pci_get_drvdata(pci_dev);
		5488	struct fe_priv *np = get_nvpriv(dev);
		5489	u8 __iomem *base = get_hwbase(dev);
4424		5490
4425	unregister_netdev(dev);	5491	unregister_netdev(dev);
		5492	/* special op: write back the misordered MAC address - otherwise
		5493	* the next nv_probe would see a wrong address.
		5494	*/
		5495	writel(np->orig_mac[0], base + NvRegMacAddrA);
		5496	writel(np->orig_mac[1], base + NvRegMacAddrB);
		5497	if (np->mac_in_use)
		5498	nv_mgmt_driver_loaded(dev, 0);
4426		5499
4427	/* free all structures */	5500	/* free all structures */
4428	free_rings(dev);	5501	free_rings(dev);
Lines 4488-4530 Link Here
4488	},	5561	},
4489	{ /* MCP55 Ethernet Controller */	5562	{ /* MCP55 Ethernet Controller */
4490	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),	5563	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4491	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_VLAN\|DEV_HAS_MSI\|DEV_HAS_MSI_X\|DEV_HAS_POWER_CNTRL\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5564	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_VLAN\|DEV_HAS_MSI\|DEV_HAS_MSI_X\|DEV_HAS_POWER_CNTRL\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4492	},	5565	},
4493	{ /* MCP55 Ethernet Controller */	5566	{ /* MCP55 Ethernet Controller */
4494	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),	5567	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4495	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_VLAN\|DEV_HAS_MSI\|DEV_HAS_MSI_X\|DEV_HAS_POWER_CNTRL\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5568	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_VLAN\|DEV_HAS_MSI\|DEV_HAS_MSI_X\|DEV_HAS_POWER_CNTRL\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4496	},	5569	},
4497	{ /* MCP61 Ethernet Controller */	5570	{ /* MCP61 Ethernet Controller */
4498	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),	5571	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4499	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5572	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4500	},	5573	},
4501	{ /* MCP61 Ethernet Controller */	5574	{ /* MCP61 Ethernet Controller */
4502	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),	5575	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4503	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5576	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4504	},	5577	},
4505	{ /* MCP61 Ethernet Controller */	5578	{ /* MCP61 Ethernet Controller */
4506	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),	5579	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4507	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5580	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4508	},	5581	},
4509	{ /* MCP61 Ethernet Controller */	5582	{ /* MCP61 Ethernet Controller */
4510	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),	5583	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4511	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5584	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4512	},	5585	},
4513	{ /* MCP65 Ethernet Controller */	5586	{ /* MCP65 Ethernet Controller */
4514	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),	5587	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4515	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5588	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4516	},	5589	},
4517	{ /* MCP65 Ethernet Controller */	5590	{ /* MCP65 Ethernet Controller */
4518	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),	5591	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4519	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5592	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4520	},	5593	},
4521	{ /* MCP65 Ethernet Controller */	5594	{ /* MCP65 Ethernet Controller */
4522	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),	5595	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4523	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5596	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4524	},	5597	},
4525	{ /* MCP65 Ethernet Controller */	5598	{ /* MCP65 Ethernet Controller */
4526	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),	5599	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4527	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED,	5600	.driver_data = DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER\|DEV_HAS_LARGEDESC\|DEV_HAS_CHECKSUM\|DEV_HAS_HIGH_DMA\|DEV_HAS_POWER_CNTRL\|DEV_HAS_MSI\|DEV_HAS_PAUSEFRAME_TX\|DEV_HAS_STATISTICS\|DEV_HAS_TEST_EXTENDED\|DEV_HAS_MGMT_UNIT,
4528	},	5601	},
4529	{0,},	5602	{0,},
4530	};	5603	};
Lines 4540-4545 Link Here
4540	static int __init init_nic(void)	5613	static int __init init_nic(void)
4541	{	5614	{
4542	printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);	5615	printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
		5616	dprintk(KERN_DEBUG "DEBUG VERSION\n");
4543	return pci_module_init(&driver);	5617	return pci_module_init(&driver);
4544	}	5618	}
4545		5619
Lines 4558-4566 Link Here
4558	MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");	5632	MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4559	module_param(msix, int, 0);	5633	module_param(msix, int, 0);
4560	MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");	5634	MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
		5635
		5636	module_param(speed_duplex, int, 0);
		5637	MODULE_PARM_DESC(speed_duplex, "PHY speed and duplex settings. Auto = 0, 10mbps half = 1, 10mbps full = 2, 100mbps half = 3, 100mbps full = 4, 1000mbps full = 5.");
		5638	module_param(autoneg, int, 0);
		5639	MODULE_PARM_DESC(autoneg, "PHY autonegotiate is enabled by setting to 1 and disabled by setting to 0.");
		5640	module_param(scatter_gather, int, 0);
		5641	MODULE_PARM_DESC(scatter_gather, "Scatter gather is enabled by setting to 1 and disabled by setting to 0.");
		5642	module_param(tso_offload, int, 0);
		5643	MODULE_PARM_DESC(tso_offload, "TCP Segmentation offload is enabled by setting to 1 and disabled by setting to 0.");
		5644	module_param(mtu, int, 0);
		5645	MODULE_PARM_DESC(mtu, "MTU value. Maximum value of 1500 or 9100 depending on hardware.");
		5646	module_param(tx_checksum_offload, int, 0);
		5647	MODULE_PARM_DESC(tx_checksum_offload, "Tx checksum offload is enabled by setting to 1 and disabled by setting to 0.");
		5648	module_param(rx_checksum_offload, int, 0);
		5649	MODULE_PARM_DESC(rx_checksum_offload, "Rx checksum offload is enabled by setting to 1 and disabled by setting to 0.");
		5650	module_param(tx_ring_size, int, 0);
		5651	MODULE_PARM_DESC(tx_ring_size, "Tx ring size. Maximum value of 1024 or 16384 depending on hardware.");
		5652	module_param(rx_ring_size, int, 0);
		5653	MODULE_PARM_DESC(rx_ring_size, "Rx ring size. Maximum value of 1024 or 16384 depending on hardware.");
		5654	module_param(tx_flow_control, int, 0);
		5655	MODULE_PARM_DESC(tx_flow_control, "Tx flow control is enabled by setting to 1 and disabled by setting to 0.");
		5656	module_param(rx_flow_control, int, 0);
		5657	MODULE_PARM_DESC(rx_flow_control, "Rx flow control is enabled by setting to 1 and disabled by setting to 0.");
4561	module_param(dma_64bit, int, 0);	5658	module_param(dma_64bit, int, 0);
4562	MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");	5659	MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4563		5660	module_param(wol, int, 0);
		5661	MODULE_PARM_DESC(wol, "Wake-On-Lan is enabled by setting to 1 and disabled by setting to 0.");
		5662	module_param(tagging_8021pq, int, 0);
		5663	MODULE_PARM_DESC(tagging_8021pq, "802.1pq tagging is enabled by setting to 1 and disabled by setting to 0.");
4564	MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");	5664	MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4565	MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");	5665	MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4566	MODULE_LICENSE("GPL");	5666	MODULE_LICENSE("GPL");

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