--- crystalhd~/bc_dts_defs.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/bc_dts_defs.h 2011-03-14 23:02:54.000000000 +0300 @@ -26,12 +26,10 @@ #ifndef _BC_DTS_DEFS_H_ #define _BC_DTS_DEFS_H_ -#include - /* BIT Mask */ #define BC_BIT(_x) (1 << (_x)) -enum BC_STATUS { +typedef enum _BC_STATUS { BC_STS_SUCCESS = 0, BC_STS_INV_ARG = 1, BC_STS_BUSY = 2, @@ -58,16 +56,22 @@ enum BC_STATUS { BC_STS_CERT_VERIFY_ERROR = 23, BC_STS_DEC_EXIST_OPEN = 24, BC_STS_PENDING = 25, - BC_STS_CLK_NOCHG = 26, + BC_STS_PWR_MGMT = 26, /* Must be the last one.*/ BC_STS_ERROR = -1 -}; +} BC_STATUS; + +typedef enum _BC_HW_STATE { + BC_HW_RUNNING = 0, + BC_HW_SUSPEND = 1, + BC_HW_RESUME = 2 +} BC_HW_STATE; /*------------------------------------------------------* * Registry Key Definitions * *------------------------------------------------------*/ -#define BC_REG_KEY_MAIN_PATH "Software\\Broadcom\\MediaPC\\70010" +#define BC_REG_KEY_MAIN_PATH "Software\\Broadcom\\MediaPC\\CrystalHD" #define BC_REG_KEY_FWPATH "FirmwareFilePath" #define BC_REG_KEY_SEC_OPT "DbgOptions" @@ -81,17 +85,17 @@ enum BC_STATUS { * */ -enum BC_SW_OPTIONS { +typedef enum _BC_SW_OPTIONS { BC_OPT_DOSER_OUT_ENCRYPT = BC_BIT(3), BC_OPT_LINK_OUT_ENCRYPT = BC_BIT(29), -}; +} BC_SW_OPTIONS; -struct BC_REG_CONFIG { +typedef struct _BC_REG_CONFIG{ uint32_t DbgOptions; -}; +} BC_REG_CONFIG; -#if defined(__KERNEL__) || defined(__LINUX_USER__) -#else +/*#if defined(__KERNEL__) || defined(__LINUX_USER__) */ +#if defined(_WIN32) || defined(_WIN64) /* Align data structures */ #define ALIGN(x) __declspec(align(x)) #endif @@ -108,7 +112,7 @@ struct BC_REG_CONFIG { */ /* To allow multiple apps to open the device. */ -enum DtsDeviceOpenMode { +enum _DtsDeviceOpenMode { DTS_PLAYBACK_MODE = 0, DTS_DIAG_MODE, DTS_MONITOR_MODE, @@ -116,7 +120,7 @@ enum DtsDeviceOpenMode { }; /* To enable the filter to selectively enable/disable fixes or erratas */ -enum DtsDeviceFixMode { +enum _DtsDeviceFixMode { DTS_LOAD_NEW_FW = BC_BIT(8), DTS_LOAD_FILE_PLAY_FW = BC_BIT(9), DTS_DISK_FMT_BD = BC_BIT(10), @@ -125,7 +129,11 @@ enum DtsDeviceFixMode { DTS_ADAPTIVE_OUTPUT_PER = BC_BIT(17), DTS_INTELLIMAP = BC_BIT(18), /* b[19]-b[21] : select clock frequency */ - DTS_PLAYBACK_DROP_RPT_MODE = BC_BIT(22) + DTS_PLAYBACK_DROP_RPT_MODE = BC_BIT(22), + DTS_DIAG_TEST_MODE = BC_BIT(23), + DTS_SINGLE_THREADED_MODE = BC_BIT(24), + DTS_FILTER_MODE = BC_BIT(25), + DTS_MFT_MODE = BC_BIT(26) }; #define DTS_DFLT_RESOLUTION(x) (x<<11) @@ -133,7 +141,7 @@ enum DtsDeviceFixMode { #define DTS_DFLT_CLOCK(x) (x<<19) /* F/W File Version corresponding to S/W Releases */ -enum FW_FILE_VER { +enum _FW_FILE_VER { /* S/W release: 02.04.02 F/W release 2.12.2.0 */ BC_FW_VER_020402 = ((12<<16) | (2<<8) | (0)) }; @@ -141,7 +149,7 @@ enum FW_FILE_VER { /*------------------------------------------------------* * Stream Types for DtsOpenDecoder() * *------------------------------------------------------*/ -enum DtsOpenDecStreamTypes { +enum _DtsOpenDecStreamTypes { BC_STREAM_TYPE_ES = 0, BC_STREAM_TYPE_PES = 1, BC_STREAM_TYPE_TS = 2, @@ -151,10 +159,11 @@ enum DtsOpenDecStreamTypes { /*------------------------------------------------------* * Video Algorithms for DtsSetVideoParams() * *------------------------------------------------------*/ -enum DtsSetVideoParamsAlgo { +enum _DtsSetVideoParamsAlgo { BC_VID_ALGO_H264 = 0, BC_VID_ALGO_MPEG2 = 1, BC_VID_ALGO_VC1 = 4, + BC_VID_ALGO_DIVX = 6, BC_VID_ALGO_VC1MP = 7, }; @@ -163,7 +172,7 @@ enum DtsSetVideoParamsAlgo { *------------------------------------------------------*/ #define BC_MPEG_VALID_PANSCAN (1) -struct BC_PIB_EXT_MPEG { +typedef struct _BC_PIB_EXT_MPEG { uint32_t valid; /* Always valid, defaults to picture size if no * sequence display extension in the stream. */ @@ -175,7 +184,8 @@ struct BC_PIB_EXT_MPEG { uint32_t offset_count; int32_t horizontal_offset[3]; int32_t vertical_offset[3]; -}; + +} BC_PIB_EXT_MPEG; /*------------------------------------------------------* * H.264 Extension to the PPB * @@ -185,7 +195,7 @@ struct BC_PIB_EXT_MPEG { #define H264_VALID_SPS_CROP (2) #define H264_VALID_VUI (4) -struct BC_PIB_EXT_H264 { +typedef struct _BC_PIB_EXT_H264 { /* 'valid' specifies which fields (or sets of * fields) below are valid. If the corresponding * bit in 'valid' is NOT set then that field(s) @@ -208,14 +218,15 @@ struct BC_PIB_EXT_H264 { /* H264_VALID_VUI */ uint32_t chroma_top; uint32_t chroma_bottom; -}; + +} BC_PIB_EXT_H264; /*------------------------------------------------------* * VC1 Extension to the PPB * *------------------------------------------------------*/ #define VC1_VALID_PANSCAN (1) -struct BC_PIB_EXT_VC1 { +typedef struct _BC_PIB_EXT_VC1 { uint32_t valid; /* Always valid, defaults to picture size if no @@ -229,12 +240,14 @@ struct BC_PIB_EXT_VC1 { int32_t ps_vert_offset[4]; int32_t ps_width[4]; int32_t ps_height[4]; -}; + +} BC_PIB_EXT_VC1; + /*------------------------------------------------------* * Picture Information Block * *------------------------------------------------------*/ -#if defined(__LINUX_USER__) +#if !defined(__KERNEL__) /* Values for 'pulldown' field. '0' means no pulldown information * was present for this picture. */ enum { @@ -262,6 +275,8 @@ enum { vdecFrameRate50, vdecFrameRate59_94, vdecFrameRate60, + vdecFrameRate14_985, + vdecFrameRate7_496, }; /* Values for the 'aspect_ratio' field. */ @@ -298,79 +313,43 @@ enum { vdecColourPrimariesSMPTE240M, vdecColourPrimariesGenericFilm, }; -/** - * @vdecRESOLUTION_CUSTOM: custom - * @vdecRESOLUTION_480i: 480i - * @vdecRESOLUTION_1080i: 1080i (1920x1080, 60i) - * @vdecRESOLUTION_NTSC: NTSC (720x483, 60i) - * @vdecRESOLUTION_480p: 480p (720x480, 60p) - * @vdecRESOLUTION_720p: 720p (1280x720, 60p) - * @vdecRESOLUTION_PAL1: PAL_1 (720x576, 50i) - * @vdecRESOLUTION_1080i25: 1080i25 (1920x1080, 50i) - * @vdecRESOLUTION_720p50: 720p50 (1280x720, 50p) - * @vdecRESOLUTION_576p: 576p (720x576, 50p) - * @vdecRESOLUTION_1080i29_97: 1080i (1920x1080, 59.94i) - * @vdecRESOLUTION_720p59_94: 720p (1280x720, 59.94p) - * @vdecRESOLUTION_SD_DVD: SD DVD (720x483, 60i) - * @vdecRESOLUTION_480p656: 480p (720x480, 60p), - * output bus width 8 bit, clock 74.25MHz - * @vdecRESOLUTION_1080p23_976: 1080p23_976 (1920x1080, 23.976p) - * @vdecRESOLUTION_720p23_976: 720p23_976 (1280x720p, 23.976p) - * @vdecRESOLUTION_240p29_97: 240p (1440x240, 29.97p ) - * @vdecRESOLUTION_240p30: 240p (1440x240, 30p) - * @vdecRESOLUTION_288p25: 288p (1440x288p, 25p) - * @vdecRESOLUTION_1080p29_97: 1080p29_97 (1920x1080, 29.97p) - * @vdecRESOLUTION_1080p30: 1080p30 (1920x1080, 30p) - * @vdecRESOLUTION_1080p24: 1080p24 (1920x1080, 24p) - * @vdecRESOLUTION_1080p25: 1080p25 (1920x1080, 25p) - * @vdecRESOLUTION_720p24: 720p24 (1280x720, 25p) - * @vdecRESOLUTION_720p29_97: 720p29.97 (1280x720, 29.97p) - * @vdecRESOLUTION_480p23_976: 480p23.976 (720*480, 23.976) - * @vdecRESOLUTION_480p29_97: 480p29.976 (720*480, 29.97p) - * @vdecRESOLUTION_576p25: 576p25 (720*576, 25p) - * @vdecRESOLUTION_480p0: 480p (720x480, 0p) - * @vdecRESOLUTION_480i0: 480i (720x480, 0i) - * @vdecRESOLUTION_576p0: 576p (720x576, 0p) - * @vdecRESOLUTION_720p0: 720p (1280x720, 0p) - * @vdecRESOLUTION_1080p0: 1080p (1920x1080, 0p) - * @vdecRESOLUTION_1080i0: 1080i (1920x1080, 0i) - */ + enum { - vdecRESOLUTION_CUSTOM = 0x00000000, - vdecRESOLUTION_480i = 0x00000001, - vdecRESOLUTION_1080i = 0x00000002, - vdecRESOLUTION_NTSC = 0x00000003, - vdecRESOLUTION_480p = 0x00000004, - vdecRESOLUTION_720p = 0x00000005, - vdecRESOLUTION_PAL1 = 0x00000006, - vdecRESOLUTION_1080i25 = 0x00000007, - vdecRESOLUTION_720p50 = 0x00000008, - vdecRESOLUTION_576p = 0x00000009, - vdecRESOLUTION_1080i29_97 = 0x0000000A, - vdecRESOLUTION_720p59_94 = 0x0000000B, - vdecRESOLUTION_SD_DVD = 0x0000000C, - vdecRESOLUTION_480p656 = 0x0000000D, - vdecRESOLUTION_1080p23_976 = 0x0000000E, - vdecRESOLUTION_720p23_976 = 0x0000000F, - vdecRESOLUTION_240p29_97 = 0x00000010, - vdecRESOLUTION_240p30 = 0x00000011, - vdecRESOLUTION_288p25 = 0x00000012, - vdecRESOLUTION_1080p29_97 = 0x00000013, - vdecRESOLUTION_1080p30 = 0x00000014, - vdecRESOLUTION_1080p24 = 0x00000015, - vdecRESOLUTION_1080p25 = 0x00000016, - vdecRESOLUTION_720p24 = 0x00000017, - vdecRESOLUTION_720p29_97 = 0x00000018, - vdecRESOLUTION_480p23_976 = 0x00000019, - vdecRESOLUTION_480p29_97 = 0x0000001A, - vdecRESOLUTION_576p25 = 0x0000001B, + vdecRESOLUTION_CUSTOM = 0x00000000, /* custom */ + vdecRESOLUTION_480i = 0x00000001, /* 480i */ + vdecRESOLUTION_1080i = 0x00000002, /* 1080i (1920x1080, 60i) */ + vdecRESOLUTION_NTSC = 0x00000003, /* NTSC (720x483, 60i) */ + vdecRESOLUTION_480p = 0x00000004, /* 480p (720x480, 60p) */ + vdecRESOLUTION_720p = 0x00000005, /* 720p (1280x720, 60p) */ + vdecRESOLUTION_PAL1 = 0x00000006, /* PAL_1 (720x576, 50i) */ + vdecRESOLUTION_1080i25 = 0x00000007, /* 1080i25 (1920x1080, 50i) */ + vdecRESOLUTION_720p50 = 0x00000008, /* 720p50 (1280x720, 50p) */ + vdecRESOLUTION_576p = 0x00000009, /* 576p (720x576, 50p) */ + vdecRESOLUTION_1080i29_97 = 0x0000000A, /* 1080i (1920x1080, 59.94i) */ + vdecRESOLUTION_720p59_94 = 0x0000000B, /* 720p (1280x720, 59.94p) */ + vdecRESOLUTION_SD_DVD = 0x0000000C, /* SD DVD (720x483, 60i) */ + vdecRESOLUTION_480p656 = 0x0000000D, /* 480p (720x480, 60p), output bus width 8 bit, clock 74.25MHz */ + vdecRESOLUTION_1080p23_976 = 0x0000000E, /* 1080p23_976 (1920x1080, 23.976p) */ + vdecRESOLUTION_720p23_976 = 0x0000000F, /* 720p23_976 (1280x720p, 23.976p) */ + vdecRESOLUTION_240p29_97 = 0x00000010, /* 240p (1440x240, 29.97p ) */ + vdecRESOLUTION_240p30 = 0x00000011, /* 240p (1440x240, 30p) */ + vdecRESOLUTION_288p25 = 0x00000012, /* 288p (1440x288p, 25p) */ + vdecRESOLUTION_1080p29_97 = 0x00000013, /* 1080p29_97 (1920x1080, 29.97p) */ + vdecRESOLUTION_1080p30 = 0x00000014, /* 1080p30 (1920x1080, 30p) */ + vdecRESOLUTION_1080p24 = 0x00000015, /* 1080p24 (1920x1080, 24p) */ + vdecRESOLUTION_1080p25 = 0x00000016, /* 1080p25 (1920x1080, 25p) */ + vdecRESOLUTION_720p24 = 0x00000017, /* 720p24 (1280x720, 25p) */ + vdecRESOLUTION_720p29_97 = 0x00000018, /* 720p29.97 (1280x720, 29.97p) */ + vdecRESOLUTION_480p23_976 = 0x00000019, /* 480p23.976 (720*480, 23.976) */ + vdecRESOLUTION_480p29_97 = 0x0000001A, /* 480p29.976 (720*480, 29.97p) */ + vdecRESOLUTION_576p25 = 0x0000001B, /* 576p25 (720*576, 25p) */ /* For Zero Frame Rate */ - vdecRESOLUTION_480p0 = 0x0000001C, - vdecRESOLUTION_480i0 = 0x0000001D, - vdecRESOLUTION_576p0 = 0x0000001E, - vdecRESOLUTION_720p0 = 0x0000001F, - vdecRESOLUTION_1080p0 = 0x00000020, - vdecRESOLUTION_1080i0 = 0x00000021, + vdecRESOLUTION_480p0 = 0x0000001C, /* 480p (720x480, 0p) */ + vdecRESOLUTION_480i0 = 0x0000001D, /* 480i (720x480, 0i) */ + vdecRESOLUTION_576p0 = 0x0000001E, /* 576p (720x576, 0p) */ + vdecRESOLUTION_720p0 = 0x0000001F, /* 720p (1280x720, 0p) */ + vdecRESOLUTION_1080p0 = 0x00000020, /* 1080p (1920x1080, 0p) */ + vdecRESOLUTION_1080i0 = 0x00000021, /* 1080i (1920x1080, 0i) */ }; /* Bit definitions for 'flags' field */ @@ -390,30 +369,15 @@ enum { #define VDEC_FLAG_PICTURE_META_DATA_PRESENT (0x40000) -#endif /* __LINUX_USER__ */ +#endif /* __KERNEL__ */ -enum _BC_OUTPUT_FORMAT { - MODE420 = 0x0, - MODE422_YUY2 = 0x1, - MODE422_UYVY = 0x2, -}; -/** - * struct BC_PIC_INFO_BLOCK - * @timeStam;: Timestamp - * @picture_number: Ordinal display number - * @width: pixels - * @height: pixels - * @chroma_format: 0x420, 0x422 or 0x444 - * @n_drop;: number of non-reference frames - * remaining to be dropped - */ -struct BC_PIC_INFO_BLOCK { +typedef struct _BC_PIC_INFO_BLOCK { /* Common fields. */ - uint64_t timeStamp; - uint32_t picture_number; - uint32_t width; - uint32_t height; - uint32_t chroma_format; + uint64_t timeStamp; /* Timestamp */ + uint32_t picture_number; /* Ordinal display number */ + uint32_t width; /* pixels */ + uint32_t height; /* pixels */ + uint32_t chroma_format; /* 0x420, 0x422 or 0x444 */ uint32_t pulldown; uint32_t flags; uint32_t frame_rate; @@ -423,86 +387,72 @@ struct BC_PIC_INFO_BLOCK { uint32_t sess_num; uint32_t ycom; uint32_t custom_aspect_ratio_width_height; - uint32_t n_drop; /* number of non-reference frames - remaining to be dropped */ + uint32_t n_drop; /* number of non-reference frames remaining to be dropped */ /* Protocol-specific extensions. */ union { - struct BC_PIB_EXT_H264 h264; - struct BC_PIB_EXT_MPEG mpeg; - struct BC_PIB_EXT_VC1 vc1; + BC_PIB_EXT_H264 h264; + BC_PIB_EXT_MPEG mpeg; + BC_PIB_EXT_VC1 vc1; } other; -}; +} BC_PIC_INFO_BLOCK, *PBC_PIC_INFO_BLOCK; /*------------------------------------------------------* * ProcOut Info * *------------------------------------------------------*/ - -/** - * enum POUT_OPTIONAL_IN_FLAGS - Optional flags for ProcOut Interface. - * @BC_POUT_FLAGS_YV12: Copy Data in YV12 format - * @BC_POUT_FLAGS_STRIDE: Stride size is valid. - * @BC_POUT_FLAGS_SIZE: Take size information from Application - * @BC_POUT_FLAGS_INTERLACED: copy only half the bytes - * @BC_POUT_FLAGS_INTERLEAVED: interleaved frame - * @: * @BC_POUT_FLAGS_FMT_CHANGE: Data is not VALID when this flag is set - * @BC_POUT_FLAGS_PIB_VALID: PIB Information valid - * @BC_POUT_FLAGS_ENCRYPTED: Data is encrypted. - * @BC_POUT_FLAGS_FLD_BOT: Bottom Field data - */ -enum POUT_OPTIONAL_IN_FLAGS_ { +/* Optional flags for ProcOut Interface.*/ +enum _POUT_OPTIONAL_IN_FLAGS_{ /* Flags from App to Device */ - BC_POUT_FLAGS_YV12 = 0x01, - BC_POUT_FLAGS_STRIDE = 0x02, - BC_POUT_FLAGS_SIZE = 0x04, - BC_POUT_FLAGS_INTERLACED = 0x08, - BC_POUT_FLAGS_INTERLEAVED = 0x10, + BC_POUT_FLAGS_YV12 = 0x01, /* Copy Data in YV12 format */ + BC_POUT_FLAGS_STRIDE = 0x02, /* Stride size is valid. */ + BC_POUT_FLAGS_SIZE = 0x04, /* Take size information from Application */ + BC_POUT_FLAGS_INTERLACED = 0x08, /* copy only half the bytes */ + BC_POUT_FLAGS_INTERLEAVED = 0x10, /* interleaved frame */ + BC_POUT_FLAGS_STRIDE_UV = 0x20, /* Stride size is valid (for UV buffers). */ + BC_POUT_FLAGS_MODE = 0x40, /* Take output mode from Application, overrides YV12 flag if on */ /* Flags from Device to APP */ - BC_POUT_FLAGS_FMT_CHANGE = 0x10000, - BC_POUT_FLAGS_PIB_VALID = 0x20000, - BC_POUT_FLAGS_ENCRYPTED = 0x40000, - BC_POUT_FLAGS_FLD_BOT = 0x80000, + BC_POUT_FLAGS_FMT_CHANGE = 0x10000, /* Data is not VALID when this flag is set */ + BC_POUT_FLAGS_PIB_VALID = 0x20000, /* PIB Information valid */ + BC_POUT_FLAGS_ENCRYPTED = 0x40000, /* Data is encrypted. */ + BC_POUT_FLAGS_FLD_BOT = 0x80000, /* Bottom Field data */ +}; + +/*Decoder Capability */ +enum DECODER_CAP_FLAGS +{ + BC_DEC_FLAGS_H264 = 0x01, + BC_DEC_FLAGS_MPEG2 = 0x02, + BC_DEC_FLAGS_VC1 = 0x04, + BC_DEC_FLAGS_M4P2 = 0x08, /*MPEG-4 Part 2: Divx, Xvid etc. */ }; -typedef enum BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, - uint32_t height, uint32_t stride, void *pOut); +#if defined(__KERNEL__) || defined(__LINUX_USER__) || defined(__LINUX__) +typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, void *pOut); +#else +typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, struct _BC_DTS_PROC_OUT *pOut); +#endif /* Line 21 Closed Caption */ /* User Data */ #define MAX_UD_SIZE 1792 /* 1920 - 128 */ -/** - * struct BC_DTS_PROC_OUT - * @Ybuff: Caller Supplied buffer for Y data - * @YbuffSz: Caller Supplied Y buffer size - * @YBuffDoneSz: Transferred Y datasize - * @*UVbuff: Caller Supplied buffer for UV data - * @UVbuffSz: Caller Supplied UV buffer size - * @UVBuffDoneSz: Transferred UV data size - * @StrideSz: Caller supplied Stride Size - * @PoutFlags: Call IN Flags - * @discCnt: Picture discontinuity count - * @PicInfo: Picture Information Block Data - * @b422Mode: Picture output Mode - * @bPibEnc: PIB encrypted - */ -struct BC_DTS_PROC_OUT { - uint8_t *Ybuff; - uint32_t YbuffSz; - uint32_t YBuffDoneSz; +typedef struct _BC_DTS_PROC_OUT { + uint8_t *Ybuff; /* Caller Supplied buffer for Y data */ + uint32_t YbuffSz; /* Caller Supplied Y buffer size */ + uint32_t YBuffDoneSz; /* Transferred Y datasize */ - uint8_t *UVbuff; - uint32_t UVbuffSz; - uint32_t UVBuffDoneSz; + uint8_t *UVbuff; /* Caller Supplied buffer for UV data */ + uint32_t UVbuffSz; /* Caller Supplied UV buffer size */ + uint32_t UVBuffDoneSz; /* Transferred UV data size */ - uint32_t StrideSz; - uint32_t PoutFlags; + uint32_t StrideSz; /* Caller supplied Stride Size */ + uint32_t PoutFlags; /* Call IN Flags */ - uint32_t discCnt; + uint32_t discCnt; /* Picture discontinuity count */ - struct BC_PIC_INFO_BLOCK PicInfo; + BC_PIC_INFO_BLOCK PicInfo; /* Picture Information Block Data */ /* Line 21 Closed Caption */ /* User Data */ @@ -512,48 +462,47 @@ struct BC_DTS_PROC_OUT { void *hnd; dts_pout_callback AppCallBack; uint8_t DropFrames; - uint8_t b422Mode; - uint8_t bPibEnc; + uint8_t b422Mode; /* Picture output Mode */ + uint8_t bPibEnc; /* PIB encrypted */ uint8_t bRevertScramble; + uint32_t StrideSzUV; /* Caller supplied Stride Size */ -}; -/** - * struct BC_DTS_STATUS - * @ReadyListCount: Number of frames in ready list (reported by driver) - * @PowerStateChange: Number of active state power - * transitions (reported by driver) - * @FramesDropped: Number of frames dropped. (reported by DIL) - * @FramesCaptured: Number of frames captured. (reported by DIL) - * @FramesRepeated: Number of frames repeated. (reported by DIL) - * @InputCount: Times compressed video has been sent to the HW. - * i.e. Successful DtsProcInput() calls (reported by DIL) - * @InputTotalSize: Amount of compressed video that has been sent to the HW. - * (reported by DIL) - * @InputBusyCount: Times compressed video has attempted to be sent to the HW - * but the input FIFO was full. (reported by DIL) - * @PIBMissCount: Amount of times a PIB is invalid. (reported by DIL) - * @cpbEmptySize: supported only for H.264, specifically changed for - * Adobe. Report size of CPB buffer available. (reported by DIL) - * @NextTimeStamp: TimeStamp of the next picture that will be returned - * by a call to ProcOutput. Added for Adobe. Reported - * back from the driver - */ -struct BC_DTS_STATUS { - uint8_t ReadyListCount; - uint8_t FreeListCount; - uint8_t PowerStateChange; +} BC_DTS_PROC_OUT; + +typedef struct _BC_DTS_STATUS { + uint8_t ReadyListCount; /* Number of frames in ready list (reported by driver) */ + uint8_t FreeListCount; /* Number of frame buffers free. (reported by driver) */ + uint8_t PowerStateChange; /* Number of active state power transitions (reported by driver) */ uint8_t reserved_[1]; - uint32_t FramesDropped; - uint32_t FramesCaptured; - uint32_t FramesRepeated; - uint32_t InputCount; - uint64_t InputTotalSize; - uint32_t InputBusyCount; - uint32_t PIBMissCount; - uint32_t cpbEmptySize; - uint64_t NextTimeStamp; - uint8_t reserved__[16]; -}; + + uint32_t FramesDropped; /* Number of frames dropped. (reported by DIL) */ + uint32_t FramesCaptured; /* Number of frames captured. (reported by DIL) */ + uint32_t FramesRepeated; /* Number of frames repeated. (reported by DIL) */ + + uint32_t InputCount; /* Times compressed video has been sent to the HW. + * i.e. Successful DtsProcInput() calls (reported by DIL) */ + uint64_t InputTotalSize; /* Amount of compressed video that has been sent to the HW. + * (reported by DIL) */ + uint32_t InputBusyCount; /* Times compressed video has attempted to be sent to the HW + * but the input FIFO was full. (reported by DIL) */ + + uint32_t PIBMissCount; /* Amount of times a PIB is invalid. (reported by DIL) */ + + uint32_t cpbEmptySize; /* supported only for H.264, specifically changed for + * SingleThreadedAppMode. Report size of CPB buffer available. + * Reported by DIL */ + uint64_t NextTimeStamp; /* TimeStamp of the next picture that will be returned + * by a call to ProcOutput. Added for SingleThreadedAppMode. + * Reported back from the driver */ + uint8_t TxBufData; + + uint8_t reserved__[3]; + + uint32_t picNumFlags; /* Picture number and flags of the next picture to be delivered from the driver */ + + uint8_t reserved___[8]; + +} BC_DTS_STATUS; #define BC_SWAP32(_v) \ ((((_v) & 0xFF000000)>>24)| \ @@ -568,5 +517,123 @@ struct BC_DTS_STATUS { #define WM_AGENT_TRAYICON_DECODER_RUN 10005 #define WM_AGENT_TRAYICON_DECODER_PAUSE 10006 +#define MAX_COLOR_SPACES 3 + +typedef enum _BC_OUTPUT_FORMAT { + MODE420 = 0x0, + MODE422_YUY2 = 0x1, + MODE422_UYVY = 0x2, + OUTPUT_MODE420 = 0x0, + OUTPUT_MODE422_YUY2 = 0x1, + OUTPUT_MODE422_UYVY = 0x2, + OUTPUT_MODE420_NV12 = 0x0, + OUTPUT_MODE_INVALID = 0xFF, +} BC_OUTPUT_FORMAT; + +typedef struct _BC_COLOR_SPACES_ { + BC_OUTPUT_FORMAT OutFmt[MAX_COLOR_SPACES]; + uint16_t Count; +} BC_COLOR_SPACES; + + +typedef enum _BC_CAPS_FLAGS_ { + PES_CONV_SUPPORT = 1, /*Support PES Conversion*/ + MULTIPLE_DECODE_SUPPORT = 2 /*Support multiple stream decode*/ +} BC_CAPS_FLAGS; + +typedef struct _BC_HW_CAPABILITY_ { + BC_CAPS_FLAGS flags; + BC_COLOR_SPACES ColorCaps; + void* Reserved1; /* Expansion Of API */ + + /*Decoder Capability */ + uint32_t DecCaps; /*DECODER_CAP_FLAGS */ +} BC_HW_CAPS, *PBC_HW_CAPS; + +typedef struct _BC_SCALING_PARAMS_ { + uint32_t sWidth; + uint32_t sHeight; + uint32_t DNR; + uint32_t Reserved1; /*Expansion Of API*/ + uint8_t *Reserved2; /*Expansion OF API*/ + uint32_t Reserved3; /*Expansion Of API*/ + uint8_t *Reserved4; /*Expansion Of API*/ + +} BC_SCALING_PARAMS, *PBC_SCALING_PARAMS; + +typedef enum _BC_MEDIA_SUBTYPE_ { + BC_MSUBTYPE_INVALID = 0, + BC_MSUBTYPE_MPEG1VIDEO, + BC_MSUBTYPE_MPEG2VIDEO, + BC_MSUBTYPE_H264, + BC_MSUBTYPE_WVC1, + BC_MSUBTYPE_WMV3, + BC_MSUBTYPE_AVC1, + BC_MSUBTYPE_WMVA, + BC_MSUBTYPE_VC1, + BC_MSUBTYPE_DIVX, + BC_MSUBTYPE_DIVX311, + BC_MSUBTYPE_OTHERS /*Types to facilitate PES conversion*/ +} BC_MEDIA_SUBTYPE; + +typedef struct _BC_INPUT_FORMAT_ { + int FGTEnable; /*Enable processing of FGT SEI*/ + int MetaDataEnable; /*Enable retrieval of picture metadata to be sent to video pipeline.*/ + int Progressive; /*Instruct decoder to always try to send back progressive + frames. If input content is 1080p, the decoder will + ignore pull-down flags and always give 1080p output. + If 1080i content is processed, the decoder will return + 1080i data. When this flag is not set, the decoder will + use pull-down information in the input stream to decide + the decoded data format.*/ + uint32_t OptFlags; /*In this field bits 0:3 are used pass default frame rate, bits 4:5 are for operation mode + (used to indicate Blu-ray mode to the decoder) and bit 6 is for the flag mpcOutPutMaxFRate + which when set tells the FW to output at the max rate for the resolution and ignore the + frame rate determined from the stream. Bit 7 is set to indicate that this is single threaded + mode and the driver will be peeked to get timestamps ahead of time*/ + BC_MEDIA_SUBTYPE mSubtype; /* Video Media Type*/ + uint32_t width; + uint32_t height; + uint32_t startCodeSz; /*Start code size for H264 clips*/ + uint8_t *pMetaData; /*Metadata buffer that is used to pass sequence header*/ + uint32_t metaDataSz; /*Metadata size*/ + uint8_t bEnableScaling; + BC_SCALING_PARAMS ScalingParams; +} BC_INPUT_FORMAT; + +typedef struct _BC_INFO_CRYSTAL_ { + uint8_t device; + union { + struct { + uint32_t dilRelease:8; + uint32_t dilMajor:8; + uint32_t dilMinor:16; + }; + uint32_t version; + } dilVersion; + + union { + struct { + uint32_t drvRelease:4; + uint32_t drvMajor:8; + uint32_t drvMinor:12; + uint32_t drvBuild:8; + }; + uint32_t version; + } drvVersion; + + union { + struct { + uint32_t fwRelease:4; + uint32_t fwMajor:8; + uint32_t fwMinor:12; + uint32_t fwBuild:8; + }; + uint32_t version; + } fwVersion; + + uint32_t Reserved1; /* For future expansion */ + uint32_t Reserved2; /* For future expansion */ +} BC_INFO_CRYSTAL, *PBC_INFO_CRYSTAL; #endif /* _BC_DTS_DEFS_H_ */ --- crystalhd~/bc_dts_glob_lnx.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/bc_dts_glob_lnx.h 2011-03-14 23:02:54.000000000 +0300 @@ -28,7 +28,7 @@ #ifndef _BC_DTS_GLOB_LNX_H_ #define _BC_DTS_GLOB_LNX_H_ -#ifdef __LINUX_USER__ +#if !defined(__KERNEL__) #include #include #include @@ -48,87 +48,112 @@ #endif -#include "crystalhd.h" +#include "bc_dts_defs.h" +#include "bcm_70012_regs.h" /* Link Register defs */ #define CRYSTALHD_API_NAME "crystalhd" #define CRYSTALHD_API_DEV_NAME "/dev/crystalhd" +enum _BC_PCI_DEV_IDS{ + BC_PCI_DEVID_INVALID = 0, + BC_PCI_DEVID_DOZER = 0x1610, + BC_PCI_DEVID_TANK = 0x1620, + BC_PCI_DEVID_LINK = 0x1612, + BC_PCI_DEVID_LOCKE = 0x1613, + BC_PCI_DEVID_DEMOBRD = 0x7411, + BC_PCI_DEVID_MORPHEUS = 0x7412, + BC_PCI_DEVID_FLEA = 0x1615, +}; + /* * These are SW stack tunable parameters shared * between the driver and the application. */ -enum BC_DTS_GLOBALS { - BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ +enum _BC_DTS_GLOBALS { + BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ PCI_CFG_SIZE = 256, /* PCI config size buffer */ BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */ - BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ - BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ + BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ + BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */ - BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/ - BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */ + BC_RX_LIST_CNT = 16, /* Max Rx DMA Rings*/ + BC_PROC_OUTPUT_TIMEOUT = 2000, /* Milliseconds */ BC_INFIFO_THRESHOLD = 0x10000, }; -struct BC_CMD_REG_ACC { +/* definitions for HW Pause */ +/* NAREN FIXME temporarily disable HW PAUSE */ +#define HW_PAUSE_THRESHOLD (BC_RX_LIST_CNT) +#define HW_RESUME_THRESHOLD (BC_RX_LIST_CNT/2) + +typedef union _addr_64_ { + struct { + uint32_t low_part; + uint32_t high_part; + }; + uint64_t full_addr; +} addr_64; + +typedef struct _BC_CMD_REG_ACC { uint32_t Offset; uint32_t Value; -}; +} BC_CMD_REG_ACC; -struct BC_CMD_DEV_MEM { +typedef struct _BC_CMD_DEV_MEM { uint32_t StartOff; uint32_t NumDwords; uint32_t Rsrd; -}; +} BC_CMD_DEV_MEM; /* FW Passthrough command structure */ -enum bc_fw_cmd_flags { +enum _bc_fw_cmd_flags { BC_FW_CMD_FLAGS_NONE = 0, BC_FW_CMD_PIB_QS = 0x01, }; -struct BC_FW_CMD { +typedef struct _BC_FW_CMD { uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ]; uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ]; uint32_t flags; uint32_t add_data; -}; +} BC_FW_CMD, *PBC_FW_CMD; -struct BC_HW_TYPE { +typedef struct _BC_HW_TYPE { uint16_t PciDevId; uint16_t PciVenId; uint8_t HwRev; uint8_t Align[3]; -}; +} BC_HW_TYPE; -struct BC_PCI_CFG { +typedef struct _BC_PCI_CFG { uint32_t Size; uint32_t Offset; uint8_t pci_cfg_space[PCI_CFG_SIZE]; -}; +} BC_PCI_CFG; -struct BC_VERSION_INFO { +typedef struct _BC_VERSION_INFO_ { uint8_t DriverMajor; uint8_t DriverMinor; uint16_t DriverRevision; -}; +} BC_VERSION_INFO; -struct BC_START_RX_CAP { +typedef struct _BC_START_RX_CAP_ { uint32_t Rsrd; uint32_t StartDeliveryThsh; uint32_t PauseThsh; uint32_t ResumeThsh; -}; +} BC_START_RX_CAP; -struct BC_FLUSH_RX_CAP { +typedef struct _BC_FLUSH_RX_CAP_ { uint32_t Rsrd; uint32_t bDiscardOnly; -}; +} BC_FLUSH_RX_CAP; -struct BC_DTS_STATS { +typedef struct _BC_DTS_STATS { uint8_t drvRLL; uint8_t drvFLL; uint8_t eosDetected; - uint8_t pwr_state_change; + uint8_t pwr_state_change; /* 0 is Default (running/stopped), 1 is going to suspend, 2 is going to resume */ /* Stats from App */ uint32_t opFrameDropped; @@ -151,20 +176,30 @@ struct BC_DTS_STATS { uint32_t DrvPIBMisses; uint32_t DrvPauseTime; uint32_t DrvRepeatedFrms; - uint32_t res1[13]; + /* + * BIT-31 MEANS READ Next PIB Info. + * Width will be in bit 0-16. + */ + uint64_t DrvNextMDataPLD; + uint32_t DrvcpbEmptySize; + + float Temperature; + uint32_t TempFromDriver; + uint32_t picNumFlags; + uint32_t res1[7]; -}; +} BC_DTS_STATS; -struct BC_PROC_INPUT { +typedef struct _BC_PROC_INPUT_ { uint8_t *pDmaBuff; uint32_t BuffSz; uint8_t Mapped; uint8_t Encrypted; uint8_t Rsrd[2]; uint32_t DramOffset; /* For debug use only */ -}; +} BC_PROC_INPUT, *PBC_PROC_INPUT; -struct BC_DEC_YUV_BUFFS { +typedef struct _BC_DEC_YUV_BUFFS { uint32_t b422Mode; uint8_t *YuvBuff; uint32_t YuvBuffSz; @@ -172,9 +207,9 @@ struct BC_DEC_YUV_BUFFS { uint32_t YBuffDoneSz; uint32_t UVBuffDoneSz; uint32_t RefCnt; -}; +} BC_DEC_YUV_BUFFS; -enum DECOUT_COMPLETION_FLAGS { +enum _DECOUT_COMPLETION_FLAGS{ COMP_FLAG_NO_INFO = 0x00, COMP_FLAG_FMT_CHANGE = 0x01, COMP_FLAG_PIB_VALID = 0x02, @@ -183,53 +218,51 @@ enum DECOUT_COMPLETION_FLAGS { COMP_FLAG_DATA_BOT = 0x10, }; -struct BC_DEC_OUT_BUFF { - struct BC_DEC_YUV_BUFFS OutPutBuffs; - struct BC_PIC_INFO_BLOCK PibInfo; +typedef struct _BC_DEC_OUT_BUFF{ + BC_DEC_YUV_BUFFS OutPutBuffs; +#if !defined(__KERNEL__) + C011_PIB PibInfo; +#else + struct C011_PIB PibInfo; +#endif uint32_t Flags; uint32_t BadFrCnt; -}; +} BC_DEC_OUT_BUFF; -struct BC_NOTIFY_MODE { +typedef struct _BC_NOTIFY_MODE { uint32_t Mode; uint32_t Rsvr[3]; -}; +} BC_NOTIFY_MODE; -struct BC_CLOCK { - uint32_t clk; - uint32_t Rsvr[3]; -}; - -struct BC_IOCTL_DATA { - enum BC_STATUS RetSts; +typedef struct _BC_IOCTL_DATA { + BC_STATUS RetSts; uint32_t IoctlDataSz; uint32_t Timeout; union { - struct BC_CMD_REG_ACC regAcc; - struct BC_CMD_DEV_MEM devMem; - struct BC_FW_CMD fwCmd; - struct BC_HW_TYPE hwType; - struct BC_PCI_CFG pciCfg; - struct BC_VERSION_INFO VerInfo; - struct BC_PROC_INPUT ProcInput; - struct BC_DEC_YUV_BUFFS RxBuffs; - struct BC_DEC_OUT_BUFF DecOutData; - struct BC_START_RX_CAP RxCap; - struct BC_FLUSH_RX_CAP FlushRxCap; - struct BC_DTS_STATS drvStat; - struct BC_NOTIFY_MODE NotifyMode; - struct BC_CLOCK clockValue; + BC_CMD_REG_ACC regAcc; + BC_CMD_DEV_MEM devMem; + BC_FW_CMD fwCmd; + BC_HW_TYPE hwType; + BC_PCI_CFG pciCfg; + BC_VERSION_INFO VerInfo; + BC_PROC_INPUT ProcInput; + BC_DEC_YUV_BUFFS RxBuffs; + BC_DEC_OUT_BUFF DecOutData; + BC_START_RX_CAP RxCap; + BC_FLUSH_RX_CAP FlushRxCap; + BC_DTS_STATS drvStat; + BC_NOTIFY_MODE NotifyMode; } u; struct _BC_IOCTL_DATA *next; -}; +} BC_IOCTL_DATA; -enum BC_DRV_CMD { +typedef enum _BC_DRV_CMD{ DRV_CMD_VERSION = 0, /* Get SW version */ DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */ DRV_CMD_REG_RD, /* Read Device Register */ DRV_CMD_REG_WR, /* Write Device Register */ DRV_CMD_FPGA_RD, /* Read FPGA Register */ - DRV_CMD_FPGA_WR, /* Write FPGA Register */ + DRV_CMD_FPGA_WR, /* Wrtie FPGA Reister */ DRV_CMD_MEM_RD, /* Read Device Memory */ DRV_CMD_MEM_WR, /* Write Device Memory */ DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */ @@ -240,61 +273,59 @@ enum BC_DRV_CMD { DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */ DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */ DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */ - DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now... - we will enhance this later*/ + DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/ DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */ DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */ - DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver - in which the application is Operating*/ - DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power - or improve performance */ + DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/ + DRV_CMD_RELEASE, /* Notify the driver to release user handle and application resources */ /* MUST be the last one.. */ DRV_CMD_END, /* End of the List.. */ -}; +} BC_DRV_CMD; #define BC_IOC_BASE 'b' #define BC_IOC_VOID _IOC_NONE #define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type) -#define BC_IOCTL_MB struct BC_IOCTL_DATA +#define BC_IOCTL_MB BC_IOCTL_DATA -#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB) -#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB) -#define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB) -#define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB) -#define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB) -#define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB) -#define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB) -#define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB) -#define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB) -#define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB) -#define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB) -#define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB) +#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB) +#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB) +#define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB) +#define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB) +#define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB) +#define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB) +#define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB) +#define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB) +#define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB) +#define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB) +#define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB) +#define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB) #define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB) -#define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB) +#define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB) #define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB) #define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB) #define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB) #define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB) -#define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB) -#define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB) -#define BCM_IOC_CHG_CLK BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB) -#define BCM_IOC_END BC_IOC_VOID +#define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB) +#define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB) +#define BCM_IOC_RELEASE BC_IOC_IOWR(DRV_CMD_RELEASE, BC_IOCTL_MB) +#define BCM_IOC_END BC_IOC_VOID /* Wrapper for main IOCTL data */ -struct crystalhd_ioctl_data { - struct BC_IOCTL_DATA udata; /* IOCTL from App..*/ +typedef struct _crystalhd_ioctl_data { + BC_IOCTL_DATA udata; /* IOCTL from App..*/ uint32_t u_id; /* Driver specific user ID */ uint32_t cmd; /* Cmd ID for driver's use. */ - void *add_cdata; /* Additional command specific data..*/ - uint32_t add_cdata_sz; /* Additional command specific data size */ - struct crystalhd_ioctl_data *next; /* List/Fifo management */ + void *add_cdata; /* Additional command specific data..*/ + uint32_t add_cdata_sz; /* Additional command specific data size */ + struct _crystalhd_ioctl_data *next; /* List/Fifo management */ +} crystalhd_ioctl_data; + +enum _crystalhd_kmod_ver{ + crystalhd_kmod_major = 3, + crystalhd_kmod_minor = 10, + crystalhd_kmod_rev = 0, }; -enum crystalhd_kmod_ver { - crystalhd_kmod_major = 0, - crystalhd_kmod_minor = 9, - crystalhd_kmod_rev = 27, -}; #endif --- crystalhd~/bcm_70012_regs.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/bcm_70012_regs.h 2011-03-14 23:02:54.000000000 +0300 @@ -203,6 +203,21 @@ ***************************************************************************/ #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ +#define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ /**************************************************************************** @@ -210,6 +225,47 @@ ***************************************************************************/ #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ +#define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ +#define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ +#define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ +#define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ +#define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_PHY + ***************************************************************************/ +#define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ +#define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ +#define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ +#define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ +#define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ /**************************************************************************** @@ -225,6 +281,60 @@ /**************************************************************************** + * BCM70012_TGT_TOP_MDIO + ***************************************************************************/ +#define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ +#define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ +#define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_TGT_RGR_BRIDGE + ***************************************************************************/ +#define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ +#define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ +#define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C + ***************************************************************************/ +#define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ +#define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ +#define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ +#define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ +#define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ +#define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ +#define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ +#define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ +#define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ +#define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ +#define I2C_CTL_REG 0x00000828 /* I2C Control Register */ +#define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ +#define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ +#define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ +#define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ +#define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ +#define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ +#define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ +#define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ +#define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ +#define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ +#define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C_GR_BRIDGE + ***************************************************************************/ +#define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ +#define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** * BCM70012_MISC_TOP_MISC1 ***************************************************************************/ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ @@ -310,6 +420,87 @@ #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ +#define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ +#define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ +#define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ +#define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ +#define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ +#define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ +#define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ +#define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ +#define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ +#define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ +#define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ +#define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ +#define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ +#define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ +#define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ +#define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ +#define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ +#define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ +#define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ +#define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ +#define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ +#define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ +#define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ +#define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ +#define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ +#define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ +#define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ +#define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ +#define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ +#define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ +#define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ +#define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ +#define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ +#define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ +#define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ +#define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ +#define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ +#define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ +#define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ +#define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ +#define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ +#define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ +#define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ +#define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ +#define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ +#define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ +#define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ +#define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ +#define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ +#define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ +#define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_GR_BRIDGE + ***************************************************************************/ +#define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ +#define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU + ***************************************************************************/ +#define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ +#define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ +#define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ +#define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ +#define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ +#define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU_RGR_BRIDGE + ***************************************************************************/ +#define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ +#define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ +#define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** @@ -342,6 +533,15 @@ /**************************************************************************** + * BCM70012_OTP_TOP_OTP_GR_BRIDGE + ***************************************************************************/ +#define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ +#define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** * BCM70012_AES_TOP_AES ***************************************************************************/ #define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ @@ -355,6 +555,16 @@ /**************************************************************************** + * BCM70012_AES_TOP_AES_RGR_BRIDGE + ***************************************************************************/ +#define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ +#define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ +#define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ + + +/**************************************************************************** * BCM70012_DCI_TOP_DCI ***************************************************************************/ #define DCI_CMD 0x00001c00 /* DCI Command Register */ @@ -373,380 +583,11712 @@ /**************************************************************************** - * BCM70012_TGT_TOP_INTR + * BCM70012_DCI_TOP_DCI_RGR_BRIDGE ***************************************************************************/ +#define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ +#define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ +#define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ + + /**************************************************************************** - * INTR :: INTR_STATUS + * BCM70012_CCE_TOP_CCE_RGR_BRIDGE ***************************************************************************/ -/* INTR :: INTR_STATUS :: reserved0 [31:26] */ -#define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 -#define INTR_INTR_STATUS_reserved0_ALIGN 0 -#define INTR_INTR_STATUS_reserved0_BITS 6 -#define INTR_INTR_STATUS_reserved0_SHIFT 26 +#define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ +#define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ +#define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ -/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 -/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_CFG + ***************************************************************************/ +/**************************************************************************** + * PCIE_CFG :: DEVICE_VENDOR_ID + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 + +/* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 -/* INTR :: INTR_STATUS :: reserved1 [23:14] */ -#define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 -#define INTR_INTR_STATUS_reserved1_ALIGN 0 -#define INTR_INTR_STATUS_reserved1_BITS 10 -#define INTR_INTR_STATUS_reserved1_SHIFT 14 -/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 +/**************************************************************************** + * PCIE_CFG :: STATUS_COMMAND + ***************************************************************************/ +/* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 + +/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 + +/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 + +/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 + +/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 + +/* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 + +/* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 + +/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 + +/* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 + +/* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 + +/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 + +/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 + +/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 + +/* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 + +/* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 + +/* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 + +/* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 + +/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 + +/* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 + +/* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 + +/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 + +/* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 -/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 +/**************************************************************************** + * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID + ***************************************************************************/ +/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 + +/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 -/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 +/**************************************************************************** + * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE + ***************************************************************************/ +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 -/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 -/* INTR :: INTR_STATUS :: reserved2 [07:06] */ -#define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 -#define INTR_INTR_STATUS_reserved2_ALIGN 0 -#define INTR_INTR_STATUS_reserved2_BITS 2 -#define INTR_INTR_STATUS_reserved2_SHIFT 6 +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_1 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 -/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 -/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_2 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_3 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 -/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 -/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_4 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 /**************************************************************************** - * MISC1 :: TX_SW_DESC_LIST_CTRL_STS + * PCIE_CFG :: CARDBUS_CIS_POINTER ***************************************************************************/ -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 +/* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 +/**************************************************************************** + * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID + ***************************************************************************/ +/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 + +/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 /**************************************************************************** - * MISC1 :: TX_DMA_ERROR_STATUS + * PCIE_CFG :: CAPABILITIES_POINTER ***************************************************************************/ -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 +/* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 +/**************************************************************************** + * PCIE_CFG :: INTERRUPT + ***************************************************************************/ +/* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 +#define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 + +/* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 +/**************************************************************************** + * PCIE_CFG :: VPD_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 +/**************************************************************************** + * PCIE_CFG :: VPD_DATA + ***************************************************************************/ +/* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ +#define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 +#define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 +/**************************************************************************** + * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 +/**************************************************************************** + * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS + ***************************************************************************/ +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 /**************************************************************************** - * MISC1 :: Y_RX_ERROR_STATUS + * PCIE_CFG :: MSI_CAPABILITY_HEADER ***************************************************************************/ -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +/**************************************************************************** + * PCIE_CFG :: MSI_LOWER_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 + +/* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER + ***************************************************************************/ +/* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_DATA + ***************************************************************************/ +/* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ +#define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 +#define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ +#define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff +#define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 +#define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 +#define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES + ***************************************************************************/ +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: SPARE + ***************************************************************************/ +/* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ +#define PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 +#define PCIE_CFG_SPARE_UNUSED_0_ALIGN 0 +#define PCIE_CFG_SPARE_UNUSED_0_BITS 16 +#define PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 + +/* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ +#define PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 +#define PCIE_CFG_SPARE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_SPARE_RESERVED_0_BITS 1 +#define PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 + +/* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ +#define PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc +#define PCIE_CFG_SPARE_UNUSED_1_ALIGN 0 +#define PCIE_CFG_SPARE_UNUSED_1_BITS 13 +#define PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 + +/* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_BITS 1 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 + +/* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_ALIGN 0 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_BITS 1 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCI_STATE + ***************************************************************************/ +/* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ +#define PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_PCI_STATE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_0_BITS 16 +#define PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_BITS 1 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 + +/* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ +#define PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 +#define PCIE_CFG_PCI_STATE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_1_BITS 3 +#define PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 + +/* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_BITS 3 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 + +/* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_ALIGN 0 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_BITS 1 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 + +/* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_ALIGN 0 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_BITS 1 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 + +/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_BITS 1 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 + +/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_ALIGN 0 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_BITS 1 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 + +/* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ +#define PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f +#define PCIE_CFG_PCI_STATE_RESERVED_2_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_2_BITS 5 +#define PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CLOCK_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 + +/* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 + +/* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 + +/* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_BITS 7 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 + +/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_BITS 7 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 + +/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_BITS 4 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_BITS 8 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: REGISTER_BASE + ***************************************************************************/ +/* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_BITS 14 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 + +/* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_BITS 16 +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 + +/* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_BITS 2 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MEMORY_BASE + ***************************************************************************/ +/* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_BITS 8 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 + +/* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_BITS 22 +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 + +/* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_BITS 2 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: REGISTER_DATA + ***************************************************************************/ +/* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_ALIGN 0 +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_BITS 32 +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MEMORY_DATA + ***************************************************************************/ +/* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_ALIGN 0 +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_BITS 32 +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_BAR_SIZE + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_BITS 28 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_BITS 4 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_BITS 32 +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_DATA + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_BITS 32 +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VPD_INTERFACE + ***************************************************************************/ +/* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_BITS 31 +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_ALIGN 0 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_BITS 1 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: INT_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: INT_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION + ***************************************************************************/ +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_BITS 4 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 + +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_BITS 20 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 + +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_BITS 8 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_EVENT + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_BITS 10 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_EVENT_MASK + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_BITS 9 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_PRESENT + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_BITS 1 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_BITS 10 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_BITS 1 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCIE_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_BITS 2 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_BITS 5 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_BITS 1 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_BITS 4 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_BITS 8 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_BITS 4 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_BITS 8 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_BITS 10 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_BITS 3 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BITS 3 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_BITS 8 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 + +/* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_BITS 5 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 + +/* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_BITS 1 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 + +/* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_BITS 3 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 + +/* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_BITS 3 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 + +/* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_BITS 2 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 + +/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_BITS 6 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 + +/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_BITS 4 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_BITS 3 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_BITS 2 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_BITS 6 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_BITS 4 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_BITS 7 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_BITS 2 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_CAPABILITIES_2 + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_BITS 27 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 + +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 + +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_BITS 4 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_STATUS_CONTROL_2 + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_BITS 27 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_BITS 4 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_CAPABILITIES_2 + ***************************************************************************/ +/* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_BITS 32 +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_STATUS_CONTROL_2 + ***************************************************************************/ +/* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_BITS 32 +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_MASK + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CORRECTABLE_ERROR_STATUS + ***************************************************************************/ +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 18 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 3 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 5 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CORRECTABLE_ERROR_MASK + ***************************************************************************/ +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_BITS 18 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_BITS 3 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_BITS 5 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_BITS 23 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_BITS 5 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_1 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_2 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_3 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_4 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_BITS 20 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_BITS 2 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_BITS 2 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_BITS 1 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_BITS 3 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_BITS 1 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_BITS 3 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_CAPABILITY_2 + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_BITS 8 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 + +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_BITS 16 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 + +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_BITS 8 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_BITS 15 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_BITS 1 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_BITS 12 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_BITS 3 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_BITS 1 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_BITS 7 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_BITS 6 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_BITS 4 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_BITS 3 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_BITS 4 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_BITS 3 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_STATUS + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_BITS 14 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_BITS 1 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_BITS 1 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_BITS 16 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_BITS 32 +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_BITS 32 +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_DATA_SELECT + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_BITS 24 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 + +/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_BITS 8 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_DATA + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_BITS 11 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_BITS 2 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_BITS 2 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_BITS 8 +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_BITS 31 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_BITS 1 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING + ***************************************************************************/ +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_BITS 25 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_TL + ***************************************************************************/ +/**************************************************************************** + * PCIE_TL :: TL_CONTROL + ***************************************************************************/ +/* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ +#define PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 +#define PCIE_TL_TL_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_0_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 + +/* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_BITS 1 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ +#define PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 +#define PCIE_TL_TL_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_1_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 + +/* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_ALIGN 0 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_BITS 1 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ +#define PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 +#define PCIE_TL_TL_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_2_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 + +/* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_BITS 1 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ +#define PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 +#define PCIE_TL_TL_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_3_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ +#define PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 +#define PCIE_TL_TL_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_4_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ +#define PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 +#define PCIE_TL_TL_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_5_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 + +/* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ +#define PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_BITS 1 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ +#define PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 +#define PCIE_TL_TL_CONTROL_RESERVED_6_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_6_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 + +/* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_ALIGN 0 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_BITS 1 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 +#define PCIE_TL_TL_CONTROL_NOT_USED_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_BITS 2 +#define PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 + +/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_BITS 3 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 + +/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_ALIGN 0 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_BITS 3 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_BITS 2 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f +#define PCIE_TL_TL_CONTROL_NOT_USED_1_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_1_BITS 6 +#define PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TRANSACTION_CONFIGURATION + ***************************************************************************/ +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_BITS 3 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_BITS 4 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:07] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000180 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_BITS 2 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 7 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_BITS 32 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 + ***************************************************************************/ +/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_ALIGN 0 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_BITS 32 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_BITS 32 +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_BITS 32 +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_BITS 8 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_BITS 4 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_BITS 4 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_BITS 5 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_BITS 11 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_BITS 13 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_BITS 5 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_BITS 5 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_BITS 16 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_BITS 2 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_BITS 5 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_BITS 19 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 + +/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_BITS 13 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_BITS 3 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_BITS 5 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_BITS 16 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_BITS 3 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_BITS 13 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_BITS 4 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_BITS 4 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_BITS 3 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_BITS 13 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_BITS 16 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_BITS 16 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_BITS 7 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_BITS 2 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_BITS 5 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_BITS 13 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_BITS 8 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_BITS 8 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO + ***************************************************************************/ +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_BITS 15 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_BITS 1 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_BITS 8 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_BITS 5 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_BITS 3 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TL_DEBUG + ***************************************************************************/ +/* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_ALIGN 0 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_BITS 1 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 + +/* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_ALIGN 0 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_BITS 1 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 + +/* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ +#define PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff +#define PCIE_TL_TL_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_DEBUG_RESERVED_0_BITS 30 +#define PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_DLL + ***************************************************************************/ +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_CONTROL + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:30] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0xc0000000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_BITS 2 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 30 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_BITS 2 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_BITS 8 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_STATUS + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_BITS 6 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 + +/* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_BITS 3 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_BITS 4 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 + +/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_BITS 2 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_BITS 5 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ATTENTION + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_BITS 26 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ATTENTION_MASK + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_BITS 24 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_BITS 2 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_REPLAY + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_BITS 9 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_BITS 13 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_BITS 10 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ACK_TIMEOUT + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_BITS 21 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_BITS 11 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD + ***************************************************************************/ +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_BITS 4 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_BITS 4 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_BITS 32 +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: ERROR_COUNT_THRESHOLD + ***************************************************************************/ +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_BITS 17 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_BITS 3 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: TL_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_BITS 8 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_BITS 8 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 + +/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_BITS 16 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DLLP_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_BITS 16 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_ALIGN 0 +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_BITS 16 +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: NAK_RECEIVED_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_BITS 16 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_ALIGN 0 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_BITS 16 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_TEST + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_BITS 16 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 + +/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 + +/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 + +/* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: PACKET_BIST + ***************************************************************************/ +/* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ +#define PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_BITS 8 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_BITS 1 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 + +/* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_BITS 1 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 + +/* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_BITS 11 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 + +/* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_BITS 7 +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 + +/* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_BITS 1 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: LINK_PCIE_1_1_CONTROL + ***************************************************************************/ +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_BITS 3 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_BITS 2 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_BITS 17 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_PHY + ***************************************************************************/ +/**************************************************************************** + * PCIE_PHY :: PHY_MODE + ***************************************************************************/ +/* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ +#define PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 +#define PCIE_PHY_PHY_MODE_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_MODE_RESERVED_0_BITS 28 +#define PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 + +/* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_ALIGN 0 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_BITS 1 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 + +/* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_ALIGN 0 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_BITS 1 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 + +/* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_ALIGN 0 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_BITS 1 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 + +/* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ +#define PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_BITS 1 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_STATUS + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_BITS 22 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 + +/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 + +/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 + +/* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 + +/* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 + +/* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 + +/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_LTSSM_CONTROL + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_N_FTS + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_BITS 7 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_BITS 1 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_ATTENTION + ***************************************************************************/ +/* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 + +/* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 + +/* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 + +/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 + +/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_ATTENTION_MASK + ***************************************************************************/ +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_BITS 20 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_TEST_CONTROL + ***************************************************************************/ +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_BITS 3 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_BITS 8 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_BITS 4 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE + ***************************************************************************/ +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_BITS 14 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_BITS 2 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_BITS 10 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE + ***************************************************************************/ +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_BITS 12 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_BITS 8 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_BITS 8 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES + ***************************************************************************/ +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_BITS 22 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 + +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_BITS 6 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 + +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_BITS 4 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES + ***************************************************************************/ +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_BITS 32 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_INTR + ***************************************************************************/ +/**************************************************************************** + * INTR :: INTR_STATUS + ***************************************************************************/ +/* INTR :: INTR_STATUS :: reserved0 [31:26] */ +#define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 +#define INTR_INTR_STATUS_reserved0_ALIGN 0 +#define INTR_INTR_STATUS_reserved0_BITS 6 +#define INTR_INTR_STATUS_reserved0_SHIFT 26 + +/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_STATUS :: reserved1 [23:14] */ +#define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 +#define INTR_INTR_STATUS_reserved1_ALIGN 0 +#define INTR_INTR_STATUS_reserved1_BITS 10 +#define INTR_INTR_STATUS_reserved1_SHIFT 14 + +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 + +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 + +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 + +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 + +/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 + +/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 + +/* INTR :: INTR_STATUS :: reserved2 [07:06] */ +#define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 +#define INTR_INTR_STATUS_reserved2_ALIGN 0 +#define INTR_INTR_STATUS_reserved2_BITS 2 +#define INTR_INTR_STATUS_reserved2_SHIFT 6 + +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 + +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 + +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 + +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 + +/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 + +/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_SET + ***************************************************************************/ +/* INTR :: INTR_SET :: reserved0 [31:26] */ +#define INTR_INTR_SET_reserved0_MASK 0xfc000000 +#define INTR_INTR_SET_reserved0_ALIGN 0 +#define INTR_INTR_SET_reserved0_BITS 6 +#define INTR_INTR_SET_reserved0_SHIFT 26 + +/* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_SET :: reserved1 [23:14] */ +#define INTR_INTR_SET_reserved1_MASK 0x00ffc000 +#define INTR_INTR_SET_reserved1_ALIGN 0 +#define INTR_INTR_SET_reserved1_BITS 10 +#define INTR_INTR_SET_reserved1_SHIFT 14 + +/* INTR :: INTR_SET :: UV_RX_DMA_L1_ERR_INTR [13:13] */ +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_MASK 0x00002000 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_SHIFT 13 + +/* INTR :: INTR_SET :: UV_RX_DMA_L1_DONE_INTR [12:12] */ +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_MASK 0x00001000 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_SHIFT 12 + +/* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 + +/* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 + +/* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 + +/* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 + +/* INTR :: INTR_SET :: reserved2 [07:06] */ +#define INTR_INTR_SET_reserved2_MASK 0x000000c0 +#define INTR_INTR_SET_reserved2_ALIGN 0 +#define INTR_INTR_SET_reserved2_BITS 2 +#define INTR_INTR_SET_reserved2_SHIFT 6 + +/* INTR :: INTR_SET :: UV_RX_DMA_L0_ERR_INTR [05:05] */ +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_MASK 0x00000020 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_SHIFT 5 + +/* INTR :: INTR_SET :: UV_RX_DMA_L0_DONE_INTR [04:04] */ +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_MASK 0x00000010 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_SHIFT 4 + +/* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 + +/* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 + +/* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 + +/* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_CLR_REG + ***************************************************************************/ +/* INTR :: INTR_CLR_REG :: reserved0 [31:26] */ +#define INTR_INTR_CLR_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_CLR_REG_reserved0_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved0_BITS 6 +#define INTR_INTR_CLR_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_CLR_REG :: reserved1 [23:14] */ +#define INTR_INTR_CLR_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_CLR_REG_reserved1_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved1_BITS 10 +#define INTR_INTR_CLR_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_CLR [13:13] */ +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_SHIFT 13 + +/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_CLR [12:12] */ +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_SHIFT 12 + +/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 + +/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 + +/* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 + +/* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 + +/* INTR :: INTR_CLR_REG :: reserved2 [07:06] */ +#define INTR_INTR_CLR_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_CLR_REG_reserved2_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved2_BITS 2 +#define INTR_INTR_CLR_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_CLR [05:05] */ +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_SHIFT 5 + +/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_CLR [04:04] */ +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_SHIFT 4 + +/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 + +/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 + +/* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 + +/* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_STS_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_STS_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_STS_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_STS_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_STS_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_STS_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_STS_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_STS_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_ERR_INTR_MSK [13:13] */ +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SHIFT 13 + +/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_DONE_INTR_MSK [12:12] */ +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SHIFT 12 + +/* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 + +/* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 + +/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 + +/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 + +/* INTR :: INTR_MSK_STS_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_STS_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_STS_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_STS_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_ERR_INTR_MSK [05:05] */ +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SHIFT 5 + +/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_DONE_INTR_MSK [04:04] */ +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SHIFT 4 + +/* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 + +/* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 + +/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 + +/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_SET_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_SET_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_SET_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_SET_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_SET_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_SET_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_SET_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_SET_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_SET [13:13] */ +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 + +/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_SET [12:12] */ +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 + +/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 + +/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 + +/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 + +/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 + +/* INTR :: INTR_MSK_SET_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_SET_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_SET_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_SET_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_SET [05:05] */ +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 + +/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_SET [04:04] */ +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 + +/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 + +/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 + +/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 + +/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_CLR_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_CLR_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_CLR_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 + +/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 + +/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 + +/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 + +/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 + +/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 + +/* INTR :: INTR_MSK_CLR_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_CLR_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 + +/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 + +/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 + +/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 + +/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 + +/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 + + +/**************************************************************************** + * INTR :: EOI_CTRL + ***************************************************************************/ +/* INTR :: EOI_CTRL :: reserved0 [31:01] */ +#define INTR_EOI_CTRL_reserved0_MASK 0xfffffffe +#define INTR_EOI_CTRL_reserved0_ALIGN 0 +#define INTR_EOI_CTRL_reserved0_BITS 31 +#define INTR_EOI_CTRL_reserved0_SHIFT 1 + +/* INTR :: EOI_CTRL :: EOI [00:00] */ +#define INTR_EOI_CTRL_EOI_MASK 0x00000001 +#define INTR_EOI_CTRL_EOI_ALIGN 0 +#define INTR_EOI_CTRL_EOI_BITS 1 +#define INTR_EOI_CTRL_EOI_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_MDIO + ***************************************************************************/ +/**************************************************************************** + * MDIO :: CTRL0 + ***************************************************************************/ +/* MDIO :: CTRL0 :: reserved0 [31:22] */ +#define MDIO_CTRL0_reserved0_MASK 0xffc00000 +#define MDIO_CTRL0_reserved0_ALIGN 0 +#define MDIO_CTRL0_reserved0_BITS 10 +#define MDIO_CTRL0_reserved0_SHIFT 22 + +/* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ +#define MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 +#define MDIO_CTRL0_WRITE_READ_COMMAND_ALIGN 0 +#define MDIO_CTRL0_WRITE_READ_COMMAND_BITS 1 +#define MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 + +/* MDIO :: CTRL0 :: PHYAD [20:16] */ +#define MDIO_CTRL0_PHYAD_MASK 0x001f0000 +#define MDIO_CTRL0_PHYAD_ALIGN 0 +#define MDIO_CTRL0_PHYAD_BITS 5 +#define MDIO_CTRL0_PHYAD_SHIFT 16 + +/* MDIO :: CTRL0 :: reserved1 [15:05] */ +#define MDIO_CTRL0_reserved1_MASK 0x0000ffe0 +#define MDIO_CTRL0_reserved1_ALIGN 0 +#define MDIO_CTRL0_reserved1_BITS 11 +#define MDIO_CTRL0_reserved1_SHIFT 5 + +/* MDIO :: CTRL0 :: REGAD [04:00] */ +#define MDIO_CTRL0_REGAD_MASK 0x0000001f +#define MDIO_CTRL0_REGAD_ALIGN 0 +#define MDIO_CTRL0_REGAD_BITS 5 +#define MDIO_CTRL0_REGAD_SHIFT 0 + + +/**************************************************************************** + * MDIO :: CTRL1 + ***************************************************************************/ +/* MDIO :: CTRL1 :: WR_STATUS [31:31] */ +#define MDIO_CTRL1_WR_STATUS_MASK 0x80000000 +#define MDIO_CTRL1_WR_STATUS_ALIGN 0 +#define MDIO_CTRL1_WR_STATUS_BITS 1 +#define MDIO_CTRL1_WR_STATUS_SHIFT 31 + +/* MDIO :: CTRL1 :: reserved0 [30:16] */ +#define MDIO_CTRL1_reserved0_MASK 0x7fff0000 +#define MDIO_CTRL1_reserved0_ALIGN 0 +#define MDIO_CTRL1_reserved0_BITS 15 +#define MDIO_CTRL1_reserved0_SHIFT 16 + +/* MDIO :: CTRL1 :: Write_Data [15:00] */ +#define MDIO_CTRL1_Write_Data_MASK 0x0000ffff +#define MDIO_CTRL1_Write_Data_ALIGN 0 +#define MDIO_CTRL1_Write_Data_BITS 16 +#define MDIO_CTRL1_Write_Data_SHIFT 0 + + +/**************************************************************************** + * MDIO :: CTRL2 + ***************************************************************************/ +/* MDIO :: CTRL2 :: RD_STATUS [31:31] */ +#define MDIO_CTRL2_RD_STATUS_MASK 0x80000000 +#define MDIO_CTRL2_RD_STATUS_ALIGN 0 +#define MDIO_CTRL2_RD_STATUS_BITS 1 +#define MDIO_CTRL2_RD_STATUS_SHIFT 31 + +/* MDIO :: CTRL2 :: reserved0 [30:16] */ +#define MDIO_CTRL2_reserved0_MASK 0x7fff0000 +#define MDIO_CTRL2_reserved0_ALIGN 0 +#define MDIO_CTRL2_reserved0_BITS 15 +#define MDIO_CTRL2_reserved0_SHIFT 16 + +/* MDIO :: CTRL2 :: Read_Data [15:00] */ +#define MDIO_CTRL2_Read_Data_MASK 0x0000ffff +#define MDIO_CTRL2_Read_Data_ALIGN 0 +#define MDIO_CTRL2_Read_Data_BITS 16 +#define MDIO_CTRL2_Read_Data_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_TGT_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * TGT_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define TGT_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define TGT_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define TGT_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_BITS 1 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 + +/* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_BITS 1 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_ALIGN 0 +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_BITS 16 +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C + ***************************************************************************/ +/**************************************************************************** + * I2C :: CHIP_ADDRESS + ***************************************************************************/ +/* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ +#define I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 +#define I2C_CHIP_ADDRESS_reserved0_ALIGN 0 +#define I2C_CHIP_ADDRESS_reserved0_BITS 24 +#define I2C_CHIP_ADDRESS_reserved0_SHIFT 8 + +/* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_ALIGN 0 +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_BITS 7 +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 + +/* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ +#define I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 +#define I2C_CHIP_ADDRESS_RESERVED_ALIGN 0 +#define I2C_CHIP_ADDRESS_RESERVED_BITS 1 +#define I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN0 + ***************************************************************************/ +/* I2C :: DATA_IN0 :: reserved0 [31:08] */ +#define I2C_DATA_IN0_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN0_reserved0_ALIGN 0 +#define I2C_DATA_IN0_reserved0_BITS 24 +#define I2C_DATA_IN0_reserved0_SHIFT 8 + +/* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ +#define I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff +#define I2C_DATA_IN0_DATA_IN0_ALIGN 0 +#define I2C_DATA_IN0_DATA_IN0_BITS 8 +#define I2C_DATA_IN0_DATA_IN0_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN1 + ***************************************************************************/ +/* I2C :: DATA_IN1 :: reserved0 [31:08] */ +#define I2C_DATA_IN1_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN1_reserved0_ALIGN 0 +#define I2C_DATA_IN1_reserved0_BITS 24 +#define I2C_DATA_IN1_reserved0_SHIFT 8 + +/* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ +#define I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff +#define I2C_DATA_IN1_DATA_IN1_ALIGN 0 +#define I2C_DATA_IN1_DATA_IN1_BITS 8 +#define I2C_DATA_IN1_DATA_IN1_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN2 + ***************************************************************************/ +/* I2C :: DATA_IN2 :: reserved0 [31:08] */ +#define I2C_DATA_IN2_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN2_reserved0_ALIGN 0 +#define I2C_DATA_IN2_reserved0_BITS 24 +#define I2C_DATA_IN2_reserved0_SHIFT 8 + +/* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ +#define I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff +#define I2C_DATA_IN2_DATA_IN2_ALIGN 0 +#define I2C_DATA_IN2_DATA_IN2_BITS 8 +#define I2C_DATA_IN2_DATA_IN2_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN3 + ***************************************************************************/ +/* I2C :: DATA_IN3 :: reserved0 [31:08] */ +#define I2C_DATA_IN3_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN3_reserved0_ALIGN 0 +#define I2C_DATA_IN3_reserved0_BITS 24 +#define I2C_DATA_IN3_reserved0_SHIFT 8 + +/* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ +#define I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff +#define I2C_DATA_IN3_DATA_IN3_ALIGN 0 +#define I2C_DATA_IN3_DATA_IN3_BITS 8 +#define I2C_DATA_IN3_DATA_IN3_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN4 + ***************************************************************************/ +/* I2C :: DATA_IN4 :: reserved0 [31:08] */ +#define I2C_DATA_IN4_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN4_reserved0_ALIGN 0 +#define I2C_DATA_IN4_reserved0_BITS 24 +#define I2C_DATA_IN4_reserved0_SHIFT 8 + +/* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ +#define I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff +#define I2C_DATA_IN4_DATA_IN4_ALIGN 0 +#define I2C_DATA_IN4_DATA_IN4_BITS 8 +#define I2C_DATA_IN4_DATA_IN4_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN5 + ***************************************************************************/ +/* I2C :: DATA_IN5 :: reserved0 [31:08] */ +#define I2C_DATA_IN5_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN5_reserved0_ALIGN 0 +#define I2C_DATA_IN5_reserved0_BITS 24 +#define I2C_DATA_IN5_reserved0_SHIFT 8 + +/* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ +#define I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff +#define I2C_DATA_IN5_DATA_IN5_ALIGN 0 +#define I2C_DATA_IN5_DATA_IN5_BITS 8 +#define I2C_DATA_IN5_DATA_IN5_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN6 + ***************************************************************************/ +/* I2C :: DATA_IN6 :: reserved0 [31:08] */ +#define I2C_DATA_IN6_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN6_reserved0_ALIGN 0 +#define I2C_DATA_IN6_reserved0_BITS 24 +#define I2C_DATA_IN6_reserved0_SHIFT 8 + +/* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ +#define I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff +#define I2C_DATA_IN6_DATA_IN6_ALIGN 0 +#define I2C_DATA_IN6_DATA_IN6_BITS 8 +#define I2C_DATA_IN6_DATA_IN6_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN7 + ***************************************************************************/ +/* I2C :: DATA_IN7 :: reserved0 [31:08] */ +#define I2C_DATA_IN7_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN7_reserved0_ALIGN 0 +#define I2C_DATA_IN7_reserved0_BITS 24 +#define I2C_DATA_IN7_reserved0_SHIFT 8 + +/* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ +#define I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff +#define I2C_DATA_IN7_DATA_IN7_ALIGN 0 +#define I2C_DATA_IN7_DATA_IN7_BITS 8 +#define I2C_DATA_IN7_DATA_IN7_SHIFT 0 + + +/**************************************************************************** + * I2C :: CNT_REG + ***************************************************************************/ +/* I2C :: CNT_REG :: reserved0 [31:08] */ +#define I2C_CNT_REG_reserved0_MASK 0xffffff00 +#define I2C_CNT_REG_reserved0_ALIGN 0 +#define I2C_CNT_REG_reserved0_BITS 24 +#define I2C_CNT_REG_reserved0_SHIFT 8 + +/* I2C :: CNT_REG :: CNT_REG2 [07:04] */ +#define I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 +#define I2C_CNT_REG_CNT_REG2_ALIGN 0 +#define I2C_CNT_REG_CNT_REG2_BITS 4 +#define I2C_CNT_REG_CNT_REG2_SHIFT 4 + +/* I2C :: CNT_REG :: CNT_REG1 [03:00] */ +#define I2C_CNT_REG_CNT_REG1_MASK 0x0000000f +#define I2C_CNT_REG_CNT_REG1_ALIGN 0 +#define I2C_CNT_REG_CNT_REG1_BITS 4 +#define I2C_CNT_REG_CNT_REG1_SHIFT 0 + + +/**************************************************************************** + * I2C :: CTL_REG + ***************************************************************************/ +/* I2C :: CTL_REG :: reserved0 [31:08] */ +#define I2C_CTL_REG_reserved0_MASK 0xffffff00 +#define I2C_CTL_REG_reserved0_ALIGN 0 +#define I2C_CTL_REG_reserved0_BITS 24 +#define I2C_CTL_REG_reserved0_SHIFT 8 + +/* I2C :: CTL_REG :: DIV_CLK [07:07] */ +#define I2C_CTL_REG_DIV_CLK_MASK 0x00000080 +#define I2C_CTL_REG_DIV_CLK_ALIGN 0 +#define I2C_CTL_REG_DIV_CLK_BITS 1 +#define I2C_CTL_REG_DIV_CLK_SHIFT 7 + +/* I2C :: CTL_REG :: INT_EN [06:06] */ +#define I2C_CTL_REG_INT_EN_MASK 0x00000040 +#define I2C_CTL_REG_INT_EN_ALIGN 0 +#define I2C_CTL_REG_INT_EN_BITS 1 +#define I2C_CTL_REG_INT_EN_SHIFT 6 + +/* I2C :: CTL_REG :: SCL_SEL [05:04] */ +#define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 +#define I2C_CTL_REG_SCL_SEL_ALIGN 0 +#define I2C_CTL_REG_SCL_SEL_BITS 2 +#define I2C_CTL_REG_SCL_SEL_SHIFT 4 + +/* I2C :: CTL_REG :: DELAY_DIS [03:03] */ +#define I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 +#define I2C_CTL_REG_DELAY_DIS_ALIGN 0 +#define I2C_CTL_REG_DELAY_DIS_BITS 1 +#define I2C_CTL_REG_DELAY_DIS_SHIFT 3 + +/* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ +#define I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 +#define I2C_CTL_REG_DEGLITCH_DIS_ALIGN 0 +#define I2C_CTL_REG_DEGLITCH_DIS_BITS 1 +#define I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 + +/* I2C :: CTL_REG :: DTF [01:00] */ +#define I2C_CTL_REG_DTF_MASK 0x00000003 +#define I2C_CTL_REG_DTF_ALIGN 0 +#define I2C_CTL_REG_DTF_BITS 2 +#define I2C_CTL_REG_DTF_SHIFT 0 + + +/**************************************************************************** + * I2C :: IIC_ENABLE + ***************************************************************************/ +/* I2C :: IIC_ENABLE :: reserved0 [31:07] */ +#define I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 +#define I2C_IIC_ENABLE_reserved0_ALIGN 0 +#define I2C_IIC_ENABLE_reserved0_BITS 25 +#define I2C_IIC_ENABLE_reserved0_SHIFT 7 + +/* I2C :: IIC_ENABLE :: RESTART [06:06] */ +#define I2C_IIC_ENABLE_RESTART_MASK 0x00000040 +#define I2C_IIC_ENABLE_RESTART_ALIGN 0 +#define I2C_IIC_ENABLE_RESTART_BITS 1 +#define I2C_IIC_ENABLE_RESTART_SHIFT 6 + +/* I2C :: IIC_ENABLE :: NO_START [05:05] */ +#define I2C_IIC_ENABLE_NO_START_MASK 0x00000020 +#define I2C_IIC_ENABLE_NO_START_ALIGN 0 +#define I2C_IIC_ENABLE_NO_START_BITS 1 +#define I2C_IIC_ENABLE_NO_START_SHIFT 5 + +/* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ +#define I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 +#define I2C_IIC_ENABLE_NO_STOP_ALIGN 0 +#define I2C_IIC_ENABLE_NO_STOP_BITS 1 +#define I2C_IIC_ENABLE_NO_STOP_SHIFT 4 + +/* I2C :: IIC_ENABLE :: reserved1 [03:03] */ +#define I2C_IIC_ENABLE_reserved1_MASK 0x00000008 +#define I2C_IIC_ENABLE_reserved1_ALIGN 0 +#define I2C_IIC_ENABLE_reserved1_BITS 1 +#define I2C_IIC_ENABLE_reserved1_SHIFT 3 + +/* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ +#define I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 +#define I2C_IIC_ENABLE_NO_ACK_ALIGN 0 +#define I2C_IIC_ENABLE_NO_ACK_BITS 1 +#define I2C_IIC_ENABLE_NO_ACK_SHIFT 2 + +/* I2C :: IIC_ENABLE :: INTRP [01:01] */ +#define I2C_IIC_ENABLE_INTRP_MASK 0x00000002 +#define I2C_IIC_ENABLE_INTRP_ALIGN 0 +#define I2C_IIC_ENABLE_INTRP_BITS 1 +#define I2C_IIC_ENABLE_INTRP_SHIFT 1 + +/* I2C :: IIC_ENABLE :: ENABLE [00:00] */ +#define I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 +#define I2C_IIC_ENABLE_ENABLE_ALIGN 0 +#define I2C_IIC_ENABLE_ENABLE_BITS 1 +#define I2C_IIC_ENABLE_ENABLE_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT0 + ***************************************************************************/ +/* I2C :: DATA_OUT0 :: reserved0 [31:08] */ +#define I2C_DATA_OUT0_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT0_reserved0_ALIGN 0 +#define I2C_DATA_OUT0_reserved0_BITS 24 +#define I2C_DATA_OUT0_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ +#define I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff +#define I2C_DATA_OUT0_DATA_OUT0_ALIGN 0 +#define I2C_DATA_OUT0_DATA_OUT0_BITS 8 +#define I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT1 + ***************************************************************************/ +/* I2C :: DATA_OUT1 :: reserved0 [31:08] */ +#define I2C_DATA_OUT1_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT1_reserved0_ALIGN 0 +#define I2C_DATA_OUT1_reserved0_BITS 24 +#define I2C_DATA_OUT1_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ +#define I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff +#define I2C_DATA_OUT1_DATA_OUT1_ALIGN 0 +#define I2C_DATA_OUT1_DATA_OUT1_BITS 8 +#define I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT2 + ***************************************************************************/ +/* I2C :: DATA_OUT2 :: reserved0 [31:08] */ +#define I2C_DATA_OUT2_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT2_reserved0_ALIGN 0 +#define I2C_DATA_OUT2_reserved0_BITS 24 +#define I2C_DATA_OUT2_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ +#define I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff +#define I2C_DATA_OUT2_DATA_OUT2_ALIGN 0 +#define I2C_DATA_OUT2_DATA_OUT2_BITS 8 +#define I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT3 + ***************************************************************************/ +/* I2C :: DATA_OUT3 :: reserved0 [31:08] */ +#define I2C_DATA_OUT3_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT3_reserved0_ALIGN 0 +#define I2C_DATA_OUT3_reserved0_BITS 24 +#define I2C_DATA_OUT3_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ +#define I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff +#define I2C_DATA_OUT3_DATA_OUT3_ALIGN 0 +#define I2C_DATA_OUT3_DATA_OUT3_BITS 8 +#define I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT4 + ***************************************************************************/ +/* I2C :: DATA_OUT4 :: reserved0 [31:08] */ +#define I2C_DATA_OUT4_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT4_reserved0_ALIGN 0 +#define I2C_DATA_OUT4_reserved0_BITS 24 +#define I2C_DATA_OUT4_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ +#define I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff +#define I2C_DATA_OUT4_DATA_OUT4_ALIGN 0 +#define I2C_DATA_OUT4_DATA_OUT4_BITS 8 +#define I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT5 + ***************************************************************************/ +/* I2C :: DATA_OUT5 :: reserved0 [31:08] */ +#define I2C_DATA_OUT5_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT5_reserved0_ALIGN 0 +#define I2C_DATA_OUT5_reserved0_BITS 24 +#define I2C_DATA_OUT5_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ +#define I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff +#define I2C_DATA_OUT5_DATA_OUT5_ALIGN 0 +#define I2C_DATA_OUT5_DATA_OUT5_BITS 8 +#define I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT6 + ***************************************************************************/ +/* I2C :: DATA_OUT6 :: reserved0 [31:08] */ +#define I2C_DATA_OUT6_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT6_reserved0_ALIGN 0 +#define I2C_DATA_OUT6_reserved0_BITS 24 +#define I2C_DATA_OUT6_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ +#define I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff +#define I2C_DATA_OUT6_DATA_OUT6_ALIGN 0 +#define I2C_DATA_OUT6_DATA_OUT6_BITS 8 +#define I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT7 + ***************************************************************************/ +/* I2C :: DATA_OUT7 :: reserved0 [31:08] */ +#define I2C_DATA_OUT7_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT7_reserved0_ALIGN 0 +#define I2C_DATA_OUT7_reserved0_BITS 24 +#define I2C_DATA_OUT7_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ +#define I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff +#define I2C_DATA_OUT7_DATA_OUT7_ALIGN 0 +#define I2C_DATA_OUT7_DATA_OUT7_BITS 8 +#define I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 + + +/**************************************************************************** + * I2C :: CTLHI_REG + ***************************************************************************/ +/* I2C :: CTLHI_REG :: reserved0 [31:02] */ +#define I2C_CTLHI_REG_reserved0_MASK 0xfffffffc +#define I2C_CTLHI_REG_reserved0_ALIGN 0 +#define I2C_CTLHI_REG_reserved0_BITS 30 +#define I2C_CTLHI_REG_reserved0_SHIFT 2 + +/* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ +#define I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 +#define I2C_CTLHI_REG_IGNORE_ACK_ALIGN 0 +#define I2C_CTLHI_REG_IGNORE_ACK_BITS 1 +#define I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 + +/* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ +#define I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 +#define I2C_CTLHI_REG_WAIT_DIS_ALIGN 0 +#define I2C_CTLHI_REG_WAIT_DIS_BITS 1 +#define I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 + + +/**************************************************************************** + * I2C :: SCL_PARAM + ***************************************************************************/ +/* I2C :: SCL_PARAM :: reserved0 [31:00] */ +#define I2C_SCL_PARAM_reserved0_MASK 0xffffffff +#define I2C_SCL_PARAM_reserved0_ALIGN 0 +#define I2C_SCL_PARAM_reserved0_BITS 32 +#define I2C_SCL_PARAM_reserved0_SHIFT 0 + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * I2C_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define I2C_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define I2C_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define I2C_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC1 + ***************************************************************************/ +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_BITS 1 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_BITS 1 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_BITS 8 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 + +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_BITS 22 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 + +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_BITS 2 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_BITS 8 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 + +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_BITS 22 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 + +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_BITS 2 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: DMA_DEBUG_OPTIONS_REG + ***************************************************************************/ +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_BITS 23 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: READ_CHANNEL_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: PCIE_DMA_CTRL + ***************************************************************************/ +/* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ +#define MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 +#define MISC1_PCIE_DMA_CTRL_reserved0_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved0_BITS 14 +#define MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 + +/* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_BITS 2 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 + +/* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:10] */ +#define MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fc00 +#define MISC1_PCIE_DMA_CTRL_reserved1_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved1_BITS 6 +#define MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 10 + +/* MISC1 :: PCIE_DMA_CTRL :: EN_WEIGHTED_RR [09:09] */ +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_MASK 0x00000200 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_BITS 1 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_SHIFT 9 + +/* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_BITS 1 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 + +/* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ +#define MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 +#define MISC1_PCIE_DMA_CTRL_reserved2_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved2_BITS 3 +#define MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 + +/* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_BITS 1 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 + +/* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_BITS 1 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 + +/* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_BITS 3 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC2 + ***************************************************************************/ +/**************************************************************************** + * MISC2 :: GLOBAL_CTRL + ***************************************************************************/ +/* MISC2 :: GLOBAL_CTRL :: reserved0 [31:21] */ +#define MISC2_GLOBAL_CTRL_reserved0_MASK 0xffe00000 +#define MISC2_GLOBAL_CTRL_reserved0_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved0_BITS 11 +#define MISC2_GLOBAL_CTRL_reserved0_SHIFT 21 + +/* MISC2 :: GLOBAL_CTRL :: EN_WRITE_ALL [20:20] */ +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_MASK 0x00100000 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_SHIFT 20 + +/* MISC2 :: GLOBAL_CTRL :: reserved1 [19:17] */ +#define MISC2_GLOBAL_CTRL_reserved1_MASK 0x000e0000 +#define MISC2_GLOBAL_CTRL_reserved1_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved1_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved1_SHIFT 17 + +/* MISC2 :: GLOBAL_CTRL :: EN_SINGLE_DMA [16:16] */ +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_MASK 0x00010000 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_SHIFT 16 + +/* MISC2 :: GLOBAL_CTRL :: reserved2 [15:11] */ +#define MISC2_GLOBAL_CTRL_reserved2_MASK 0x0000f800 +#define MISC2_GLOBAL_CTRL_reserved2_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved2_BITS 5 +#define MISC2_GLOBAL_CTRL_reserved2_SHIFT 11 + +/* MISC2 :: GLOBAL_CTRL :: Y_UV_FIFO_LEN_SEL [10:10] */ +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_MASK 0x00000400 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_ALIGN 0 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_BITS 1 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_SHIFT 10 + +/* MISC2 :: GLOBAL_CTRL :: ODD_DE_EOFRST_DIS [09:09] */ +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_MASK 0x00000200 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_ALIGN 0 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_BITS 1 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_SHIFT 9 + +/* MISC2 :: GLOBAL_CTRL :: DIS_BIT_STUFFING [08:08] */ +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_MASK 0x00000100 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_ALIGN 0 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_BITS 1 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_SHIFT 8 + +/* MISC2 :: GLOBAL_CTRL :: reserved3 [07:05] */ +#define MISC2_GLOBAL_CTRL_reserved3_MASK 0x000000e0 +#define MISC2_GLOBAL_CTRL_reserved3_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved3_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved3_SHIFT 5 + +/* MISC2 :: GLOBAL_CTRL :: EN_PROG_MODE [04:04] */ +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_MASK 0x00000010 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_SHIFT 4 + +/* MISC2 :: GLOBAL_CTRL :: reserved4 [03:01] */ +#define MISC2_GLOBAL_CTRL_reserved4_MASK 0x0000000e +#define MISC2_GLOBAL_CTRL_reserved4_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved4_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved4_SHIFT 1 + +/* MISC2 :: GLOBAL_CTRL :: EN_188B [00:00] */ +#define MISC2_GLOBAL_CTRL_EN_188B_MASK 0x00000001 +#define MISC2_GLOBAL_CTRL_EN_188B_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_188B_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_188B_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: INTERNAL_STATUS + ***************************************************************************/ +/* MISC2 :: INTERNAL_STATUS :: reserved0 [31:12] */ +#define MISC2_INTERNAL_STATUS_reserved0_MASK 0xfffff000 +#define MISC2_INTERNAL_STATUS_reserved0_ALIGN 0 +#define MISC2_INTERNAL_STATUS_reserved0_BITS 20 +#define MISC2_INTERNAL_STATUS_reserved0_SHIFT 12 + +/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_FULL [11:11] */ +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_MASK 0x00000800 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_SHIFT 11 + +/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_FULL [10:10] */ +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_MASK 0x00000400 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_SHIFT 10 + +/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_FULL [09:09] */ +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_SHIFT 9 + +/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_FULL [08:08] */ +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_MASK 0x00000100 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_SHIFT 8 + +/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_EMPTY [07:07] */ +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000080 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_SHIFT 7 + +/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_EMPTY [06:06] */ +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_MASK 0x00000040 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_SHIFT 6 + +/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_EMPTY [05:05] */ +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 + +/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_EMPTY [04:04] */ +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_MASK 0x00000010 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_SHIFT 4 + +/* MISC2 :: INTERNAL_STATUS :: reserved1 [03:00] */ +#define MISC2_INTERNAL_STATUS_reserved1_MASK 0x0000000f +#define MISC2_INTERNAL_STATUS_reserved1_ALIGN 0 +#define MISC2_INTERNAL_STATUS_reserved1_BITS 4 +#define MISC2_INTERNAL_STATUS_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: INTERNAL_STATUS_MUX_CTRL + ***************************************************************************/ +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_BITS 16 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_BITS 1 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_BITS 3 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_BITS 3 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_BITS 1 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_BITS 4 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_BITS 4 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: DEBUG_FIFO_LENGTH + ***************************************************************************/ +/* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_ALIGN 0 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_BITS 11 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 + +/* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_ALIGN 0 +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_BITS 21 +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC3 + ***************************************************************************/ +/**************************************************************************** + * MISC3 :: RESET_CTRL + ***************************************************************************/ +/* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ +#define MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 +#define MISC3_RESET_CTRL_reserved0_ALIGN 0 +#define MISC3_RESET_CTRL_reserved0_BITS 23 +#define MISC3_RESET_CTRL_reserved0_SHIFT 9 + +/* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ +#define MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 +#define MISC3_RESET_CTRL_PLL_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_PLL_RESET_BITS 1 +#define MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 + +/* MISC3 :: RESET_CTRL :: reserved1 [07:02] */ +#define MISC3_RESET_CTRL_reserved1_MASK 0x000000fc +#define MISC3_RESET_CTRL_reserved1_ALIGN 0 +#define MISC3_RESET_CTRL_reserved1_BITS 6 +#define MISC3_RESET_CTRL_reserved1_SHIFT 2 + +/* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ +#define MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 +#define MISC3_RESET_CTRL_POR_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_POR_RESET_BITS 1 +#define MISC3_RESET_CTRL_POR_RESET_SHIFT 1 + +/* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ +#define MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 +#define MISC3_RESET_CTRL_CORE_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_CORE_RESET_BITS 1 +#define MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: BIST_CTRL + ***************************************************************************/ +/* MISC3 :: BIST_CTRL :: MBIST_OVERRIDE [31:31] */ +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_MASK 0x80000000 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_BITS 1 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_SHIFT 31 + +/* MISC3 :: BIST_CTRL :: reserved0 [30:15] */ +#define MISC3_BIST_CTRL_reserved0_MASK 0x7fff8000 +#define MISC3_BIST_CTRL_reserved0_ALIGN 0 +#define MISC3_BIST_CTRL_reserved0_BITS 16 +#define MISC3_BIST_CTRL_reserved0_SHIFT 15 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_2 [14:14] */ +#define MISC3_BIST_CTRL_MBIST_EN_2_MASK 0x00004000 +#define MISC3_BIST_CTRL_MBIST_EN_2_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_2_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_2_SHIFT 14 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_1 [13:13] */ +#define MISC3_BIST_CTRL_MBIST_EN_1_MASK 0x00002000 +#define MISC3_BIST_CTRL_MBIST_EN_1_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_1_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_1_SHIFT 13 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_0 [12:12] */ +#define MISC3_BIST_CTRL_MBIST_EN_0_MASK 0x00001000 +#define MISC3_BIST_CTRL_MBIST_EN_0_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_0_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_0_SHIFT 12 + +/* MISC3 :: BIST_CTRL :: reserved1 [11:06] */ +#define MISC3_BIST_CTRL_reserved1_MASK 0x00000fc0 +#define MISC3_BIST_CTRL_reserved1_ALIGN 0 +#define MISC3_BIST_CTRL_reserved1_BITS 6 +#define MISC3_BIST_CTRL_reserved1_SHIFT 6 + +/* MISC3 :: BIST_CTRL :: MBIST_SETUP [05:04] */ +#define MISC3_BIST_CTRL_MBIST_SETUP_MASK 0x00000030 +#define MISC3_BIST_CTRL_MBIST_SETUP_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_SETUP_BITS 2 +#define MISC3_BIST_CTRL_MBIST_SETUP_SHIFT 4 + +/* MISC3 :: BIST_CTRL :: reserved2 [03:01] */ +#define MISC3_BIST_CTRL_reserved2_MASK 0x0000000e +#define MISC3_BIST_CTRL_reserved2_ALIGN 0 +#define MISC3_BIST_CTRL_reserved2_BITS 3 +#define MISC3_BIST_CTRL_reserved2_SHIFT 1 + +/* MISC3 :: BIST_CTRL :: MBIST_ASYNC_RESET [00:00] */ +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_MASK 0x00000001 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_BITS 1 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: BIST_STATUS + ***************************************************************************/ +/* MISC3 :: BIST_STATUS :: reserved0 [31:31] */ +#define MISC3_BIST_STATUS_reserved0_MASK 0x80000000 +#define MISC3_BIST_STATUS_reserved0_ALIGN 0 +#define MISC3_BIST_STATUS_reserved0_BITS 1 +#define MISC3_BIST_STATUS_reserved0_SHIFT 31 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_2 [30:30] */ +#define MISC3_BIST_STATUS_MBIST_GO_2_MASK 0x40000000 +#define MISC3_BIST_STATUS_MBIST_GO_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_2_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_2_SHIFT 30 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_1 [29:29] */ +#define MISC3_BIST_STATUS_MBIST_GO_1_MASK 0x20000000 +#define MISC3_BIST_STATUS_MBIST_GO_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_1_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_1_SHIFT 29 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_0 [28:28] */ +#define MISC3_BIST_STATUS_MBIST_GO_0_MASK 0x10000000 +#define MISC3_BIST_STATUS_MBIST_GO_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_0_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_0_SHIFT 28 + +/* MISC3 :: BIST_STATUS :: reserved1 [27:27] */ +#define MISC3_BIST_STATUS_reserved1_MASK 0x08000000 +#define MISC3_BIST_STATUS_reserved1_ALIGN 0 +#define MISC3_BIST_STATUS_reserved1_BITS 1 +#define MISC3_BIST_STATUS_reserved1_SHIFT 27 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_2 [26:26] */ +#define MISC3_BIST_STATUS_MBIST_DONE_2_MASK 0x04000000 +#define MISC3_BIST_STATUS_MBIST_DONE_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_2_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_2_SHIFT 26 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_1 [25:25] */ +#define MISC3_BIST_STATUS_MBIST_DONE_1_MASK 0x02000000 +#define MISC3_BIST_STATUS_MBIST_DONE_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_1_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_1_SHIFT 25 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_0 [24:24] */ +#define MISC3_BIST_STATUS_MBIST_DONE_0_MASK 0x01000000 +#define MISC3_BIST_STATUS_MBIST_DONE_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_0_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_0_SHIFT 24 + +/* MISC3 :: BIST_STATUS :: reserved2 [23:06] */ +#define MISC3_BIST_STATUS_reserved2_MASK 0x00ffffc0 +#define MISC3_BIST_STATUS_reserved2_ALIGN 0 +#define MISC3_BIST_STATUS_reserved2_BITS 18 +#define MISC3_BIST_STATUS_reserved2_SHIFT 6 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_2 [05:04] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_MASK 0x00000030 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_SHIFT 4 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_1 [03:02] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_MASK 0x0000000c +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_SHIFT 2 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_0 [01:00] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_MASK 0x00000003 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: RX_CHECKSUM + ***************************************************************************/ +/* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_ALIGN 0 +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_BITS 32 +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: TX_CHECKSUM + ***************************************************************************/ +/* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_ALIGN 0 +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_BITS 32 +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: ECO_CTRL_CORE + ***************************************************************************/ +/* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ +#define MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 +#define MISC3_ECO_CTRL_CORE_reserved0_ALIGN 0 +#define MISC3_ECO_CTRL_CORE_reserved0_BITS 16 +#define MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 + +/* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_ALIGN 0 +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_BITS 16 +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: CSI_TEST_CTRL + ***************************************************************************/ +/* MISC3 :: CSI_TEST_CTRL :: ENABLE_CSI_TEST [31:31] */ +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_MASK 0x80000000 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_BITS 1 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_SHIFT 31 + +/* MISC3 :: CSI_TEST_CTRL :: reserved0 [30:24] */ +#define MISC3_CSI_TEST_CTRL_reserved0_MASK 0x7f000000 +#define MISC3_CSI_TEST_CTRL_reserved0_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_reserved0_BITS 7 +#define MISC3_CSI_TEST_CTRL_reserved0_SHIFT 24 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_CLOCK_ENABLE [23:16] */ +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_MASK 0x00ff0000 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_SHIFT 16 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_SYNC [15:08] */ +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_MASK 0x0000ff00 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_SHIFT 8 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_DATA [07:00] */ +#define MISC3_CSI_TEST_CTRL_CSI_DATA_MASK 0x000000ff +#define MISC3_CSI_TEST_CTRL_CSI_DATA_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_DATA_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_DATA_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: HD_DVI_TEST_CTRL + ***************************************************************************/ +/* MISC3 :: HD_DVI_TEST_CTRL :: reserved0 [31:25] */ +#define MISC3_HD_DVI_TEST_CTRL_reserved0_MASK 0xfe000000 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_BITS 7 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_SHIFT 25 + +/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_VBLANK_N [24:24] */ +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_MASK 0x01000000 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_BITS 1 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_SHIFT 24 + +/* MISC3 :: HD_DVI_TEST_CTRL :: NEG_VIDO_DVI_DATA [23:12] */ +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_MASK 0x00fff000 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_BITS 12 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_SHIFT 12 + +/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_DVI_DATA [11:00] */ +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_MASK 0x00000fff +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_BITS 12 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_PERST + ***************************************************************************/ +/**************************************************************************** + * MISC_PERST :: ECO_CTRL_PERST + ***************************************************************************/ +/* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ +#define MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_ALIGN 0 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_BITS 16 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 + +/* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_ALIGN 0 +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_BITS 16 +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: DECODER_CTRL + ***************************************************************************/ +/* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ +#define MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 +#define MISC_PERST_DECODER_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_reserved0_BITS 27 +#define MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 + +/* MISC_PERST :: DECODER_CTRL :: STOP_BCM7412_CLK [04:04] */ +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_MASK 0x00000010 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_BITS 1 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_SHIFT 4 + +/* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ +#define MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e +#define MISC_PERST_DECODER_CTRL_reserved1_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_reserved1_BITS 3 +#define MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 + +/* MISC_PERST :: DECODER_CTRL :: BCM7412_RESET [00:00] */ +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_MASK 0x00000001 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_BITS 1 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: CCE_STATUS + ***************************************************************************/ +/* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ +#define MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 +#define MISC_PERST_CCE_STATUS_CCE_DONE_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_DONE_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 + +/* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ +#define MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 +#define MISC_PERST_CCE_STATUS_reserved0_ALIGN 0 +#define MISC_PERST_CCE_STATUS_reserved0_BITS 28 +#define MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: PCIE_DEBUG + ***************************************************************************/ +/* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_BITS 16 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 + +/* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:11] */ +#define MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000f800 +#define MISC_PERST_PCIE_DEBUG_reserved0_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_reserved0_BITS 5 +#define MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 11 + +/* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_BITS 1 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 + +/* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_BITS 1 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 + +/* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_BITS 1 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 + +/* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ +#define MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 +#define MISC_PERST_PCIE_DEBUG_reserved1_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_reserved1_BITS 4 +#define MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 + +/* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_BITS 4 +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: PCIE_DEBUG_STATUS + ***************************************************************************/ +/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:06] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xffffffc0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_BITS 26 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 6 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [03:02] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000000c +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_BITS 2 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 2 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: VREG_CTRL + ***************************************************************************/ +/* MISC_PERST :: VREG_CTRL :: reserved0 [31:08] */ +#define MISC_PERST_VREG_CTRL_reserved0_MASK 0xffffff00 +#define MISC_PERST_VREG_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_VREG_CTRL_reserved0_BITS 24 +#define MISC_PERST_VREG_CTRL_reserved0_SHIFT 8 + +/* MISC_PERST :: VREG_CTRL :: VREG1P2_SEL [07:04] */ +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_MASK 0x000000f0 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_ALIGN 0 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_BITS 4 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_SHIFT 4 + +/* MISC_PERST :: VREG_CTRL :: VREG2P5_SEL [03:00] */ +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_MASK 0x0000000f +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_ALIGN 0 +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_BITS 4 +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: MEM_CTRL + ***************************************************************************/ +/* MISC_PERST :: MEM_CTRL :: reserved0 [31:04] */ +#define MISC_PERST_MEM_CTRL_reserved0_MASK 0xfffffff0 +#define MISC_PERST_MEM_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_MEM_CTRL_reserved0_BITS 28 +#define MISC_PERST_MEM_CTRL_reserved0_SHIFT 4 + +/* MISC_PERST :: MEM_CTRL :: Y_RM [03:03] */ +#define MISC_PERST_MEM_CTRL_Y_RM_MASK 0x00000008 +#define MISC_PERST_MEM_CTRL_Y_RM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_Y_RM_BITS 1 +#define MISC_PERST_MEM_CTRL_Y_RM_SHIFT 3 + +/* MISC_PERST :: MEM_CTRL :: Y_CCM [02:02] */ +#define MISC_PERST_MEM_CTRL_Y_CCM_MASK 0x00000004 +#define MISC_PERST_MEM_CTRL_Y_CCM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_Y_CCM_BITS 1 +#define MISC_PERST_MEM_CTRL_Y_CCM_SHIFT 2 + +/* MISC_PERST :: MEM_CTRL :: UV_RM [01:01] */ +#define MISC_PERST_MEM_CTRL_UV_RM_MASK 0x00000002 +#define MISC_PERST_MEM_CTRL_UV_RM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_UV_RM_BITS 1 +#define MISC_PERST_MEM_CTRL_UV_RM_SHIFT 1 + +/* MISC_PERST :: MEM_CTRL :: UV_CCM [00:00] */ +#define MISC_PERST_MEM_CTRL_UV_CCM_MASK 0x00000001 +#define MISC_PERST_MEM_CTRL_UV_CCM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_UV_CCM_BITS 1 +#define MISC_PERST_MEM_CTRL_UV_CCM_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: CLOCK_CTRL + ***************************************************************************/ +/* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:20] */ +#define MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfff00000 +#define MISC_PERST_CLOCK_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_reserved0_BITS 12 +#define MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 20 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_DIV [19:16] */ +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_MASK 0x000f0000 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_BITS 4 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_SHIFT 16 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_MULT [15:08] */ +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_MASK 0x0000ff00 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_BITS 8 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_SHIFT 8 + +/* MISC_PERST :: CLOCK_CTRL :: reserved1 [07:03] */ +#define MISC_PERST_CLOCK_CTRL_reserved1_MASK 0x000000f8 +#define MISC_PERST_CLOCK_CTRL_reserved1_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_reserved1_BITS 5 +#define MISC_PERST_CLOCK_CTRL_reserved1_SHIFT 3 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_PWRDOWN [02:02] */ +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_MASK 0x00000004 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_BITS 1 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_SHIFT 2 + +/* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_BITS 1 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 + +/* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_BITS 1 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_GISB_ARBITER + ***************************************************************************/ +/**************************************************************************** + * GISB_ARBITER :: REVISION + ***************************************************************************/ +/* GISB_ARBITER :: REVISION :: reserved0 [31:16] */ +#define GISB_ARBITER_REVISION_reserved0_MASK 0xffff0000 +#define GISB_ARBITER_REVISION_reserved0_ALIGN 0 +#define GISB_ARBITER_REVISION_reserved0_BITS 16 +#define GISB_ARBITER_REVISION_reserved0_SHIFT 16 + +/* GISB_ARBITER :: REVISION :: MAJOR [15:08] */ +#define GISB_ARBITER_REVISION_MAJOR_MASK 0x0000ff00 +#define GISB_ARBITER_REVISION_MAJOR_ALIGN 0 +#define GISB_ARBITER_REVISION_MAJOR_BITS 8 +#define GISB_ARBITER_REVISION_MAJOR_SHIFT 8 + +/* GISB_ARBITER :: REVISION :: MINOR [07:00] */ +#define GISB_ARBITER_REVISION_MINOR_MASK 0x000000ff +#define GISB_ARBITER_REVISION_MINOR_ALIGN 0 +#define GISB_ARBITER_REVISION_MINOR_BITS 8 +#define GISB_ARBITER_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: SCRATCH + ***************************************************************************/ +/* GISB_ARBITER :: SCRATCH :: scratch_bit [31:00] */ +#define GISB_ARBITER_SCRATCH_scratch_bit_MASK 0xffffffff +#define GISB_ARBITER_SCRATCH_scratch_bit_ALIGN 0 +#define GISB_ARBITER_SCRATCH_scratch_bit_BITS 32 +#define GISB_ARBITER_SCRATCH_scratch_bit_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: REQ_MASK + ***************************************************************************/ +/* GISB_ARBITER :: REQ_MASK :: reserved0 [31:06] */ +#define GISB_ARBITER_REQ_MASK_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_REQ_MASK_reserved0_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_reserved0_BITS 26 +#define GISB_ARBITER_REQ_MASK_reserved0_SHIFT 6 + +/* GISB_ARBITER :: REQ_MASK :: bsp [05:05] */ +#define GISB_ARBITER_REQ_MASK_bsp_MASK 0x00000020 +#define GISB_ARBITER_REQ_MASK_bsp_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_bsp_BITS 1 +#define GISB_ARBITER_REQ_MASK_bsp_SHIFT 5 +#define GISB_ARBITER_REQ_MASK_bsp_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: tgt [04:04] */ +#define GISB_ARBITER_REQ_MASK_tgt_MASK 0x00000010 +#define GISB_ARBITER_REQ_MASK_tgt_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_tgt_BITS 1 +#define GISB_ARBITER_REQ_MASK_tgt_SHIFT 4 +#define GISB_ARBITER_REQ_MASK_tgt_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: aes [03:03] */ +#define GISB_ARBITER_REQ_MASK_aes_MASK 0x00000008 +#define GISB_ARBITER_REQ_MASK_aes_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_aes_BITS 1 +#define GISB_ARBITER_REQ_MASK_aes_SHIFT 3 +#define GISB_ARBITER_REQ_MASK_aes_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: dci [02:02] */ +#define GISB_ARBITER_REQ_MASK_dci_MASK 0x00000004 +#define GISB_ARBITER_REQ_MASK_dci_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_dci_BITS 1 +#define GISB_ARBITER_REQ_MASK_dci_SHIFT 2 +#define GISB_ARBITER_REQ_MASK_dci_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: cce [01:01] */ +#define GISB_ARBITER_REQ_MASK_cce_MASK 0x00000002 +#define GISB_ARBITER_REQ_MASK_cce_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_cce_BITS 1 +#define GISB_ARBITER_REQ_MASK_cce_SHIFT 1 +#define GISB_ARBITER_REQ_MASK_cce_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: dbu [00:00] */ +#define GISB_ARBITER_REQ_MASK_dbu_MASK 0x00000001 +#define GISB_ARBITER_REQ_MASK_dbu_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_dbu_BITS 1 +#define GISB_ARBITER_REQ_MASK_dbu_SHIFT 0 +#define GISB_ARBITER_REQ_MASK_dbu_UNMASK 0 + + +/**************************************************************************** + * GISB_ARBITER :: TIMER + ***************************************************************************/ +/* GISB_ARBITER :: TIMER :: hi_count [31:16] */ +#define GISB_ARBITER_TIMER_hi_count_MASK 0xffff0000 +#define GISB_ARBITER_TIMER_hi_count_ALIGN 0 +#define GISB_ARBITER_TIMER_hi_count_BITS 16 +#define GISB_ARBITER_TIMER_hi_count_SHIFT 16 + +/* GISB_ARBITER :: TIMER :: lo_count [15:00] */ +#define GISB_ARBITER_TIMER_lo_count_MASK 0x0000ffff +#define GISB_ARBITER_TIMER_lo_count_ALIGN 0 +#define GISB_ARBITER_TIMER_lo_count_BITS 16 +#define GISB_ARBITER_TIMER_lo_count_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CTRL + ***************************************************************************/ +/* GISB_ARBITER :: BP_CTRL :: reserved0 [31:02] */ +#define GISB_ARBITER_BP_CTRL_reserved0_MASK 0xfffffffc +#define GISB_ARBITER_BP_CTRL_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_reserved0_BITS 30 +#define GISB_ARBITER_BP_CTRL_reserved0_SHIFT 2 + +/* GISB_ARBITER :: BP_CTRL :: breakpoint_tea [01:01] */ +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_MASK 0x00000002 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_BITS 1 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_SHIFT 1 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_DISABLE 0 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ENABLE 1 + +/* GISB_ARBITER :: BP_CTRL :: repeat_capture [00:00] */ +#define GISB_ARBITER_BP_CTRL_repeat_capture_MASK 0x00000001 +#define GISB_ARBITER_BP_CTRL_repeat_capture_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_BITS 1 +#define GISB_ARBITER_BP_CTRL_repeat_capture_SHIFT 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_DISABLE 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_CLR + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_CLR :: reserved0 [31:01] */ +#define GISB_ARBITER_BP_CAP_CLR_reserved0_MASK 0xfffffffe +#define GISB_ARBITER_BP_CAP_CLR_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_CLR_reserved0_BITS 31 +#define GISB_ARBITER_BP_CAP_CLR_reserved0_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_CLR :: clear [00:00] */ +#define GISB_ARBITER_BP_CAP_CLR_clear_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_CLR_clear_ALIGN 0 +#define GISB_ARBITER_BP_CAP_CLR_clear_BITS 1 +#define GISB_ARBITER_BP_CAP_CLR_clear_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_0 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_0_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_0_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_0_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_0_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_0 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_0_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_0_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_0_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_0_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_0 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_0_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_0_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_0 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_0_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_0_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_0_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_0_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_0_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_0_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_aes_BITS 1 +#define GISB_ARBITER_BP_READ_0_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_0_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_0_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_0_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_fve_BITS 1 +#define GISB_ARBITER_BP_READ_0_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_0_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_0_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_0_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_0_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_0_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_0_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_0_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_0_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_0_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_0_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_0_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_cce_BITS 1 +#define GISB_ARBITER_BP_READ_0_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_0_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_0 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_0_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_0_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_0 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_0_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_0_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_0_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_0_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_0_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_0_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_0_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_0_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_0_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_0_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_0_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_0_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_0_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_0_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_0_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_0_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_0_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_0_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_0 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_0_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_0 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_0_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_0_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_0_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_0 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_0_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_0_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_0_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_0 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_0_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_0_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_0_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_1 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_1_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_1_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_1_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_1_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_1 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_1_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_1_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_1_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_1_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_1 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_1_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_1_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_1 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_1_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_1_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_1_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_1_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_1_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_1_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_aes_BITS 1 +#define GISB_ARBITER_BP_READ_1_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_1_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_1_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_1_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_fve_BITS 1 +#define GISB_ARBITER_BP_READ_1_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_1_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_1_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_1_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_1_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_1_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_1_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_1_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_1_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_1_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_1_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_1_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_cce_BITS 1 +#define GISB_ARBITER_BP_READ_1_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_1_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_1 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_1_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_1_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_1 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_1_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_1_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_1_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_1_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_1_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_1_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_1_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_1_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_1_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_1_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_1_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_1_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_1_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_1_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_1_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_1_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_1_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_1_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_1 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_1_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_1 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_1_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_1_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_1_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_1 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_1_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_1_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_1_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_1 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_1_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_1_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_1_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_2 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_2_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_2_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_2_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_2_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_2 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_2_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_2_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_2_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_2_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_2 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_2_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_2_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_2 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_2_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_2_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_2_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_2_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_2_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_2_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_aes_BITS 1 +#define GISB_ARBITER_BP_READ_2_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_2_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_2_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_2_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_fve_BITS 1 +#define GISB_ARBITER_BP_READ_2_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_2_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_2_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_2_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_2_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_2_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_2_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_2_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_2_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_2_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_2_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_2_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_cce_BITS 1 +#define GISB_ARBITER_BP_READ_2_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_2_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_2 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_2_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_2_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_2 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_2_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_2_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_2_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_2_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_2_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_2_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_2_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_2_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_2_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_2_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_2_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_2_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_2_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_2_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_2_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_2_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_2_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_2_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_2 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_2_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_2 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_2_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_2_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_2_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_2 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_2_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_2_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_2_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_2 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_2_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_2_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_2_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_3 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_3_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_3_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_3_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_3_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_3 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_3_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_3_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_3_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_3_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_3 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_3_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_3_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_3 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_3_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_3_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_3_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_3_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_3_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_3_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_aes_BITS 1 +#define GISB_ARBITER_BP_READ_3_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_3_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_3_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_3_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_fve_BITS 1 +#define GISB_ARBITER_BP_READ_3_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_3_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_3_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_3_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_3_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_3_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_3_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_3_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_3_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_3_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_3_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_3_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_cce_BITS 1 +#define GISB_ARBITER_BP_READ_3_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_3_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_3 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_3_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_3_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_3 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_3_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_3_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_3_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_3_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_3_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_3_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_3_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_3_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_3_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_3_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_3_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_3_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_3_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_3_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_3_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_3_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_3_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_3_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_3 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_3_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_3 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_3_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_3_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_3_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_3 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_3_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_3_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_3_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_3 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_3_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_3_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_3_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_4 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_4_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_4_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_4_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_4_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_4 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_4_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_4_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_4_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_4_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_4 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_4_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_4_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_4 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_4_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_4_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_4_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_4_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_4_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_4_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_aes_BITS 1 +#define GISB_ARBITER_BP_READ_4_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_4_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_4_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_4_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_fve_BITS 1 +#define GISB_ARBITER_BP_READ_4_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_4_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_4_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_4_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_4_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_4_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_4_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_4_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_4_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_4_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_4_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_4_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_cce_BITS 1 +#define GISB_ARBITER_BP_READ_4_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_4_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_4 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_4_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_4_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_4 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_4_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_4_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_4_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_4_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_4_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_4_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_4_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_4_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_4_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_4_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_4_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_4_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_4_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_4_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_4_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_4_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_4_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_4_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_4 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_4_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_4 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_4_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_4_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_4_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_4 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_4_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_4_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_4_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_4 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_4_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_4_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_4_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_5 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_5_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_5_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_5_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_5_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_5 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_5_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_5_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_5_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_5_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_5 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_5_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_5_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_5 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_5_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_5_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_5_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_5_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_5_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_5_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_aes_BITS 1 +#define GISB_ARBITER_BP_READ_5_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_5_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_5_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_5_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_fve_BITS 1 +#define GISB_ARBITER_BP_READ_5_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_5_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_5_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_5_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_5_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_5_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_5_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_5_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_5_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_5_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_5_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_5_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_cce_BITS 1 +#define GISB_ARBITER_BP_READ_5_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_5_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_5 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_5_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_5_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_5 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_5_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_5_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_5_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_5_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_5_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_5_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_5_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_5_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_5_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_5_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_5_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_5_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_5_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_5_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_5_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_5_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_5_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_5_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_5 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_5_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_5 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_5_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_5_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_5_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_5 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_5_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_5_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_5_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_5 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_5_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_5_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_5_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_6 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_6_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_6_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_6_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_6_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_6 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_6_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_6_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_6_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_6_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_6 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_6_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_6_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_6 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_6_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_6_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_6_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_6_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_6_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_6_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_aes_BITS 1 +#define GISB_ARBITER_BP_READ_6_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_6_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_6_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_6_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_fve_BITS 1 +#define GISB_ARBITER_BP_READ_6_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_6_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_6_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_6_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_6_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_6_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_6_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_6_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_6_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_6_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_6_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_6_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_cce_BITS 1 +#define GISB_ARBITER_BP_READ_6_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_6_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_6 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_6_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_6_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_6 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_6_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_6_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_6_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_6_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_6_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_6_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_6_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_6_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_6_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_6_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_6_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_6_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_6_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_6_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_6_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_6_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_6_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_6_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_6 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_6_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_6 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_6_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_6_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_6_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_6 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_6_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_6_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_6_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_6 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_6_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_6_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_6_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_7 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_7_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_7_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_7_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_7_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_7 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_7_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_7_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_7_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_7_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_7 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_7_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_7_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_7 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_7_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_7_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_7_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_7_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_7_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_7_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_aes_BITS 1 +#define GISB_ARBITER_BP_READ_7_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_7_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_7_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_7_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_fve_BITS 1 +#define GISB_ARBITER_BP_READ_7_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_7_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_7_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_7_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_7_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_7_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_7_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_7_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_7_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_7_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_7_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_7_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_cce_BITS 1 +#define GISB_ARBITER_BP_READ_7_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_7_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_7 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_7_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_7_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_7 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_7_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_7_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_7_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_7_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_7_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_7_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_7_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_7_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_7_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_7_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_7_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_7_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_7_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_7_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_7_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_7_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_7_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_7_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_7 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_7_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_7 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_7_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_7_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_7_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_7 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_7_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_7_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_7_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_7 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_7_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_7_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_7_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_ADDR + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_ADDR :: address [31:00] */ +#define GISB_ARBITER_BP_CAP_ADDR_address_MASK 0xffffffff +#define GISB_ARBITER_BP_CAP_ADDR_address_ALIGN 0 +#define GISB_ARBITER_BP_CAP_ADDR_address_BITS 32 +#define GISB_ARBITER_BP_CAP_ADDR_address_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_DATA + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_DATA :: data [31:00] */ +#define GISB_ARBITER_BP_CAP_DATA_data_MASK 0xffffffff +#define GISB_ARBITER_BP_CAP_DATA_data_ALIGN 0 +#define GISB_ARBITER_BP_CAP_DATA_data_BITS 32 +#define GISB_ARBITER_BP_CAP_DATA_data_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_STATUS + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_STATUS :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_BITS 26 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_CAP_STATUS :: bs_b [05:02] */ +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_MASK 0x0000003c +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_BITS 4 +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_SHIFT 2 + +/* GISB_ARBITER :: BP_CAP_STATUS :: write [01:01] */ +#define GISB_ARBITER_BP_CAP_STATUS_write_MASK 0x00000002 +#define GISB_ARBITER_BP_CAP_STATUS_write_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_write_BITS 1 +#define GISB_ARBITER_BP_CAP_STATUS_write_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_STATUS :: valid [00:00] */ +#define GISB_ARBITER_BP_CAP_STATUS_valid_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_STATUS_valid_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_valid_BITS 1 +#define GISB_ARBITER_BP_CAP_STATUS_valid_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_MASTER + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_MASTER :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_BITS 26 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_CAP_MASTER :: bsp [05:05] */ +#define GISB_ARBITER_BP_CAP_MASTER_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_SHIFT 5 + +/* GISB_ARBITER :: BP_CAP_MASTER :: aes [04:04] */ +#define GISB_ARBITER_BP_CAP_MASTER_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_CAP_MASTER_aes_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_aes_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_aes_SHIFT 4 + +/* GISB_ARBITER :: BP_CAP_MASTER :: fve [03:03] */ +#define GISB_ARBITER_BP_CAP_MASTER_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_CAP_MASTER_fve_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_fve_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_fve_SHIFT 3 + +/* GISB_ARBITER :: BP_CAP_MASTER :: tgt [02:02] */ +#define GISB_ARBITER_BP_CAP_MASTER_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_SHIFT 2 + +/* GISB_ARBITER :: BP_CAP_MASTER :: dbu [01:01] */ +#define GISB_ARBITER_BP_CAP_MASTER_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_MASTER :: cce [00:00] */ +#define GISB_ARBITER_BP_CAP_MASTER_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_MASTER_cce_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_cce_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_cce_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_CLR + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_CLR :: reserved0 [31:01] */ +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_MASK 0xfffffffe +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_BITS 31 +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_CLR :: clear [00:00] */ +#define GISB_ARBITER_ERR_CAP_CLR_clear_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_CLR_clear_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_CLR_clear_BITS 1 +#define GISB_ARBITER_ERR_CAP_CLR_clear_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_ADDR + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_ADDR :: address [31:00] */ +#define GISB_ARBITER_ERR_CAP_ADDR_address_MASK 0xffffffff +#define GISB_ARBITER_ERR_CAP_ADDR_address_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_ADDR_address_BITS 32 +#define GISB_ARBITER_ERR_CAP_ADDR_address_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_DATA + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_DATA :: data [31:00] */ +#define GISB_ARBITER_ERR_CAP_DATA_data_MASK 0xffffffff +#define GISB_ARBITER_ERR_CAP_DATA_data_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_DATA_data_BITS 32 +#define GISB_ARBITER_ERR_CAP_DATA_data_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_STATUS + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved0 [31:13] */ +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_BITS 19 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_SHIFT 13 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: timeout [12:12] */ +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_MASK 0x00001000 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_SHIFT 12 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: tea [11:11] */ +#define GISB_ARBITER_ERR_CAP_STATUS_tea_MASK 0x00000800 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_SHIFT 11 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved1 [10:06] */ +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_BITS 5 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_SHIFT 6 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: bs_b [05:02] */ +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_MASK 0x0000003c +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_BITS 4 +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_SHIFT 2 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: write [01:01] */ +#define GISB_ARBITER_ERR_CAP_STATUS_write_MASK 0x00000002 +#define GISB_ARBITER_ERR_CAP_STATUS_write_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_write_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_write_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: valid [00:00] */ +#define GISB_ARBITER_ERR_CAP_STATUS_valid_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_MASTER + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_MASTER :: reserved0 [31:06] */ +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_BITS 26 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_SHIFT 6 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: bsp [05:05] */ +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_MASK 0x00000020 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_SHIFT 5 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: aes [04:04] */ +#define GISB_ARBITER_ERR_CAP_MASTER_aes_MASK 0x00000010 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_SHIFT 4 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: fve [03:03] */ +#define GISB_ARBITER_ERR_CAP_MASTER_fve_MASK 0x00000008 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_SHIFT 3 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: tgt [02:02] */ +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_MASK 0x00000004 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_SHIFT 2 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: dbu [01:01] */ +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_MASK 0x00000002 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: cce [00:00] */ +#define GISB_ARBITER_ERR_CAP_MASTER_cce_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * MISC_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define MISC_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define MISC_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define MISC_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU + ***************************************************************************/ +/**************************************************************************** + * DBU :: DBU_CMD + ***************************************************************************/ +/* DBU :: DBU_CMD :: reserved0 [31:03] */ +#define DBU_DBU_CMD_reserved0_MASK 0xfffffff8 +#define DBU_DBU_CMD_reserved0_ALIGN 0 +#define DBU_DBU_CMD_reserved0_BITS 29 +#define DBU_DBU_CMD_reserved0_SHIFT 3 + +/* DBU :: DBU_CMD :: RX_OVERFLOW [02:02] */ +#define DBU_DBU_CMD_RX_OVERFLOW_MASK 0x00000004 +#define DBU_DBU_CMD_RX_OVERFLOW_ALIGN 0 +#define DBU_DBU_CMD_RX_OVERFLOW_BITS 1 +#define DBU_DBU_CMD_RX_OVERFLOW_SHIFT 2 + +/* DBU :: DBU_CMD :: RX_ERROR [01:01] */ +#define DBU_DBU_CMD_RX_ERROR_MASK 0x00000002 +#define DBU_DBU_CMD_RX_ERROR_ALIGN 0 +#define DBU_DBU_CMD_RX_ERROR_BITS 1 +#define DBU_DBU_CMD_RX_ERROR_SHIFT 1 + +/* DBU :: DBU_CMD :: ENABLE [00:00] */ +#define DBU_DBU_CMD_ENABLE_MASK 0x00000001 +#define DBU_DBU_CMD_ENABLE_ALIGN 0 +#define DBU_DBU_CMD_ENABLE_BITS 1 +#define DBU_DBU_CMD_ENABLE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_STATUS + ***************************************************************************/ +/* DBU :: DBU_STATUS :: reserved0 [31:02] */ +#define DBU_DBU_STATUS_reserved0_MASK 0xfffffffc +#define DBU_DBU_STATUS_reserved0_ALIGN 0 +#define DBU_DBU_STATUS_reserved0_BITS 30 +#define DBU_DBU_STATUS_reserved0_SHIFT 2 + +/* DBU :: DBU_STATUS :: TXDATA_OCCUPIED [01:01] */ +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_MASK 0x00000002 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_ALIGN 0 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_BITS 1 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_SHIFT 1 + +/* DBU :: DBU_STATUS :: RXDATA_VALID [00:00] */ +#define DBU_DBU_STATUS_RXDATA_VALID_MASK 0x00000001 +#define DBU_DBU_STATUS_RXDATA_VALID_ALIGN 0 +#define DBU_DBU_STATUS_RXDATA_VALID_BITS 1 +#define DBU_DBU_STATUS_RXDATA_VALID_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_CONFIG + ***************************************************************************/ +/* DBU :: DBU_CONFIG :: reserved0 [31:03] */ +#define DBU_DBU_CONFIG_reserved0_MASK 0xfffffff8 +#define DBU_DBU_CONFIG_reserved0_ALIGN 0 +#define DBU_DBU_CONFIG_reserved0_BITS 29 +#define DBU_DBU_CONFIG_reserved0_SHIFT 3 + +/* DBU :: DBU_CONFIG :: CRLF_ENABLE [02:02] */ +#define DBU_DBU_CONFIG_CRLF_ENABLE_MASK 0x00000004 +#define DBU_DBU_CONFIG_CRLF_ENABLE_ALIGN 0 +#define DBU_DBU_CONFIG_CRLF_ENABLE_BITS 1 +#define DBU_DBU_CONFIG_CRLF_ENABLE_SHIFT 2 + +/* DBU :: DBU_CONFIG :: DEBUGSM_ENABLE [01:01] */ +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_MASK 0x00000002 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_ALIGN 0 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_BITS 1 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_SHIFT 1 + +/* DBU :: DBU_CONFIG :: TIMING_OVERRIDE [00:00] */ +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_MASK 0x00000001 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_ALIGN 0 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_BITS 1 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_TIMING + ***************************************************************************/ +/* DBU :: DBU_TIMING :: BIT_INTERVAL [31:16] */ +#define DBU_DBU_TIMING_BIT_INTERVAL_MASK 0xffff0000 +#define DBU_DBU_TIMING_BIT_INTERVAL_ALIGN 0 +#define DBU_DBU_TIMING_BIT_INTERVAL_BITS 16 +#define DBU_DBU_TIMING_BIT_INTERVAL_SHIFT 16 + +/* DBU :: DBU_TIMING :: FB_SMPL_OFFSET [15:00] */ +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_MASK 0x0000ffff +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_ALIGN 0 +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_BITS 16 +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_RXDATA + ***************************************************************************/ +/* DBU :: DBU_RXDATA :: reserved0 [31:09] */ +#define DBU_DBU_RXDATA_reserved0_MASK 0xfffffe00 +#define DBU_DBU_RXDATA_reserved0_ALIGN 0 +#define DBU_DBU_RXDATA_reserved0_BITS 23 +#define DBU_DBU_RXDATA_reserved0_SHIFT 9 + +/* DBU :: DBU_RXDATA :: ERROR [08:08] */ +#define DBU_DBU_RXDATA_ERROR_MASK 0x00000100 +#define DBU_DBU_RXDATA_ERROR_ALIGN 0 +#define DBU_DBU_RXDATA_ERROR_BITS 1 +#define DBU_DBU_RXDATA_ERROR_SHIFT 8 + +/* DBU :: DBU_RXDATA :: VALUE [07:00] */ +#define DBU_DBU_RXDATA_VALUE_MASK 0x000000ff +#define DBU_DBU_RXDATA_VALUE_ALIGN 0 +#define DBU_DBU_RXDATA_VALUE_BITS 8 +#define DBU_DBU_RXDATA_VALUE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_TXDATA + ***************************************************************************/ +/* DBU :: DBU_TXDATA :: reserved0 [31:08] */ +#define DBU_DBU_TXDATA_reserved0_MASK 0xffffff00 +#define DBU_DBU_TXDATA_reserved0_ALIGN 0 +#define DBU_DBU_TXDATA_reserved0_BITS 24 +#define DBU_DBU_TXDATA_reserved0_SHIFT 8 + +/* DBU :: DBU_TXDATA :: VALUE [07:00] */ +#define DBU_DBU_TXDATA_VALUE_MASK 0x000000ff +#define DBU_DBU_TXDATA_VALUE_ALIGN 0 +#define DBU_DBU_TXDATA_VALUE_BITS 8 +#define DBU_DBU_TXDATA_VALUE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * DBU_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define DBU_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define DBU_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define DBU_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* DBU_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define DBU_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* DBU_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define DBU_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define DBU_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define DBU_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define DBU_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define DBU_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define DBU_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* DBU_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* DBU_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* DBU_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP + ***************************************************************************/ +/**************************************************************************** + * OTP :: CONFIG_INFO + ***************************************************************************/ +/* OTP :: CONFIG_INFO :: reserved0 [31:22] */ +#define OTP_CONFIG_INFO_reserved0_MASK 0xffc00000 +#define OTP_CONFIG_INFO_reserved0_ALIGN 0 +#define OTP_CONFIG_INFO_reserved0_BITS 10 +#define OTP_CONFIG_INFO_reserved0_SHIFT 22 + +/* OTP :: CONFIG_INFO :: SELVL [21:20] */ +#define OTP_CONFIG_INFO_SELVL_MASK 0x00300000 +#define OTP_CONFIG_INFO_SELVL_ALIGN 0 +#define OTP_CONFIG_INFO_SELVL_BITS 2 +#define OTP_CONFIG_INFO_SELVL_SHIFT 20 + +/* OTP :: CONFIG_INFO :: reserved1 [19:17] */ +#define OTP_CONFIG_INFO_reserved1_MASK 0x000e0000 +#define OTP_CONFIG_INFO_reserved1_ALIGN 0 +#define OTP_CONFIG_INFO_reserved1_BITS 3 +#define OTP_CONFIG_INFO_reserved1_SHIFT 17 + +/* OTP :: CONFIG_INFO :: PTEST [16:16] */ +#define OTP_CONFIG_INFO_PTEST_MASK 0x00010000 +#define OTP_CONFIG_INFO_PTEST_ALIGN 0 +#define OTP_CONFIG_INFO_PTEST_BITS 1 +#define OTP_CONFIG_INFO_PTEST_SHIFT 16 + +/* OTP :: CONFIG_INFO :: reserved2 [15:13] */ +#define OTP_CONFIG_INFO_reserved2_MASK 0x0000e000 +#define OTP_CONFIG_INFO_reserved2_ALIGN 0 +#define OTP_CONFIG_INFO_reserved2_BITS 3 +#define OTP_CONFIG_INFO_reserved2_SHIFT 13 + +/* OTP :: CONFIG_INFO :: MAX_REDUNDANT_ROWS [12:08] */ +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_MASK 0x00001f00 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_ALIGN 0 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_BITS 5 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_SHIFT 8 + +/* OTP :: CONFIG_INFO :: MAX_RETRY [07:04] */ +#define OTP_CONFIG_INFO_MAX_RETRY_MASK 0x000000f0 +#define OTP_CONFIG_INFO_MAX_RETRY_ALIGN 0 +#define OTP_CONFIG_INFO_MAX_RETRY_BITS 4 +#define OTP_CONFIG_INFO_MAX_RETRY_SHIFT 4 + +/* OTP :: CONFIG_INFO :: reserved3 [03:01] */ +#define OTP_CONFIG_INFO_reserved3_MASK 0x0000000e +#define OTP_CONFIG_INFO_reserved3_ALIGN 0 +#define OTP_CONFIG_INFO_reserved3_BITS 3 +#define OTP_CONFIG_INFO_reserved3_SHIFT 1 + +/* OTP :: CONFIG_INFO :: PROG_MODE [00:00] */ +#define OTP_CONFIG_INFO_PROG_MODE_MASK 0x00000001 +#define OTP_CONFIG_INFO_PROG_MODE_ALIGN 0 +#define OTP_CONFIG_INFO_PROG_MODE_BITS 1 +#define OTP_CONFIG_INFO_PROG_MODE_SHIFT 0 + + +/**************************************************************************** + * OTP :: CMD + ***************************************************************************/ +/* OTP :: CMD :: reserved0 [31:02] */ +#define OTP_CMD_reserved0_MASK 0xfffffffc +#define OTP_CMD_reserved0_ALIGN 0 +#define OTP_CMD_reserved0_BITS 30 +#define OTP_CMD_reserved0_SHIFT 2 + +/* OTP :: CMD :: KEYS_AVAIL [01:01] */ +#define OTP_CMD_KEYS_AVAIL_MASK 0x00000002 +#define OTP_CMD_KEYS_AVAIL_ALIGN 0 +#define OTP_CMD_KEYS_AVAIL_BITS 1 +#define OTP_CMD_KEYS_AVAIL_SHIFT 1 + +/* OTP :: CMD :: PROGRAM_OTP [00:00] */ +#define OTP_CMD_PROGRAM_OTP_MASK 0x00000001 +#define OTP_CMD_PROGRAM_OTP_ALIGN 0 +#define OTP_CMD_PROGRAM_OTP_BITS 1 +#define OTP_CMD_PROGRAM_OTP_SHIFT 0 + + +/**************************************************************************** + * OTP :: STATUS + ***************************************************************************/ +/* OTP :: STATUS :: reserved0 [31:30] */ +#define OTP_STATUS_reserved0_MASK 0xc0000000 +#define OTP_STATUS_reserved0_ALIGN 0 +#define OTP_STATUS_reserved0_BITS 2 +#define OTP_STATUS_reserved0_SHIFT 30 + +/* OTP :: STATUS :: TOTAL_RETRIES [29:17] */ +#define OTP_STATUS_TOTAL_RETRIES_MASK 0x3ffe0000 +#define OTP_STATUS_TOTAL_RETRIES_ALIGN 0 +#define OTP_STATUS_TOTAL_RETRIES_BITS 13 +#define OTP_STATUS_TOTAL_RETRIES_SHIFT 17 + +/* OTP :: STATUS :: ROWS_USED [16:12] */ +#define OTP_STATUS_ROWS_USED_MASK 0x0001f000 +#define OTP_STATUS_ROWS_USED_ALIGN 0 +#define OTP_STATUS_ROWS_USED_BITS 5 +#define OTP_STATUS_ROWS_USED_SHIFT 12 + +/* OTP :: STATUS :: MAX_RETRIES [11:08] */ +#define OTP_STATUS_MAX_RETRIES_MASK 0x00000f00 +#define OTP_STATUS_MAX_RETRIES_ALIGN 0 +#define OTP_STATUS_MAX_RETRIES_BITS 4 +#define OTP_STATUS_MAX_RETRIES_SHIFT 8 + +/* OTP :: STATUS :: PROG_STATUS [07:04] */ +#define OTP_STATUS_PROG_STATUS_MASK 0x000000f0 +#define OTP_STATUS_PROG_STATUS_ALIGN 0 +#define OTP_STATUS_PROG_STATUS_BITS 4 +#define OTP_STATUS_PROG_STATUS_SHIFT 4 + +/* OTP :: STATUS :: reserved1 [03:03] */ +#define OTP_STATUS_reserved1_MASK 0x00000008 +#define OTP_STATUS_reserved1_ALIGN 0 +#define OTP_STATUS_reserved1_BITS 1 +#define OTP_STATUS_reserved1_SHIFT 3 + +/* OTP :: STATUS :: CHECKSUM_MISMATCH [02:02] */ +#define OTP_STATUS_CHECKSUM_MISMATCH_MASK 0x00000004 +#define OTP_STATUS_CHECKSUM_MISMATCH_ALIGN 0 +#define OTP_STATUS_CHECKSUM_MISMATCH_BITS 1 +#define OTP_STATUS_CHECKSUM_MISMATCH_SHIFT 2 + +/* OTP :: STATUS :: INSUFFICIENT_ROWS [01:01] */ +#define OTP_STATUS_INSUFFICIENT_ROWS_MASK 0x00000002 +#define OTP_STATUS_INSUFFICIENT_ROWS_ALIGN 0 +#define OTP_STATUS_INSUFFICIENT_ROWS_BITS 1 +#define OTP_STATUS_INSUFFICIENT_ROWS_SHIFT 1 + +/* OTP :: STATUS :: PROGRAMMED [00:00] */ +#define OTP_STATUS_PROGRAMMED_MASK 0x00000001 +#define OTP_STATUS_PROGRAMMED_ALIGN 0 +#define OTP_STATUS_PROGRAMMED_BITS 1 +#define OTP_STATUS_PROGRAMMED_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_MISC + ***************************************************************************/ +/* OTP :: CONTENT_MISC :: reserved0 [31:06] */ +#define OTP_CONTENT_MISC_reserved0_MASK 0xffffffc0 +#define OTP_CONTENT_MISC_reserved0_ALIGN 0 +#define OTP_CONTENT_MISC_reserved0_BITS 26 +#define OTP_CONTENT_MISC_reserved0_SHIFT 6 + +/* OTP :: CONTENT_MISC :: DCI_SECURITY_ENABLE [05:05] */ +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_MASK 0x00000020 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_SHIFT 5 + +/* OTP :: CONTENT_MISC :: AES_SECURITY_ENABLE [04:04] */ +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_MASK 0x00000010 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_SHIFT 4 + +/* OTP :: CONTENT_MISC :: DISABLE_JTAG [03:03] */ +#define OTP_CONTENT_MISC_DISABLE_JTAG_MASK 0x00000008 +#define OTP_CONTENT_MISC_DISABLE_JTAG_ALIGN 0 +#define OTP_CONTENT_MISC_DISABLE_JTAG_BITS 1 +#define OTP_CONTENT_MISC_DISABLE_JTAG_SHIFT 3 + +/* OTP :: CONTENT_MISC :: DISABLE_UART [02:02] */ +#define OTP_CONTENT_MISC_DISABLE_UART_MASK 0x00000004 +#define OTP_CONTENT_MISC_DISABLE_UART_ALIGN 0 +#define OTP_CONTENT_MISC_DISABLE_UART_BITS 1 +#define OTP_CONTENT_MISC_DISABLE_UART_SHIFT 2 + +/* OTP :: CONTENT_MISC :: ENABLE_RANDOMIZATION [01:01] */ +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_MASK 0x00000002 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_ALIGN 0 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_BITS 1 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_SHIFT 1 + +/* OTP :: CONTENT_MISC :: OTP_SECURITY_ENABLE [00:00] */ +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_MASK 0x00000001 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_0 + ***************************************************************************/ +/* OTP :: CONTENT_AES_0 :: AES_KEY_0 [31:00] */ +#define OTP_CONTENT_AES_0_AES_KEY_0_MASK 0xffffffff +#define OTP_CONTENT_AES_0_AES_KEY_0_ALIGN 0 +#define OTP_CONTENT_AES_0_AES_KEY_0_BITS 32 +#define OTP_CONTENT_AES_0_AES_KEY_0_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_1 + ***************************************************************************/ +/* OTP :: CONTENT_AES_1 :: AES_KEY_1 [31:00] */ +#define OTP_CONTENT_AES_1_AES_KEY_1_MASK 0xffffffff +#define OTP_CONTENT_AES_1_AES_KEY_1_ALIGN 0 +#define OTP_CONTENT_AES_1_AES_KEY_1_BITS 32 +#define OTP_CONTENT_AES_1_AES_KEY_1_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_2 + ***************************************************************************/ +/* OTP :: CONTENT_AES_2 :: AES_KEY_2 [31:00] */ +#define OTP_CONTENT_AES_2_AES_KEY_2_MASK 0xffffffff +#define OTP_CONTENT_AES_2_AES_KEY_2_ALIGN 0 +#define OTP_CONTENT_AES_2_AES_KEY_2_BITS 32 +#define OTP_CONTENT_AES_2_AES_KEY_2_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_3 + ***************************************************************************/ +/* OTP :: CONTENT_AES_3 :: AES_KEY_3 [31:00] */ +#define OTP_CONTENT_AES_3_AES_KEY_3_MASK 0xffffffff +#define OTP_CONTENT_AES_3_AES_KEY_3_ALIGN 0 +#define OTP_CONTENT_AES_3_AES_KEY_3_BITS 32 +#define OTP_CONTENT_AES_3_AES_KEY_3_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_0 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_0 :: SHA_KEY_0 [31:00] */ +#define OTP_CONTENT_SHA_0_SHA_KEY_0_MASK 0xffffffff +#define OTP_CONTENT_SHA_0_SHA_KEY_0_ALIGN 0 +#define OTP_CONTENT_SHA_0_SHA_KEY_0_BITS 32 +#define OTP_CONTENT_SHA_0_SHA_KEY_0_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_1 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_1 :: SHA_KEY_1 [31:00] */ +#define OTP_CONTENT_SHA_1_SHA_KEY_1_MASK 0xffffffff +#define OTP_CONTENT_SHA_1_SHA_KEY_1_ALIGN 0 +#define OTP_CONTENT_SHA_1_SHA_KEY_1_BITS 32 +#define OTP_CONTENT_SHA_1_SHA_KEY_1_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_2 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_2 :: SHA_KEY_2 [31:00] */ +#define OTP_CONTENT_SHA_2_SHA_KEY_2_MASK 0xffffffff +#define OTP_CONTENT_SHA_2_SHA_KEY_2_ALIGN 0 +#define OTP_CONTENT_SHA_2_SHA_KEY_2_BITS 32 +#define OTP_CONTENT_SHA_2_SHA_KEY_2_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_3 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_3 :: SHA_KEY_3 [31:00] */ +#define OTP_CONTENT_SHA_3_SHA_KEY_3_MASK 0xffffffff +#define OTP_CONTENT_SHA_3_SHA_KEY_3_ALIGN 0 +#define OTP_CONTENT_SHA_3_SHA_KEY_3_BITS 32 +#define OTP_CONTENT_SHA_3_SHA_KEY_3_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_4 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_4 :: SHA_KEY_4 [31:00] */ +#define OTP_CONTENT_SHA_4_SHA_KEY_4_MASK 0xffffffff +#define OTP_CONTENT_SHA_4_SHA_KEY_4_ALIGN 0 +#define OTP_CONTENT_SHA_4_SHA_KEY_4_BITS 32 +#define OTP_CONTENT_SHA_4_SHA_KEY_4_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_5 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_5 :: SHA_KEY_5 [31:00] */ +#define OTP_CONTENT_SHA_5_SHA_KEY_5_MASK 0xffffffff +#define OTP_CONTENT_SHA_5_SHA_KEY_5_ALIGN 0 +#define OTP_CONTENT_SHA_5_SHA_KEY_5_BITS 32 +#define OTP_CONTENT_SHA_5_SHA_KEY_5_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_6 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_6 :: SHA_KEY_6 [31:00] */ +#define OTP_CONTENT_SHA_6_SHA_KEY_6_MASK 0xffffffff +#define OTP_CONTENT_SHA_6_SHA_KEY_6_ALIGN 0 +#define OTP_CONTENT_SHA_6_SHA_KEY_6_BITS 32 +#define OTP_CONTENT_SHA_6_SHA_KEY_6_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_7 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_7 :: SHA_KEY_7 [31:00] */ +#define OTP_CONTENT_SHA_7_SHA_KEY_7_MASK 0xffffffff +#define OTP_CONTENT_SHA_7_SHA_KEY_7_ALIGN 0 +#define OTP_CONTENT_SHA_7_SHA_KEY_7_BITS 32 +#define OTP_CONTENT_SHA_7_SHA_KEY_7_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_CHECKSUM + ***************************************************************************/ +/* OTP :: CONTENT_CHECKSUM :: reserved0 [31:16] */ +#define OTP_CONTENT_CHECKSUM_reserved0_MASK 0xffff0000 +#define OTP_CONTENT_CHECKSUM_reserved0_ALIGN 0 +#define OTP_CONTENT_CHECKSUM_reserved0_BITS 16 +#define OTP_CONTENT_CHECKSUM_reserved0_SHIFT 16 + +/* OTP :: CONTENT_CHECKSUM :: CHECKSUM [15:00] */ +#define OTP_CONTENT_CHECKSUM_CHECKSUM_MASK 0x0000ffff +#define OTP_CONTENT_CHECKSUM_CHECKSUM_ALIGN 0 +#define OTP_CONTENT_CHECKSUM_CHECKSUM_BITS 16 +#define OTP_CONTENT_CHECKSUM_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_CTRL + ***************************************************************************/ +/* OTP :: PROG_CTRL :: reserved0 [31:02] */ +#define OTP_PROG_CTRL_reserved0_MASK 0xfffffffc +#define OTP_PROG_CTRL_reserved0_ALIGN 0 +#define OTP_PROG_CTRL_reserved0_BITS 30 +#define OTP_PROG_CTRL_reserved0_SHIFT 2 + +/* OTP :: PROG_CTRL :: ENABLE [01:01] */ +#define OTP_PROG_CTRL_ENABLE_MASK 0x00000002 +#define OTP_PROG_CTRL_ENABLE_ALIGN 0 +#define OTP_PROG_CTRL_ENABLE_BITS 1 +#define OTP_PROG_CTRL_ENABLE_SHIFT 1 + +/* OTP :: PROG_CTRL :: RST [00:00] */ +#define OTP_PROG_CTRL_RST_MASK 0x00000001 +#define OTP_PROG_CTRL_RST_ALIGN 0 +#define OTP_PROG_CTRL_RST_BITS 1 +#define OTP_PROG_CTRL_RST_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_STATUS + ***************************************************************************/ +/* OTP :: PROG_STATUS :: reserved0 [31:02] */ +#define OTP_PROG_STATUS_reserved0_MASK 0xfffffffc +#define OTP_PROG_STATUS_reserved0_ALIGN 0 +#define OTP_PROG_STATUS_reserved0_BITS 30 +#define OTP_PROG_STATUS_reserved0_SHIFT 2 + +/* OTP :: PROG_STATUS :: ORDY [01:01] */ +#define OTP_PROG_STATUS_ORDY_MASK 0x00000002 +#define OTP_PROG_STATUS_ORDY_ALIGN 0 +#define OTP_PROG_STATUS_ORDY_BITS 1 +#define OTP_PROG_STATUS_ORDY_SHIFT 1 + +/* OTP :: PROG_STATUS :: IRDY [00:00] */ +#define OTP_PROG_STATUS_IRDY_MASK 0x00000001 +#define OTP_PROG_STATUS_IRDY_ALIGN 0 +#define OTP_PROG_STATUS_IRDY_BITS 1 +#define OTP_PROG_STATUS_IRDY_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_PULSE + ***************************************************************************/ +/* OTP :: PROG_PULSE :: PROG_HI [31:00] */ +#define OTP_PROG_PULSE_PROG_HI_MASK 0xffffffff +#define OTP_PROG_PULSE_PROG_HI_ALIGN 0 +#define OTP_PROG_PULSE_PROG_HI_BITS 32 +#define OTP_PROG_PULSE_PROG_HI_SHIFT 0 + + +/**************************************************************************** + * OTP :: VERIFY_PULSE + ***************************************************************************/ +/* OTP :: VERIFY_PULSE :: PROG_LOW [31:16] */ +#define OTP_VERIFY_PULSE_PROG_LOW_MASK 0xffff0000 +#define OTP_VERIFY_PULSE_PROG_LOW_ALIGN 0 +#define OTP_VERIFY_PULSE_PROG_LOW_BITS 16 +#define OTP_VERIFY_PULSE_PROG_LOW_SHIFT 16 + +/* OTP :: VERIFY_PULSE :: VERIFY [15:00] */ +#define OTP_VERIFY_PULSE_VERIFY_MASK 0x0000ffff +#define OTP_VERIFY_PULSE_VERIFY_ALIGN 0 +#define OTP_VERIFY_PULSE_VERIFY_BITS 16 +#define OTP_VERIFY_PULSE_VERIFY_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_MASK + ***************************************************************************/ +/* OTP :: PROG_MASK :: reserved0 [31:17] */ +#define OTP_PROG_MASK_reserved0_MASK 0xfffe0000 +#define OTP_PROG_MASK_reserved0_ALIGN 0 +#define OTP_PROG_MASK_reserved0_BITS 15 +#define OTP_PROG_MASK_reserved0_SHIFT 17 + +/* OTP :: PROG_MASK :: PROG_MASK [16:00] */ +#define OTP_PROG_MASK_PROG_MASK_MASK 0x0001ffff +#define OTP_PROG_MASK_PROG_MASK_ALIGN 0 +#define OTP_PROG_MASK_PROG_MASK_BITS 17 +#define OTP_PROG_MASK_PROG_MASK_SHIFT 0 + + +/**************************************************************************** + * OTP :: DATA_INPUT + ***************************************************************************/ +/* OTP :: DATA_INPUT :: reserved0 [31:31] */ +#define OTP_DATA_INPUT_reserved0_MASK 0x80000000 +#define OTP_DATA_INPUT_reserved0_ALIGN 0 +#define OTP_DATA_INPUT_reserved0_BITS 1 +#define OTP_DATA_INPUT_reserved0_SHIFT 31 + +/* OTP :: DATA_INPUT :: CMD [30:28] */ +#define OTP_DATA_INPUT_CMD_MASK 0x70000000 +#define OTP_DATA_INPUT_CMD_ALIGN 0 +#define OTP_DATA_INPUT_CMD_BITS 3 +#define OTP_DATA_INPUT_CMD_SHIFT 28 + +/* OTP :: DATA_INPUT :: reserved1 [27:26] */ +#define OTP_DATA_INPUT_reserved1_MASK 0x0c000000 +#define OTP_DATA_INPUT_reserved1_ALIGN 0 +#define OTP_DATA_INPUT_reserved1_BITS 2 +#define OTP_DATA_INPUT_reserved1_SHIFT 26 + +/* OTP :: DATA_INPUT :: ADDR [25:20] */ +#define OTP_DATA_INPUT_ADDR_MASK 0x03f00000 +#define OTP_DATA_INPUT_ADDR_ALIGN 0 +#define OTP_DATA_INPUT_ADDR_BITS 6 +#define OTP_DATA_INPUT_ADDR_SHIFT 20 + +/* OTP :: DATA_INPUT :: reserved2 [19:18] */ +#define OTP_DATA_INPUT_reserved2_MASK 0x000c0000 +#define OTP_DATA_INPUT_reserved2_ALIGN 0 +#define OTP_DATA_INPUT_reserved2_BITS 2 +#define OTP_DATA_INPUT_reserved2_SHIFT 18 + +/* OTP :: DATA_INPUT :: WRCOL [17:17] */ +#define OTP_DATA_INPUT_WRCOL_MASK 0x00020000 +#define OTP_DATA_INPUT_WRCOL_ALIGN 0 +#define OTP_DATA_INPUT_WRCOL_BITS 1 +#define OTP_DATA_INPUT_WRCOL_SHIFT 17 + +/* OTP :: DATA_INPUT :: DIN [16:00] */ +#define OTP_DATA_INPUT_DIN_MASK 0x0001ffff +#define OTP_DATA_INPUT_DIN_ALIGN 0 +#define OTP_DATA_INPUT_DIN_BITS 17 +#define OTP_DATA_INPUT_DIN_SHIFT 0 + + +/**************************************************************************** + * OTP :: DATA_OUTPUT + ***************************************************************************/ +/* OTP :: DATA_OUTPUT :: reserved0 [31:17] */ +#define OTP_DATA_OUTPUT_reserved0_MASK 0xfffe0000 +#define OTP_DATA_OUTPUT_reserved0_ALIGN 0 +#define OTP_DATA_OUTPUT_reserved0_BITS 15 +#define OTP_DATA_OUTPUT_reserved0_SHIFT 17 + +/* OTP :: DATA_OUTPUT :: DOUT [16:00] */ +#define OTP_DATA_OUTPUT_DOUT_MASK 0x0001ffff +#define OTP_DATA_OUTPUT_DOUT_ALIGN 0 +#define OTP_DATA_OUTPUT_DOUT_BITS 17 +#define OTP_DATA_OUTPUT_DOUT_SHIFT 0 + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * OTP_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* OTP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define OTP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define OTP_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define OTP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* OTP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define OTP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define OTP_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define OTP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* OTP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define OTP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define OTP_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define OTP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * OTP_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* OTP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define OTP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 +/**************************************************************************** + * OTP_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 +/**************************************************************************** + * OTP_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: OTP_00_SW_RESET [00:00] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_MASK 0x00000001 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_BITS 1 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_SHIFT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_DEASSERT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ASSERT 1 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 +/**************************************************************************** + * BCM70012_AES_TOP_AES + ***************************************************************************/ +/**************************************************************************** + * AES :: CONFIG_INFO + ***************************************************************************/ +/* AES :: CONFIG_INFO :: SWAP [31:31] */ +#define AES_CONFIG_INFO_SWAP_MASK 0x80000000 +#define AES_CONFIG_INFO_SWAP_ALIGN 0 +#define AES_CONFIG_INFO_SWAP_BITS 1 +#define AES_CONFIG_INFO_SWAP_SHIFT 31 + +/* AES :: CONFIG_INFO :: reserved0 [30:19] */ +#define AES_CONFIG_INFO_reserved0_MASK 0x7ff80000 +#define AES_CONFIG_INFO_reserved0_ALIGN 0 +#define AES_CONFIG_INFO_reserved0_BITS 12 +#define AES_CONFIG_INFO_reserved0_SHIFT 19 + +/* AES :: CONFIG_INFO :: OFFSET [18:02] */ +#define AES_CONFIG_INFO_OFFSET_MASK 0x0007fffc +#define AES_CONFIG_INFO_OFFSET_ALIGN 0 +#define AES_CONFIG_INFO_OFFSET_BITS 17 +#define AES_CONFIG_INFO_OFFSET_SHIFT 2 + +/* AES :: CONFIG_INFO :: reserved1 [01:00] */ +#define AES_CONFIG_INFO_reserved1_MASK 0x00000003 +#define AES_CONFIG_INFO_reserved1_ALIGN 0 +#define AES_CONFIG_INFO_reserved1_BITS 2 +#define AES_CONFIG_INFO_reserved1_SHIFT 0 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 -#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 +/**************************************************************************** + * AES :: CMD + ***************************************************************************/ +/* AES :: CMD :: reserved0 [31:13] */ +#define AES_CMD_reserved0_MASK 0xffffe000 +#define AES_CMD_reserved0_ALIGN 0 +#define AES_CMD_reserved0_BITS 19 +#define AES_CMD_reserved0_SHIFT 13 + +/* AES :: CMD :: WRITE_EEPROM [12:12] */ +#define AES_CMD_WRITE_EEPROM_MASK 0x00001000 +#define AES_CMD_WRITE_EEPROM_ALIGN 0 +#define AES_CMD_WRITE_EEPROM_BITS 1 +#define AES_CMD_WRITE_EEPROM_SHIFT 12 + +/* AES :: CMD :: reserved1 [11:09] */ +#define AES_CMD_reserved1_MASK 0x00000e00 +#define AES_CMD_reserved1_ALIGN 0 +#define AES_CMD_reserved1_BITS 3 +#define AES_CMD_reserved1_SHIFT 9 + +/* AES :: CMD :: START_EEPROM_COPY [08:08] */ +#define AES_CMD_START_EEPROM_COPY_MASK 0x00000100 +#define AES_CMD_START_EEPROM_COPY_ALIGN 0 +#define AES_CMD_START_EEPROM_COPY_BITS 1 +#define AES_CMD_START_EEPROM_COPY_SHIFT 8 + +/* AES :: CMD :: reserved2 [07:05] */ +#define AES_CMD_reserved2_MASK 0x000000e0 +#define AES_CMD_reserved2_ALIGN 0 +#define AES_CMD_reserved2_BITS 3 +#define AES_CMD_reserved2_SHIFT 5 + +/* AES :: CMD :: PREPARE_ENCRYPTION [04:04] */ +#define AES_CMD_PREPARE_ENCRYPTION_MASK 0x00000010 +#define AES_CMD_PREPARE_ENCRYPTION_ALIGN 0 +#define AES_CMD_PREPARE_ENCRYPTION_BITS 1 +#define AES_CMD_PREPARE_ENCRYPTION_SHIFT 4 + +/* AES :: CMD :: reserved3 [03:01] */ +#define AES_CMD_reserved3_MASK 0x0000000e +#define AES_CMD_reserved3_ALIGN 0 +#define AES_CMD_reserved3_BITS 3 +#define AES_CMD_reserved3_SHIFT 1 + +/* AES :: CMD :: START_KEY_LOAD [00:00] */ +#define AES_CMD_START_KEY_LOAD_MASK 0x00000001 +#define AES_CMD_START_KEY_LOAD_ALIGN 0 +#define AES_CMD_START_KEY_LOAD_BITS 1 +#define AES_CMD_START_KEY_LOAD_SHIFT 0 -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 +/**************************************************************************** + * AES :: STATUS + ***************************************************************************/ +/* AES :: STATUS :: reserved0 [31:23] */ +#define AES_STATUS_reserved0_MASK 0xff800000 +#define AES_STATUS_reserved0_ALIGN 0 +#define AES_STATUS_reserved0_BITS 9 +#define AES_STATUS_reserved0_SHIFT 23 + +/* AES :: STATUS :: STUCK_AT_ZERO [22:22] */ +#define AES_STATUS_STUCK_AT_ZERO_MASK 0x00400000 +#define AES_STATUS_STUCK_AT_ZERO_ALIGN 0 +#define AES_STATUS_STUCK_AT_ZERO_BITS 1 +#define AES_STATUS_STUCK_AT_ZERO_SHIFT 22 + +/* AES :: STATUS :: STUCK_AT_ONE [21:21] */ +#define AES_STATUS_STUCK_AT_ONE_MASK 0x00200000 +#define AES_STATUS_STUCK_AT_ONE_ALIGN 0 +#define AES_STATUS_STUCK_AT_ONE_BITS 1 +#define AES_STATUS_STUCK_AT_ONE_SHIFT 21 + +/* AES :: STATUS :: RANDOM_READY [20:20] */ +#define AES_STATUS_RANDOM_READY_MASK 0x00100000 +#define AES_STATUS_RANDOM_READY_ALIGN 0 +#define AES_STATUS_RANDOM_READY_BITS 1 +#define AES_STATUS_RANDOM_READY_SHIFT 20 + +/* AES :: STATUS :: reserved1 [19:16] */ +#define AES_STATUS_reserved1_MASK 0x000f0000 +#define AES_STATUS_reserved1_ALIGN 0 +#define AES_STATUS_reserved1_BITS 4 +#define AES_STATUS_reserved1_SHIFT 16 + +/* AES :: STATUS :: WRITE_EEPROM_TIMEOUT [15:15] */ +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_MASK 0x00008000 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_ALIGN 0 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_BITS 1 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_SHIFT 15 + +/* AES :: STATUS :: WRITE_DATA_MISMATCH [14:14] */ +#define AES_STATUS_WRITE_DATA_MISMATCH_MASK 0x00004000 +#define AES_STATUS_WRITE_DATA_MISMATCH_ALIGN 0 +#define AES_STATUS_WRITE_DATA_MISMATCH_BITS 1 +#define AES_STATUS_WRITE_DATA_MISMATCH_SHIFT 14 + +/* AES :: STATUS :: WRITE_GISB_ERROR [13:13] */ +#define AES_STATUS_WRITE_GISB_ERROR_MASK 0x00002000 +#define AES_STATUS_WRITE_GISB_ERROR_ALIGN 0 +#define AES_STATUS_WRITE_GISB_ERROR_BITS 1 +#define AES_STATUS_WRITE_GISB_ERROR_SHIFT 13 + +/* AES :: STATUS :: WRITE_DONE [12:12] */ +#define AES_STATUS_WRITE_DONE_MASK 0x00001000 +#define AES_STATUS_WRITE_DONE_ALIGN 0 +#define AES_STATUS_WRITE_DONE_BITS 1 +#define AES_STATUS_WRITE_DONE_SHIFT 12 + +/* AES :: STATUS :: reserved2 [11:11] */ +#define AES_STATUS_reserved2_MASK 0x00000800 +#define AES_STATUS_reserved2_ALIGN 0 +#define AES_STATUS_reserved2_BITS 1 +#define AES_STATUS_reserved2_SHIFT 11 + +/* AES :: STATUS :: COPY_EEPROM_ERROR [10:10] */ +#define AES_STATUS_COPY_EEPROM_ERROR_MASK 0x00000400 +#define AES_STATUS_COPY_EEPROM_ERROR_ALIGN 0 +#define AES_STATUS_COPY_EEPROM_ERROR_BITS 1 +#define AES_STATUS_COPY_EEPROM_ERROR_SHIFT 10 + +/* AES :: STATUS :: COPY_GISB_ERROR [09:09] */ +#define AES_STATUS_COPY_GISB_ERROR_MASK 0x00000200 +#define AES_STATUS_COPY_GISB_ERROR_ALIGN 0 +#define AES_STATUS_COPY_GISB_ERROR_BITS 1 +#define AES_STATUS_COPY_GISB_ERROR_SHIFT 9 + +/* AES :: STATUS :: COPY_DONE [08:08] */ +#define AES_STATUS_COPY_DONE_MASK 0x00000100 +#define AES_STATUS_COPY_DONE_ALIGN 0 +#define AES_STATUS_COPY_DONE_BITS 1 +#define AES_STATUS_COPY_DONE_SHIFT 8 + +/* AES :: STATUS :: PREPARE_EEPROM_TIMEOUT [07:07] */ +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_MASK 0x00000080 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_ALIGN 0 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_BITS 1 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_SHIFT 7 + +/* AES :: STATUS :: PREPARE_DATA_MISMATCH [06:06] */ +#define AES_STATUS_PREPARE_DATA_MISMATCH_MASK 0x00000040 +#define AES_STATUS_PREPARE_DATA_MISMATCH_ALIGN 0 +#define AES_STATUS_PREPARE_DATA_MISMATCH_BITS 1 +#define AES_STATUS_PREPARE_DATA_MISMATCH_SHIFT 6 + +/* AES :: STATUS :: PREPARE_GISB_ERROR [05:05] */ +#define AES_STATUS_PREPARE_GISB_ERROR_MASK 0x00000020 +#define AES_STATUS_PREPARE_GISB_ERROR_ALIGN 0 +#define AES_STATUS_PREPARE_GISB_ERROR_BITS 1 +#define AES_STATUS_PREPARE_GISB_ERROR_SHIFT 5 + +/* AES :: STATUS :: PREPARE_DONE [04:04] */ +#define AES_STATUS_PREPARE_DONE_MASK 0x00000010 +#define AES_STATUS_PREPARE_DONE_ALIGN 0 +#define AES_STATUS_PREPARE_DONE_BITS 1 +#define AES_STATUS_PREPARE_DONE_SHIFT 4 + +/* AES :: STATUS :: reserved3 [03:02] */ +#define AES_STATUS_reserved3_MASK 0x0000000c +#define AES_STATUS_reserved3_ALIGN 0 +#define AES_STATUS_reserved3_BITS 2 +#define AES_STATUS_reserved3_SHIFT 2 + +/* AES :: STATUS :: KEY_LOAD_GISB_ERROR [01:01] */ +#define AES_STATUS_KEY_LOAD_GISB_ERROR_MASK 0x00000002 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_ALIGN 0 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_BITS 1 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_SHIFT 1 + +/* AES :: STATUS :: KEY_LOAD_DONE [00:00] */ +#define AES_STATUS_KEY_LOAD_DONE_MASK 0x00000001 +#define AES_STATUS_KEY_LOAD_DONE_ALIGN 0 +#define AES_STATUS_KEY_LOAD_DONE_BITS 1 +#define AES_STATUS_KEY_LOAD_DONE_SHIFT 0 /**************************************************************************** - * MISC1 :: UV_RX_ERROR_STATUS + * AES :: EEPROM_CONFIG ***************************************************************************/ -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 +/* AES :: EEPROM_CONFIG :: LENGTH [31:20] */ +#define AES_EEPROM_CONFIG_LENGTH_MASK 0xfff00000 +#define AES_EEPROM_CONFIG_LENGTH_ALIGN 0 +#define AES_EEPROM_CONFIG_LENGTH_BITS 12 +#define AES_EEPROM_CONFIG_LENGTH_SHIFT 20 + +/* AES :: EEPROM_CONFIG :: reserved0 [19:16] */ +#define AES_EEPROM_CONFIG_reserved0_MASK 0x000f0000 +#define AES_EEPROM_CONFIG_reserved0_ALIGN 0 +#define AES_EEPROM_CONFIG_reserved0_BITS 4 +#define AES_EEPROM_CONFIG_reserved0_SHIFT 16 + +/* AES :: EEPROM_CONFIG :: START_ADDR [15:02] */ +#define AES_EEPROM_CONFIG_START_ADDR_MASK 0x0000fffc +#define AES_EEPROM_CONFIG_START_ADDR_ALIGN 0 +#define AES_EEPROM_CONFIG_START_ADDR_BITS 14 +#define AES_EEPROM_CONFIG_START_ADDR_SHIFT 2 + +/* AES :: EEPROM_CONFIG :: reserved1 [01:00] */ +#define AES_EEPROM_CONFIG_reserved1_MASK 0x00000003 +#define AES_EEPROM_CONFIG_reserved1_ALIGN 0 +#define AES_EEPROM_CONFIG_reserved1_BITS 2 +#define AES_EEPROM_CONFIG_reserved1_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 +/**************************************************************************** + * AES :: EEPROM_DATA_0 + ***************************************************************************/ +/* AES :: EEPROM_DATA_0 :: DATA [31:00] */ +#define AES_EEPROM_DATA_0_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_0_DATA_ALIGN 0 +#define AES_EEPROM_DATA_0_DATA_BITS 32 +#define AES_EEPROM_DATA_0_DATA_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 +/**************************************************************************** + * AES :: EEPROM_DATA_1 + ***************************************************************************/ +/* AES :: EEPROM_DATA_1 :: DATA [31:00] */ +#define AES_EEPROM_DATA_1_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_1_DATA_ALIGN 0 +#define AES_EEPROM_DATA_1_DATA_BITS 32 +#define AES_EEPROM_DATA_1_DATA_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 +/**************************************************************************** + * AES :: EEPROM_DATA_2 + ***************************************************************************/ +/* AES :: EEPROM_DATA_2 :: DATA [31:00] */ +#define AES_EEPROM_DATA_2_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_2_DATA_ALIGN 0 +#define AES_EEPROM_DATA_2_DATA_BITS 32 +#define AES_EEPROM_DATA_2_DATA_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 +/**************************************************************************** + * AES :: EEPROM_DATA_3 + ***************************************************************************/ +/* AES :: EEPROM_DATA_3 :: DATA [31:00] */ +#define AES_EEPROM_DATA_3_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_3_DATA_ALIGN 0 +#define AES_EEPROM_DATA_3_DATA_BITS 32 +#define AES_EEPROM_DATA_3_DATA_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 -#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 +/**************************************************************************** + * BCM70012_AES_TOP_AES_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * AES_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* AES_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define AES_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define AES_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define AES_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* AES_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define AES_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define AES_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define AES_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* AES_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define AES_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define AES_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define AES_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 +/**************************************************************************** + * AES_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* AES_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define AES_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define AES_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define AES_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* AES_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* AES_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* AES_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* AES_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI + ***************************************************************************/ +/**************************************************************************** + * DCI :: CMD + ***************************************************************************/ +/* DCI :: CMD :: reserved0 [31:09] */ +#define DCI_CMD_reserved0_MASK 0xfffffe00 +#define DCI_CMD_reserved0_ALIGN 0 +#define DCI_CMD_reserved0_BITS 23 +#define DCI_CMD_reserved0_SHIFT 9 + +/* DCI :: CMD :: FORCE_FW_VALIDATED [08:08] */ +#define DCI_CMD_FORCE_FW_VALIDATED_MASK 0x00000100 +#define DCI_CMD_FORCE_FW_VALIDATED_ALIGN 0 +#define DCI_CMD_FORCE_FW_VALIDATED_BITS 1 +#define DCI_CMD_FORCE_FW_VALIDATED_SHIFT 8 + +/* DCI :: CMD :: reserved1 [07:05] */ +#define DCI_CMD_reserved1_MASK 0x000000e0 +#define DCI_CMD_reserved1_ALIGN 0 +#define DCI_CMD_reserved1_BITS 3 +#define DCI_CMD_reserved1_SHIFT 5 + +/* DCI :: CMD :: START_PROCESSOR [04:04] */ +#define DCI_CMD_START_PROCESSOR_MASK 0x00000010 +#define DCI_CMD_START_PROCESSOR_ALIGN 0 +#define DCI_CMD_START_PROCESSOR_BITS 1 +#define DCI_CMD_START_PROCESSOR_SHIFT 4 + +/* DCI :: CMD :: reserved2 [03:02] */ +#define DCI_CMD_reserved2_MASK 0x0000000c +#define DCI_CMD_reserved2_ALIGN 0 +#define DCI_CMD_reserved2_BITS 2 +#define DCI_CMD_reserved2_SHIFT 2 + +/* DCI :: CMD :: DOWNLOAD_COMPLETE [01:01] */ +#define DCI_CMD_DOWNLOAD_COMPLETE_MASK 0x00000002 +#define DCI_CMD_DOWNLOAD_COMPLETE_ALIGN 0 +#define DCI_CMD_DOWNLOAD_COMPLETE_BITS 1 +#define DCI_CMD_DOWNLOAD_COMPLETE_SHIFT 1 + +/* DCI :: CMD :: INITIATE_FW_DOWNLOAD [00:00] */ +#define DCI_CMD_INITIATE_FW_DOWNLOAD_MASK 0x00000001 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_ALIGN 0 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_BITS 1 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_SHIFT 0 + + +/**************************************************************************** + * DCI :: STATUS + ***************************************************************************/ +/* DCI :: STATUS :: reserved0 [31:10] */ +#define DCI_STATUS_reserved0_MASK 0xfffffc00 +#define DCI_STATUS_reserved0_ALIGN 0 +#define DCI_STATUS_reserved0_BITS 22 +#define DCI_STATUS_reserved0_SHIFT 10 + +/* DCI :: STATUS :: SIGNATURE_MATCHED [09:09] */ +#define DCI_STATUS_SIGNATURE_MATCHED_MASK 0x00000200 +#define DCI_STATUS_SIGNATURE_MATCHED_ALIGN 0 +#define DCI_STATUS_SIGNATURE_MATCHED_BITS 1 +#define DCI_STATUS_SIGNATURE_MATCHED_SHIFT 9 + +/* DCI :: STATUS :: SIGNATURE_MISMATCH [08:08] */ +#define DCI_STATUS_SIGNATURE_MISMATCH_MASK 0x00000100 +#define DCI_STATUS_SIGNATURE_MISMATCH_ALIGN 0 +#define DCI_STATUS_SIGNATURE_MISMATCH_BITS 1 +#define DCI_STATUS_SIGNATURE_MISMATCH_SHIFT 8 + +/* DCI :: STATUS :: reserved1 [07:06] */ +#define DCI_STATUS_reserved1_MASK 0x000000c0 +#define DCI_STATUS_reserved1_ALIGN 0 +#define DCI_STATUS_reserved1_BITS 2 +#define DCI_STATUS_reserved1_SHIFT 6 + +/* DCI :: STATUS :: GISB_ERROR [05:05] */ +#define DCI_STATUS_GISB_ERROR_MASK 0x00000020 +#define DCI_STATUS_GISB_ERROR_ALIGN 0 +#define DCI_STATUS_GISB_ERROR_BITS 1 +#define DCI_STATUS_GISB_ERROR_SHIFT 5 + +/* DCI :: STATUS :: DOWNLOAD_READY [04:04] */ +#define DCI_STATUS_DOWNLOAD_READY_MASK 0x00000010 +#define DCI_STATUS_DOWNLOAD_READY_ALIGN 0 +#define DCI_STATUS_DOWNLOAD_READY_BITS 1 +#define DCI_STATUS_DOWNLOAD_READY_SHIFT 4 + +/* DCI :: STATUS :: reserved2 [03:01] */ +#define DCI_STATUS_reserved2_MASK 0x0000000e +#define DCI_STATUS_reserved2_ALIGN 0 +#define DCI_STATUS_reserved2_BITS 3 +#define DCI_STATUS_reserved2_SHIFT 1 + +/* DCI :: STATUS :: FIRMWARE_VALIDATED [00:00] */ +#define DCI_STATUS_FIRMWARE_VALIDATED_MASK 0x00000001 +#define DCI_STATUS_FIRMWARE_VALIDATED_ALIGN 0 +#define DCI_STATUS_FIRMWARE_VALIDATED_BITS 1 +#define DCI_STATUS_FIRMWARE_VALIDATED_SHIFT 0 + + +/**************************************************************************** + * DCI :: DRAM_BASE_ADDR + ***************************************************************************/ +/* DCI :: DRAM_BASE_ADDR :: reserved0 [31:13] */ +#define DCI_DRAM_BASE_ADDR_reserved0_MASK 0xffffe000 +#define DCI_DRAM_BASE_ADDR_reserved0_ALIGN 0 +#define DCI_DRAM_BASE_ADDR_reserved0_BITS 19 +#define DCI_DRAM_BASE_ADDR_reserved0_SHIFT 13 + +/* DCI :: DRAM_BASE_ADDR :: BASE_ADDR [12:00] */ +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_MASK 0x00001fff +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_ALIGN 0 +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_BITS 13 +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_SHIFT 0 + + +/**************************************************************************** + * DCI :: FIRMWARE_ADDR + ***************************************************************************/ +/* DCI :: FIRMWARE_ADDR :: reserved0 [31:19] */ +#define DCI_FIRMWARE_ADDR_reserved0_MASK 0xfff80000 +#define DCI_FIRMWARE_ADDR_reserved0_ALIGN 0 +#define DCI_FIRMWARE_ADDR_reserved0_BITS 13 +#define DCI_FIRMWARE_ADDR_reserved0_SHIFT 19 + +/* DCI :: FIRMWARE_ADDR :: FW_ADDR [18:02] */ +#define DCI_FIRMWARE_ADDR_FW_ADDR_MASK 0x0007fffc +#define DCI_FIRMWARE_ADDR_FW_ADDR_ALIGN 0 +#define DCI_FIRMWARE_ADDR_FW_ADDR_BITS 17 +#define DCI_FIRMWARE_ADDR_FW_ADDR_SHIFT 2 + +/* DCI :: FIRMWARE_ADDR :: reserved1 [01:00] */ +#define DCI_FIRMWARE_ADDR_reserved1_MASK 0x00000003 +#define DCI_FIRMWARE_ADDR_reserved1_ALIGN 0 +#define DCI_FIRMWARE_ADDR_reserved1_BITS 2 +#define DCI_FIRMWARE_ADDR_reserved1_SHIFT 0 + + +/**************************************************************************** + * DCI :: FIRMWARE_DATA + ***************************************************************************/ +/* DCI :: FIRMWARE_DATA :: FW_DATA [31:00] */ +#define DCI_FIRMWARE_DATA_FW_DATA_MASK 0xffffffff +#define DCI_FIRMWARE_DATA_FW_DATA_ALIGN 0 +#define DCI_FIRMWARE_DATA_FW_DATA_BITS 32 +#define DCI_FIRMWARE_DATA_FW_DATA_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_0 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_0 :: SIG_DATA_0 [31:00] */ +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_ALIGN 0 +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_BITS 32 +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_1 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_1 :: SIG_DATA_1 [31:00] */ +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_ALIGN 0 +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_BITS 32 +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_2 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_2 :: SIG_DATA_2 [31:00] */ +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_ALIGN 0 +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_BITS 32 +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_3 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_3 :: SIG_DATA_3 [31:00] */ +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_ALIGN 0 +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_BITS 32 +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_4 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_4 :: SIG_DATA_4 [31:00] */ +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_ALIGN 0 +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_BITS 32 +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_5 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_5 :: SIG_DATA_5 [31:00] */ +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_ALIGN 0 +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_BITS 32 +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_6 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_6 :: SIG_DATA_6 [31:00] */ +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_ALIGN 0 +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_BITS 32 +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_7 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_7 :: SIG_DATA_7 [31:00] */ +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_ALIGN 0 +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_BITS 32 +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_SHIFT 0 + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * DCI_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define DCI_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define DCI_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define DCI_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* DCI_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define DCI_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* DCI_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define DCI_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define DCI_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define DCI_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define DCI_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define DCI_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define DCI_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* DCI_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* DCI_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* DCI_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_CCE_TOP_CCE_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * CCE_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define CCE_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define CCE_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define CCE_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + /**************************************************************************** * Datatype Definitions. @@ -754,4 +12296,3 @@ #endif /* #ifndef MACFILE_H__ */ /* End of File */ - --- crystalhd~/bcm_70015_regs.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/bcm_70015_regs.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,1376 @@ +/*************************************************************************** + * Copyright (c) 1999-2009, Broadcom Corporation + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + ********************************************************************** + * + * $brcm_Workfile: bchp_misc1.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:11p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:40 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:11p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_MISC1_H__ +#define BCHP_MISC1_H__ + +/*************************************************************************** + *MISC1 - Registers for DMA List Control + ***************************************************************************/ +#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00502000 /* Tx DMA Descriptor List0 First Descriptor lower Address */ +#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00502004 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ +#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00502008 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ +#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x0050200c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ +#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00502010 /* Tx DMA Software Descriptor List Control and Status */ +#define BCHP_MISC1_TX_DMA_ERROR_STATUS 0x00502018 /* Tx DMA Engine Error Status */ +#define BCHP_MISC1_TX_DMA_CTRL 0x00502034 /* Tx DMA Flea Interface Control */ +#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00502050 /* Y Rx Software Descriptor List Control and Status */ +#define BCHP_MISC1_Y_RX_ERROR_STATUS 0x00502054 /* Y Rx Engine Error Status */ +#define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00502060 /* Y Rx List0 Current Descriptor Byte Count */ +#define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x0050206c /* Y Rx List1 Current Descriptor Byte Count */ +#define BCHP_MISC1_HIF_RX_ERROR_STATUS 0x00502094 /* HIF Rx Engine Error Status */ +#define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT 0x005020a0 /* HIF Rx List0 Current Descriptor Byte Count */ +#define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT 0x005020ac /* HIF Rx List1 Current Descriptor Byte Count */ +#define BCHP_MISC1_HIF_DMA_CTRL 0x005020b0 /* HIF Rx DMA Flea Interface Control */ +#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG 0x005020c0 /* DMA Debug Options Register */ + +/*************************************************************************** + *TX_SW_DESC_LIST_CTRL_STS - Tx DMA Software Descriptor List Control and Status + ***************************************************************************/ +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ +#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 + +#endif /* #ifndef BCHP_MISC1_H__ */ + +/********************************************************************** + * + * $brcm_Workfile: bchp_misc2.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:11p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:37 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:11p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_MISC2_H__ +#define BCHP_MISC2_H__ + +/*************************************************************************** + *MISC2 - Registers for Meta DMA, Direct DRAM Access, Global Controls + ***************************************************************************/ +#define BCHP_MISC2_DIRECT_WINDOW_CONTROL 0x00502120 /* Direct DRAM Access Window Control */ + +/*************************************************************************** + *DIRECT_WINDOW_CONTROL - Direct DRAM Access Window Control + ***************************************************************************/ +/* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_BASE_ADDR [31:16] */ +#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK 0xffff0000 + +/* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_ENABLE [00:00] */ +#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK 0x00000001 + +#endif /* #ifndef BCHP_MISC2_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_misc3.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:11p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:19 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:11p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_MISC3_H__ +#define BCHP_MISC3_H__ + +/*************************************************************************** + *MISC3 - Registers for Reset, Options, DMA Checksums + ***************************************************************************/ +#define BCHP_MISC3_RESET_CTRL 0x00502200 /* Reset Control Register */ + +#endif /* #ifndef BCHP_MISC3_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_scrub_ctrl.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:18p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:19 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:18p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_SCRUB_CTRL_H__ +#define BCHP_SCRUB_CTRL_H__ + +/*************************************************************************** + *SCRUB_CTRL - Scrub Control Registers + ***************************************************************************/ +#define BCHP_SCRUB_CTRL_SCRUB_ENABLE 0x000f6000 /* Secure Sequencer Enable */ +#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS 0x000f6004 /* ARM Bridge Out-of-Range Checker End Address */ +#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS 0x000f6008 /* Static ARCH End Address */ +#define BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c /* Boot Image CMAC value[31:0] */ +#define BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 /* Boot Image CMAC value[63:32] */ +#define BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 /* Boot Image CMAC value[95:64] */ +#define BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 /* Boot Image CMAC value[127:96] */ + +/*************************************************************************** + *SCRUB_ENABLE - Secure Sequencer Enable + ***************************************************************************/ +/* SCRUB_CTRL :: SCRUB_ENABLE :: DSCRAM_EN [01:01] */ +#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT 1 + +/* SCRUB_CTRL :: SCRUB_ENABLE :: SCRUB_EN [00:00] */ +#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT 0 + +/*************************************************************************** + *BORCH_END_ADDRESS - ARM Bridge Out-of-Range Checker End Address + ***************************************************************************/ +/* SCRUB_CTRL :: BORCH_END_ADDRESS :: BORCH_END_ADDR [26:00] */ +#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK 0x07ffffff + +#endif /* #ifndef BCHP_SCRUB_CTRL_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_wrap_misc_intr2.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:23p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:21 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:23p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_WRAP_MISC_INTR2_H__ +#define BCHP_WRAP_MISC_INTR2_H__ + +/*************************************************************************** + *WRAP_MISC_INTR2 - MISC block Level 2 Interrupt Controller + ***************************************************************************/ +#define BCHP_WRAP_MISC_INTR2_CPU_STATUS 0x000f2000 /* CPU interrupt Status Register */ +#define BCHP_WRAP_MISC_INTR2_PCI_STATUS 0x000f2018 /* PCI interrupt Status Register */ +#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR 0x000f2020 /* PCI interrupt Clear Register */ + +/*************************************************************************** + *CPU_STATUS - CPU interrupt Status Register + ***************************************************************************/ +/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ +#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 + +/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_DONE_INTR [22:22] */ +#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 + +/* WRAP_MISC_INTR2 :: CPU_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ +#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 + +/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_ERR_INTR [04:04] */ +#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT 4 + +#endif /* #ifndef BCHP_WRAP_MISC_INTR2_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_armcr4_bridge.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:28p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:56 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:28p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_ARMCR4_BRIDGE_H__ +#define BCHP_ARMCR4_BRIDGE_H__ + +/*************************************************************************** + *ARMCR4_BRIDGE - ARM Cortex R4 Bridge control registers + ***************************************************************************/ +#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID 0x000e0000 /* ARM Cortex R4 bridge revision ID */ +#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL 0x000e0004 /* Bridge interface and buffer configuration + */ +#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL 0x000e0008 /* ARM core configuration */ +#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS 0x000e0014 /* Bridge interface and buffer status */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 0x000e0018 /* PCI mailbox #1 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 0x000e001c /* ARM mailbox #1 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 0x000e0020 /* PCI mailbox #2 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 0x000e0024 /* ARM mailbox #2 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 0x000e0028 /* PCI mailbox #3 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 0x000e002c /* ARM mailbox #3 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4 0x000e0030 /* PCI mailbox #4 */ +#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4 0x000e0034 /* ARM mailbox #4 */ +#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1 0x000e0038 /* CPU semaphore #1 */ +#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2 0x000e003c /* CPU semaphore #2 */ +#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3 0x000e0040 /* CPU semaphore #3 */ +#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4 0x000e0044 /* CPU semaphore #4 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 0x000e0048 /* CPU scratchpad #1 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2 0x000e004c /* CPU scratchpad #2 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3 0x000e0050 /* CPU scratchpad #3 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4 0x000e0054 /* CPU scratchpad #4 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 0x000e0058 /* CPU scratchpad #5 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6 0x000e005c /* CPU scratchpad #6 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7 0x000e0060 /* CPU scratchpad #7 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 0x000e0064 /* CPU scratchpad #8 */ +#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 0x000e0068 /* CPU scratchpad #9 */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG 0x000e006c /* Performance monitor configuration */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT 0x000e0070 /* Performance monitor count threshold */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT 0x000e0074 /* Counts the number of merge buffer updates (hits + misses) */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS 0x000e0078 /* Counts the number of merge buffer misses */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT 0x000e007c /* Counts the number of prefetch buffer accesses (hits + misses) */ +#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS 0x000e0080 /* Counts the number of prefetch buffer misses */ +#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1 0x000e0084 /* ARM memory TM1 control register */ +#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2 0x000e0088 /* ARM memory TM2 control register */ +#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3 0x000e008c /* ARM memory TM3 control register */ +#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS 0x000e0090 /* Fifo Status */ +#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS 0x000e0094 /* Bridge Out-of-range Checker Status */ +#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4 0x000e0098 /* ARM memory TM4 control register */ + + +/*************************************************************************** + *REG_BRIDGE_CTL - Bridge interface and buffer configuration + ***************************************************************************/ +/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: arm_run_request [01:01] */ +#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT 1 + +#endif /* #ifndef BCHP_ARMCR4_BRIDGE_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_intr.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:09p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:44 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:09p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_INTR_H__ +#define BCHP_INTR_H__ + +/*************************************************************************** + *INTR - TGT L2 Interrupt Controller Registers + ***************************************************************************/ +#define BCHP_INTR_INTR_STATUS 0x00500700 /* Interrupt Status Register */ +#define BCHP_INTR_INTR_CLR_REG 0x00500708 /* Interrupt Clear Register */ +#define BCHP_INTR_INTR_MSK_SET_REG 0x00500710 /* Interrupt Mask Set Register */ +#define BCHP_INTR_INTR_MSK_CLR_REG 0x00500714 /* Interrupt Mask Clear Register */ +#define BCHP_INTR_EOI_CTRL 0x00500718 /* End of interrupt control register */ + + +#endif /* #ifndef BCHP_INTR_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_pri_arb_control_regs.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:14p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:12 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:14p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ +#define BCHP_PRI_ARB_CONTROL_REGS_H__ + +/*************************************************************************** + *PRI_ARB_CONTROL_REGS - PRIMARY_ARB control registers + ***************************************************************************/ +#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0 0x0040cb00 /* Refresh client control for ddr interface #0 */ +#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL 0x0040cb30 /* Master Control */ + +/*************************************************************************** + *REFRESH_CTL_0 - Refresh client control for ddr interface #0 + ***************************************************************************/ +/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: enable [12:12] */ +#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK 0x00001000 + +/*************************************************************************** + *MASTER_CTL - Master Control + ***************************************************************************/ +/* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: arb_disable [00:00] */ +#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable 0 +#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable 1 + +#endif /* #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_ddr23_ctl_regs_0.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 7:59p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:08 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h $ + * + * Hydra_Software_Devel/1 7/17/09 7:59p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_DDR23_CTL_REGS_0_H__ +#define BCHP_DDR23_CTL_REGS_0_H__ + +/*************************************************************************** + *DDR23_CTL_REGS_0 - DDR23 controller registers + ***************************************************************************/ +#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS 0x01800004 /* DDR23 Controller status register */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1 0x01800010 /* DDR23 Controller Configuration Set #1 */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2 0x01800014 /* DDR23 Controller Configuration Set #2 */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3 0x01800018 /* DDR23 Controller Configuration Set #3 */ +#define BCHP_DDR23_CTL_REGS_0_REFRESH 0x0180001c /* DDR23 Controller Automated Refresh Configuration */ +#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD 0x01800020 /* Host Initiated Refresh Control */ +#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD 0x01800024 /* Host Initiated Precharge Control */ +#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD 0x01800028 /* Host Initiated Load Mode Control */ +#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD 0x0180002c /* Host Initiated Load Extended Mode Control */ +#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD 0x01800030 /* Host Initiated Load Extended Mode #2 Control */ +#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD 0x01800034 /* Host Initiated Load Extended Mode #3 Control */ +#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE 0x01800038 /* Host Initiated ZQ Calibration Cycle */ +#define BCHP_DDR23_CTL_REGS_0_LATENCY 0x01800040 /* DDR2 Controller Access Latency Control */ +#define BCHP_DDR23_CTL_REGS_0_SCRATCH 0x01800058 /* Scratch Register */ +#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL 0x018000f0 /* RAM Macro TM Control */ + +/*************************************************************************** + *CTL_STATUS - DDR23 Controller status register + ***************************************************************************/ +/* DDR23_CTL_REGS_0 :: CTL_STATUS :: clke [01:01] */ +#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK 0x00000002 + +/* DDR23_CTL_REGS_0 :: CTL_STATUS :: idle [00:00] */ +#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK 0x00000001 + +/*************************************************************************** + *PARAMS1 - DDR23 Controller Configuration Set #1 + ***************************************************************************/ +/* DDR23_CTL_REGS_0 :: PARAMS1 :: trtp [31:28] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_MASK 0xf0000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_SHIFT 28 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: twl [27:24] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_MASK 0x0f000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_SHIFT 24 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: tcas [23:20] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_MASK 0x00f00000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_SHIFT 20 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: twtr [19:16] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_MASK 0x000f0000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_SHIFT 16 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: twr [15:12] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_MASK 0x0000f000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_SHIFT 12 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: trrd [11:08] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_MASK 0x00000f00 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_SHIFT 8 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: trp [07:04] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_MASK 0x000000f0 +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_SHIFT 4 + +/* DDR23_CTL_REGS_0 :: PARAMS1 :: trcd [03:00] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_MASK 0x0000000f +#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_SHIFT 0 + +/*************************************************************************** + *PARAMS2 - DDR23 Controller Configuration Set #2 + ***************************************************************************/ +/* DDR23_CTL_REGS_0 :: PARAMS2 :: auto_idle [31:31] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_MASK 0x80000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_SHIFT 31 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: row_bits [30:30] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_MASK 0x40000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_SHIFT 30 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: use_chr_hgt [29:29] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_MASK 0x20000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_SHIFT 29 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: clke [28:28] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK 0x10000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_SHIFT 28 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: sd_col_bits [27:26] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_MASK 0x0c000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_SHIFT 26 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: il_sel [25:25] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_MASK 0x02000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_SHIFT 25 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: dis_itlv [24:24] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_MASK 0x01000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_SHIFT 24 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: reserved0 [23:23] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_MASK 0x00800000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_SHIFT 23 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: cs0_only [22:22] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_MASK 0x00400000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_SHIFT 22 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: allow_pictmem_rd [21:21] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_MASK 0x00200000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_SHIFT 21 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: bank_bits [20:20] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_MASK 0x00100000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_SHIFT 20 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: trfc [19:12] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_MASK 0x000ff000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_SHIFT 12 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: tfaw [11:06] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_MASK 0x00000fc0 +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_SHIFT 6 + +/* DDR23_CTL_REGS_0 :: PARAMS2 :: tras [05:00] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_MASK 0x0000003f +#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_SHIFT 0 + +/*************************************************************************** + *PARAMS3 - DDR23 Controller Configuration Set #3 + ***************************************************************************/ +/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr3_reset [31:31] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_MASK 0x80000000 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_SHIFT 31 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved0 [30:06] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_MASK 0x7fffffc0 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_SHIFT 6 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr_bl [05:05] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_MASK 0x00000020 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_SHIFT 5 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: cmd_2t [04:04] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_MASK 0x00000010 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_SHIFT 4 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_mode [03:03] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_MASK 0x00000008 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_SHIFT 3 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_te_adj [02:02] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_MASK 0x00000004 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_SHIFT 2 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_le_adj [01:01] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_MASK 0x00000002 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_SHIFT 1 + +/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_en [00:00] */ +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK 0x00000001 +#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_SHIFT 0 + +/*************************************************************************** + *UPDATE_VDL - RAM Macro TM Control + ***************************************************************************/ +/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: refresh [00:00] */ +#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK 0x00000001 + + +#endif /* #ifndef BCHP_DDR23_CTL_REGS_0_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_ddr23_phy_byte_lane_0.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 7:59p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:18 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h $ + * + * Hydra_Software_Devel/1 7/17/09 7:59p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ +#define BCHP_DDR23_PHY_BYTE_LANE_0_H__ + +/*************************************************************************** + *DDR23_PHY_BYTE_LANE_0 - DDR23 DDR23 byte lane #0 control registers + ***************************************************************************/ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE 0x01801204 /* Byte lane VDL calibration control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS 0x01801208 /* Byte lane VDL calibration status register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x01801210 /* Read DQSP VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x01801214 /* Read DQSN VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x01801218 /* Read Enable VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x0180121c /* Write data and mask VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL 0x01801230 /* Byte Lane read channel control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x0180123c /* Idle mode SSTL pad control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x01801240 /* SSTL pad drive characteristics control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x01801248 /* Write cycle preamble control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x0180124c /* Clock Regulator control register */ + +/*************************************************************************** + *READ_CONTROL - Byte Lane read channel control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK 0x00000300 +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT 8 + +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK 0x00000008 +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT 3 + +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK 0x00000004 +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT 2 + +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 + +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 +#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 + +/*************************************************************************** + *IDLE_PAD_CONTROL - Idle mode SSTL pad control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK 0x80000000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 + +/*************************************************************************** + *DRIVE_PAD_CTL - SSTL pad drive characteristics control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 + +/*************************************************************************** + *CLOCK_REG_CONTROL - Clock Regulator control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 + +#endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_ddr23_phy_byte_lane_1.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 7:59p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:17 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h $ + * + * Hydra_Software_Devel/1 7/17/09 7:59p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ +#define BCHP_DDR23_PHY_BYTE_LANE_1_H__ + +/*************************************************************************** + *DDR23_PHY_BYTE_LANE_1 - DDR23 DDR23 byte lane #1 control registers + ***************************************************************************/ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE 0x01801104 /* Byte lane VDL calibration control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS 0x01801108 /* Byte lane VDL calibration status register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x01801110 /* Read DQSP VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x01801114 /* Read DQSN VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x01801118 /* Read Enable VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x0180111c /* Write data and mask VDL static override control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL 0x01801130 /* Byte Lane read channel control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x0180113c /* Idle mode SSTL pad control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x01801140 /* SSTL pad drive characteristics control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x01801144 /* Clock pad disable register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x01801148 /* Write cycle preamble control register */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x0180114c /* Clock Regulator control register */ + +/*************************************************************************** + *READ_CONTROL - Byte Lane read channel control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK 0x00000008 + +/*************************************************************************** + *IDLE_PAD_CONTROL - Idle mode SSTL pad control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK 0x80000000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 + +/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 + +/*************************************************************************** + *DRIVE_PAD_CTL - SSTL pad drive characteristics control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 6 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_SHIFT 4 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 + +/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_MASK 0x00000001 +#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_SHIFT 0 + +/*************************************************************************** + *CLOCK_PAD_DISABLE - Clock pad disable register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 + +/*************************************************************************** + *CLOCK_REG_CONTROL - Clock Regulator control register + ***************************************************************************/ +/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ +#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 + +#endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_ddr23_phy_control_regs.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 7:59p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:21 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h $ + * + * Hydra_Software_Devel/1 7/17/09 7:59p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ +#define BCHP_DDR23_PHY_CONTROL_REGS_H__ + +/*************************************************************************** + *DDR23_PHY_CONTROL_REGS - DDR23 DDR23 physical interface control registers + ***************************************************************************/ +#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL 0x01801004 /* PHY clock power management control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS 0x01801010 /* PHY PLL status register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG 0x01801014 /* PHY PLL configuration register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x01801018 /* PHY PLL pre-divider control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER 0x0180101c /* PHY PLL divider control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x01801030 /* Address & Control VDL static override control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x01801038 /* Idle mode SSTL pad control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x0180103c /* PVT Compensation control and status register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x01801040 /* SSTL pad drive characteristics control register */ +#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x01801044 /* Clock Regulator control register */ + +/*************************************************************************** + *CLK_PM_CTRL - PHY clock power management control register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 + +/*************************************************************************** + *PLL_CONFIG - PHY PLL configuration register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ENB_CLKOUT [04:04] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK 0x00000010 + +/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 + +/*************************************************************************** + *IDLE_PAD_CONTROL - Idle mode SSTL pad control register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK 0x80000000 + +/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK 0x00000100 + +/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040 + +/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002 + +/*************************************************************************** + *DRIVE_PAD_CTL - SSTL pad drive characteristics control register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:05] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xffffffe0 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 5 + +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [04:04] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_SHIFT 4 + +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 + +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 + +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 + +/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: slew [00:00] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_MASK 0x00000001 +#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_SHIFT 0 + +/*************************************************************************** + *ZQ_PVT_COMP_CTL - PVT Compensation control and status register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK 0x10000000 + +/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK 0x04000000 + +/*************************************************************************** + *CLOCK_REG_CONTROL - Clock Regulator control register + ***************************************************************************/ +/* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ +#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 + +#endif /* #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_clk.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 7:58p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:39 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h $ + * + * Hydra_Software_Devel/1 7/17/09 7:58p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_CLK_H__ +#define BCHP_CLK_H__ + +/*************************************************************************** + *CLK - CLOCK_GEN Registers + ***************************************************************************/ +#define BCHP_CLK_PM_CTRL 0x00070004 /* Software power management control to turn off clocks */ +#define BCHP_CLK_TEMP_MON_CTRL 0x00070040 /* Temperature monitor control. */ +#define BCHP_CLK_TEMP_MON_STATUS 0x00070044 /* Temperature monitor status. */ +#define BCHP_CLK_PLL0_ARM_DIV 0x00070110 /* Main PLL0 channel 3 ARM clock divider settings */ +#define BCHP_CLK_PLL1_CTRL 0x00070120 /* Main PLL1 reset, enable, powerdown, and control */ + +/*************************************************************************** + *PM_CTRL - Software power management control to turn off clocks + ***************************************************************************/ +/* CLK :: PM_CTRL :: DIS_SUN_27_LOW_PWR [25:25] */ +#define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK 0x02000000 + +/* CLK :: PM_CTRL :: DIS_SUN_108_LOW_PWR [24:24] */ +#define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK 0x01000000 + +/* CLK :: PM_CTRL :: DIS_MISC_OTP_9_CLK [19:19] */ +#define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK 0x00080000 + +/* CLK :: PM_CTRL :: DIS_ARM_CLK [18:18] */ +#define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK 0x00040000 + +/* CLK :: PM_CTRL :: DIS_AVD_CLK [17:17] */ +#define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK 0x00020000 + +/* CLK :: PM_CTRL :: DIS_BLINK_108_CLK [12:12] */ +#define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK 0x00001000 + +/* CLK :: PM_CTRL :: DIS_DDR_108_CLK [11:11] */ +#define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK 0x00000800 + +/* CLK :: PM_CTRL :: DIS_AVD_108_CLK [10:10] */ +#define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK 0x00000400 + +/* CLK :: PM_CTRL :: DIS_MISC_108_CLK [09:09] */ +#define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK 0x00000200 + +/* CLK :: PM_CTRL :: DIS_BLINK_216_CLK [04:04] */ +#define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK 0x00000010 + +/* CLK :: PM_CTRL :: DIS_DDR_216_CLK [03:03] */ +#define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK 0x00000008 + +/* CLK :: PM_CTRL :: DIS_AVD_216_CLK [02:02] */ +#define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK 0x00000004 + +/* CLK :: PM_CTRL :: DIS_MISC_216_CLK [01:01] */ +#define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK 0x00000002 + +/* CLK :: PM_CTRL :: DIS_SUN_216_CLK [00:00] */ +#define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK 0x00000001 + +/*************************************************************************** + *PLL1_CTRL - Main PLL1 reset, enable, powerdown, and control + ***************************************************************************/ +/* CLK :: PLL1_CTRL :: POWERDOWN [03:03] */ +#define BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK 0x00000008 + +#endif /* #ifndef BCHP_CLK_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_pcie_tl.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:13p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:28 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:13p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_PCIE_TL_H__ +#define BCHP_PCIE_TL_H__ + +/*************************************************************************** + *PCIE_TL - PCIE TL related registers + ***************************************************************************/ +#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION 0x00500404 /* TRANSACTION_CONFIGURATION Register */ + +#endif /* #ifndef BCHP_PCIE_TL_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_sun_gisb_arb.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:19p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:30 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:19p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_SUN_GISB_ARB_H__ +#define BCHP_SUN_GISB_ARB_H__ + +/*************************************************************************** + *SUN_GISB_ARB - GISB Arbiter registers + ***************************************************************************/ +#define BCHP_SUN_GISB_ARB_TIMER 0x0040000c /* GISB ARBITER Timer Value Register */ + +#endif /* #ifndef BCHP_SUN_GISB_ARB_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_misc_perst.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:12p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:23 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:12p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_MISC_PERST_H__ +#define BCHP_MISC_PERST_H__ + +/*************************************************************************** + *MISC_PERST - Registers for Link reset on PERST_N + ***************************************************************************/ +#define BCHP_MISC_PERST_CLOCK_CTRL 0x0050229c /* Clock Control Register */ + +/*************************************************************************** + *CLOCK_CTRL - Clock Control Register + ***************************************************************************/ +/* MISC_PERST :: CLOCK_CTRL :: EARLY_L1_EXIT [02:02] */ +#define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK 0x00000004 + +#endif /* #ifndef BCHP_MISC_PERST_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_sun_top_ctrl.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:20p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:43:07 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:20p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_SUN_TOP_CTRL_H__ +#define BCHP_SUN_TOP_CTRL_H__ + +/*************************************************************************** + *SUN_TOP_CTRL - Top Control registers + ***************************************************************************/ +#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ + +#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_gio.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:07p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:13 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:07p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_GIO_H__ +#define BCHP_GIO_H__ + +/*************************************************************************** + *GIO - GPIO + ***************************************************************************/ +#define BCHP_GIO_DATA_LO 0x00406004 /* GENERAL PURPOSE I/O DATA [31:0] */ +#define BCHP_GIO_IODIR_LO 0x00406008 /* GENERAL PURPOSE I/O DIRECTION [31:0] */ + +#endif /* #ifndef BCHP_GIO_H__ */ + +/*************************************************************************** + * + * $brcm_Workfile: bchp_pri_client_regs.h $ + * $brcm_Revision: Hydra_Software_Devel/1 $ + * $brcm_Date: 7/17/09 8:16p $ + * + * Module Description: + * DO NOT EDIT THIS FILE DIRECTLY + * + * This module was generated magically with RDB from a source description + * file. You must edit the source file for changes to be made to this file. + * + * + * Date: Generated on Fri Jul 17 19:42:12 2009 + * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 + * + * Compiled with: RDB Utility combo_header.pl + * RDB Parser 3.0 + * unknown unknown + * Perl Interpreter 5.008008 + * Operating System linux + * + * Revision History: + * + * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h $ + * + * Hydra_Software_Devel/1 7/17/09 8:16p albertl + * PR56880: Initial revision. + * + ***************************************************************************/ + +#ifndef BCHP_PRI_CLIENT_REGS_H__ +#define BCHP_PRI_CLIENT_REGS_H__ + +/*************************************************************************** + *PRI_CLIENT_REGS - PRIMARY_ARB_CLIENTS client configuration registers + ***************************************************************************/ +#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT 0x0040c000 /* Arbiter Client DEBLOCK Blockout Counter Register */ +#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL 0x0040c004 /* Arbiter Client DEBLOCK Configuration Register */ + +#endif /* #ifndef BCHP_PRI_CLIENT_REGS_H__ */ --- crystalhd~/crystalhd_cmds.c 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_cmds.c 2015-04-06 20:12:09.000000000 +0300 @@ -4,7 +4,7 @@ * Name: crystalhd_cmds . c * * Description: - * BCM70010 Linux driver user command interfaces. + * BCM70012/BCM70015 Linux driver user command interfaces. * * HISTORY: * @@ -24,7 +24,8 @@ * along with this driver. If not, see . **********************************************************************/ -#include "crystalhd.h" +#include "crystalhd_lnx.h" +#include "crystalhd_hw.h" static struct crystalhd_user *bc_cproc_get_uid(struct crystalhd_cmd *ctx) { @@ -41,7 +42,7 @@ static struct crystalhd_user *bc_cproc_g return user; } -static int bc_cproc_get_user_count(struct crystalhd_cmd *ctx) +int bc_get_userhandle_count(struct crystalhd_cmd *ctx) { int i, count = 0; @@ -53,68 +54,77 @@ static int bc_cproc_get_user_count(struc return count; } -static void bc_cproc_mark_pwr_state(struct crystalhd_cmd *ctx) +static void bc_cproc_mark_pwr_state(struct crystalhd_cmd *ctx, uint32_t state) { int i; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { if (!ctx->user[i].in_use) continue; - if (ctx->user[i].mode == DTS_DIAG_MODE || - ctx->user[i].mode == DTS_PLAYBACK_MODE) { - ctx->pwr_state_change = 1; + if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || + (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { + ctx->pwr_state_change = state; break; } } } -static enum BC_STATUS bc_cproc_notify_mode(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_notify_mode(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { + struct device *dev = chddev(); int rc = 0, i = 0; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->user[idata->u_id].mode != DTS_MODE_INV) { - BCMLOG_ERR("Close the handle first..\n"); + dev_err(dev, "Close the handle first..\n"); return BC_STS_ERR_USAGE; } - if (idata->udata.u.NotifyMode.Mode == DTS_MONITOR_MODE) { + + if ((idata->udata.u.NotifyMode.Mode && 0xFF) == DTS_MONITOR_MODE) { ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; return BC_STS_SUCCESS; } + if (ctx->state != BC_LINK_INVALID) { - BCMLOG_ERR("Link invalid state %d\n", ctx->state); + dev_err(dev, "Link invalid state notify mode %x \n", ctx->state); return BC_STS_ERR_USAGE; } + /* Check for duplicate playback sessions..*/ for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - if (ctx->user[i].mode == DTS_DIAG_MODE || - ctx->user[i].mode == DTS_PLAYBACK_MODE) { - BCMLOG_ERR("multiple playback sessions are not supported..\n"); + if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || + (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { + dev_err(dev, "multiple playback sessions are not " + "supported..\n"); return BC_STS_ERR_USAGE; } } ctx->cin_wait_exit = 0; + ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; + /* Create list pools */ + rc = crystalhd_create_elem_pool(ctx->adp, BC_LINK_ELEM_POOL_SZ); + if (rc) + return BC_STS_ERROR; /* Setup mmap pool for uaddr sgl mapping..*/ rc = crystalhd_create_dio_pool(ctx->adp, BC_LINK_MAX_SGLS); if (rc) return BC_STS_ERROR; /* Setup Hardware DMA rings */ - return crystalhd_hw_setup_dma_rings(&ctx->hw_ctx); + return crystalhd_hw_setup_dma_rings(ctx->hw_ctx); } -static enum BC_STATUS bc_cproc_get_version(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_get_version(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } idata->udata.u.VerInfo.DriverMajor = crystalhd_kmod_major; @@ -124,11 +134,10 @@ static enum BC_STATUS bc_cproc_get_versi } -static enum BC_STATUS bc_cproc_get_hwtype(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_get_hwtype(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } @@ -142,94 +151,94 @@ static enum BC_STATUS bc_cproc_get_hwtyp return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_reg_rd(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_reg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; - idata->udata.u.regAcc.Value = bc_dec_reg_rd(ctx->adp, + idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadDevRegister(ctx->adp, idata->udata.u.regAcc.Offset); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_reg_wr(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_reg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; - bc_dec_reg_wr(ctx->adp, idata->udata.u.regAcc.Offset, + ctx->hw_ctx->pfnWriteDevRegister(ctx->adp, idata->udata.u.regAcc.Offset, idata->udata.u.regAcc.Value); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_link_reg_rd(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_link_reg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; - idata->udata.u.regAcc.Value = crystalhd_reg_rd(ctx->adp, + idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadFPGARegister(ctx->adp, idata->udata.u.regAcc.Offset); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_link_reg_wr(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_link_reg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; - crystalhd_reg_wr(ctx->adp, idata->udata.u.regAcc.Offset, + ctx->hw_ctx->pfnWriteFPGARegister(ctx->adp, idata->udata.u.regAcc.Offset, idata->udata.u.regAcc.Value); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_mem_rd(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_mem_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata || !idata->add_cdata) return BC_STS_INV_ARG; if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { - BCMLOG_ERR("insufficient buffer\n"); + dev_err(chddev(), "insufficient buffer\n"); return BC_STS_INV_ARG; } - sts = crystalhd_mem_rd(ctx->adp, idata->udata.u.devMem.StartOff, + sts = ctx->hw_ctx->pfnDevDRAMRead(ctx->hw_ctx, idata->udata.u.devMem.StartOff, idata->udata.u.devMem.NumDwords, (uint32_t *)idata->add_cdata); return sts; } -static enum BC_STATUS bc_cproc_mem_wr(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_mem_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata || !idata->add_cdata) return BC_STS_INV_ARG; if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { - BCMLOG_ERR("insufficient buffer\n"); + dev_err(chddev(), "insufficient buffer\n"); return BC_STS_INV_ARG; } - sts = crystalhd_mem_wr(ctx->adp, idata->udata.u.devMem.StartOff, + sts = ctx->hw_ctx->pfnDevDRAMWrite(ctx->hw_ctx, idata->udata.u.devMem.StartOff, idata->udata.u.devMem.NumDwords, (uint32_t *)idata->add_cdata); return sts; } -static enum BC_STATUS bc_cproc_cfg_rd(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_cfg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { uint32_t ix, cnt, off, len; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; uint32_t *temp; if (!ctx || !idata) @@ -239,8 +248,10 @@ static enum BC_STATUS bc_cproc_cfg_rd(st off = idata->udata.u.pciCfg.Offset; len = idata->udata.u.pciCfg.Size; - if (len <= 4) - return crystalhd_pci_cfg_rd(ctx->adp, off, len, temp); + if (len <= 4) { + sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, temp); + return sts; + } /* Truncate to dword alignment..*/ len = 4; @@ -248,7 +259,7 @@ static enum BC_STATUS bc_cproc_cfg_rd(st for (ix = 0; ix < cnt; ix++) { sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, &temp[ix]); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("config read : %d\n", sts); + dev_err(chddev(), "config read : %d\n", sts); return sts; } off += len; @@ -257,11 +268,11 @@ static enum BC_STATUS bc_cproc_cfg_rd(st return sts; } -static enum BC_STATUS bc_cproc_cfg_wr(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_cfg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { uint32_t ix, cnt, off, len; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; uint32_t *temp; if (!ctx || !idata) @@ -280,7 +291,7 @@ static enum BC_STATUS bc_cproc_cfg_wr(st for (ix = 0; ix < cnt; ix++) { sts = crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[ix]); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("config write : %d\n", sts); + dev_err(chddev(), "config write : %d\n", sts); return sts; } off += len; @@ -289,29 +300,34 @@ static enum BC_STATUS bc_cproc_cfg_wr(st return sts; } -static enum BC_STATUS bc_cproc_download_fw(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_download_fw(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; + + dev_dbg(chddev(), "Downloading FW\n"); if (!ctx || !idata || !idata->add_cdata || !idata->add_cdata_sz) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } - if (ctx->state != BC_LINK_INVALID) { - BCMLOG_ERR("Link invalid state %d\n", ctx->state); + if ((ctx->state != BC_LINK_INVALID) && (ctx->state != BC_LINK_RESUME)) { + dev_dbg(chddev(), "Link invalid state download fw %x \n", ctx->state); return BC_STS_ERR_USAGE; } - sts = crystalhd_download_fw(ctx->adp, (uint8_t *)idata->add_cdata, + sts = ctx->hw_ctx->pfnFWDwnld(ctx->hw_ctx, (uint8_t *)idata->add_cdata, idata->add_cdata_sz); - if (sts != BC_STS_SUCCESS) - BCMLOG_ERR("Firmware Download Failure!! - %d\n", sts); - else + if (sts != BC_STS_SUCCESS) { + dev_info(chddev(), "Firmware Download Failure!! - %d\n", sts); + } else ctx->state |= BC_LINK_INIT; + ctx->pwr_state_change = BC_HW_RUNNING; + + ctx->hw_ctx->FwCmdCnt = 0; return sts; } @@ -328,14 +344,14 @@ static enum BC_STATUS bc_cproc_download_ * Abort pending input transfers and issue decoder flush command. * */ -static enum BC_STATUS bc_cproc_do_fw_cmd(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_do_fw_cmd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { - enum BC_STATUS sts; + struct device *dev = chddev(); + BC_STATUS sts; uint32_t *cmd; if (!(ctx->state & BC_LINK_INIT)) { - BCMLOG_ERR("Link invalid state %d\n", ctx->state); + dev_dbg(dev, "Link invalid state do fw cmd %x \n", ctx->state); return BC_STS_ERR_USAGE; } @@ -345,18 +361,18 @@ static enum BC_STATUS bc_cproc_do_fw_cmd if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { if (!cmd[3]) { ctx->state &= ~BC_LINK_PAUSED; - crystalhd_hw_unpause(&ctx->hw_ctx); + ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, false); } } else if (cmd[0] == eCMD_C011_DEC_CHAN_FLUSH) { - BCMLOG(BCMLOG_INFO, "Flush issued\n"); + dev_dbg(dev, "Flush issued\n"); if (cmd[3]) ctx->cin_wait_exit = 1; } - sts = crystalhd_do_fw_cmd(&ctx->hw_ctx, &idata->udata.u.fwCmd); + sts = ctx->hw_ctx->pfnDoFirmwareCmd(ctx->hw_ctx, &idata->udata.u.fwCmd); if (sts != BC_STS_SUCCESS) { - BCMLOG(BCMLOG_INFO, "fw cmd %x failed\n", cmd[0]); + dev_dbg(dev, "fw cmd %x failed\n", cmd[0]); return sts; } @@ -364,7 +380,7 @@ static enum BC_STATUS bc_cproc_do_fw_cmd if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { if (cmd[3]) { ctx->state |= BC_LINK_PAUSED; - crystalhd_hw_pause(&ctx->hw_ctx); + ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, true); } } @@ -372,51 +388,52 @@ static enum BC_STATUS bc_cproc_do_fw_cmd } static void bc_proc_in_completion(struct crystalhd_dio_req *dio_hnd, - wait_queue_head_t *event, enum BC_STATUS sts) + wait_queue_head_t *event, BC_STATUS sts) { if (!dio_hnd || !event) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "%s: Invalid Arg\n", __func__); return; } - if (sts == BC_STS_IO_USER_ABORT) - return; + if (sts == BC_STS_IO_USER_ABORT || sts == BC_STS_PWR_MGMT) + return; dio_hnd->uinfo.comp_sts = sts; dio_hnd->uinfo.ev_sts = 1; crystalhd_set_event(event); } -static enum BC_STATUS bc_cproc_codein_sleep(struct crystalhd_cmd *ctx) +static BC_STATUS bc_cproc_codein_sleep(struct crystalhd_cmd *ctx) { wait_queue_head_t sleep_ev; int rc = 0; if (ctx->state & BC_LINK_SUSPEND) - return BC_STS_IO_USER_ABORT; + return BC_STS_PWR_MGMT; if (ctx->cin_wait_exit) { ctx->cin_wait_exit = 0; return BC_STS_CMD_CANCELLED; } crystalhd_create_event(&sleep_ev); - crystalhd_wait_on_event(&sleep_ev, 0, 100, rc, 0); + crystalhd_wait_on_event(&sleep_ev, 0, 100, rc, false); if (rc == -EINTR) return BC_STS_IO_USER_ABORT; return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata, +static BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata, struct crystalhd_dio_req *dio) { + struct device *dev = chddev(); uint32_t tx_listid = 0; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; wait_queue_head_t event; int rc = 0; if (!ctx || !idata || !dio) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } @@ -424,7 +441,7 @@ static enum BC_STATUS bc_cproc_hw_txdma( ctx->tx_list_id = 0; /* msleep_interruptible(2000); */ - sts = crystalhd_hw_post_tx(&ctx->hw_ctx, dio, bc_proc_in_completion, + sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, bc_proc_in_completion, &event, &tx_listid, idata->udata.u.ProcInput.Encrypted); @@ -432,13 +449,13 @@ static enum BC_STATUS bc_cproc_hw_txdma( sts = bc_cproc_codein_sleep(ctx); if (sts != BC_STS_SUCCESS) break; - sts = crystalhd_hw_post_tx(&ctx->hw_ctx, dio, + sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, bc_proc_in_completion, &event, &tx_listid, idata->udata.u.ProcInput.Encrypted); } if (sts != BC_STS_SUCCESS) { - BCMLOG(BCMLOG_DBG, "_hw_txdma returning sts:%d\n", sts); + dev_dbg(dev, "_hw_txdma returning sts:%d\n", sts); return sts; } if (ctx->cin_wait_exit) @@ -446,16 +463,18 @@ static enum BC_STATUS bc_cproc_hw_txdma( ctx->tx_list_id = tx_listid; + dev_dbg(dev, "Sending TX\n"); + /* _post() succeeded.. wait for the completion. */ - crystalhd_wait_on_event(&event, (dio->uinfo.ev_sts), 3000, rc, 0); + crystalhd_wait_on_event(&event, (dio->uinfo.ev_sts), 3000, rc, false); ctx->tx_list_id = 0; if (!rc) { return dio->uinfo.comp_sts; } else if (rc == -EBUSY) { - BCMLOG(BCMLOG_DBG, "_tx_post() T/O\n"); + dev_dbg(dev, "_tx_post() T/O \n"); sts = BC_STS_TIMEOUT; } else if (rc == -EINTR) { - BCMLOG(BCMLOG_DBG, "Tx Wait Signal int.\n"); + dev_dbg(dev, "Tx Wait Signal int.\n"); sts = BC_STS_IO_USER_ABORT; } else { sts = BC_STS_IO_ERROR; @@ -465,57 +484,62 @@ static enum BC_STATUS bc_cproc_hw_txdma( * so no need to wait on the event again.. the return itself * ensures the release of our resources. */ - crystalhd_hw_cancel_tx(&ctx->hw_ctx, tx_listid); + crystalhd_hw_cancel_tx(ctx->hw_ctx, tx_listid); return sts; } /* Helper function to check on user buffers */ -static enum BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, - uint32_t ub_sz, uint32_t uv_off, bool en_422) +static BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_sz, + uint32_t uv_off, bool en_422) { + struct device *dev = chddev(); if (!ubuff || !ub_sz) { - BCMLOG_ERR("%s->Invalid Arg %p %x\n", + dev_err(dev, "%s->Invalid Arg %p %x\n", ((pin) ? "TX" : "RX"), ubuff, ub_sz); return BC_STS_INV_ARG; } /* Check for alignment */ if (((uintptr_t)ubuff) & 0x03) { - BCMLOG_ERR( - "%s-->Un-aligned address not implemented yet.. %p\n", - ((pin) ? "TX" : "RX"), ubuff); + dev_err(dev, "%s-->Un-aligned address not implemented yet.. %p \n", + ((pin) ? "TX" : "RX"), ubuff); return BC_STS_NOT_IMPL; } if (pin) return BC_STS_SUCCESS; if (!en_422 && !uv_off) { - BCMLOG_ERR("Need UV offset for 420 mode.\n"); + dev_err(dev, "Need UV offset for 420 mode.\n"); return BC_STS_INV_ARG; } if (en_422 && uv_off) { - BCMLOG_ERR("UV offset in 422 mode ??\n"); + dev_err(dev, "UV offset in 422 mode ??\n"); return BC_STS_INV_ARG; } return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_proc_input(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_proc_input(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { + struct device *dev = chddev(); void *ubuff; uint32_t ub_sz; struct crystalhd_dio_req *dio_hnd = NULL; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } + if (ctx->state & BC_LINK_SUSPEND) { + dev_err(dev, "proc_input: Link Suspended\n"); + return BC_STS_PWR_MGMT; + } + ubuff = idata->udata.u.ProcInput.pDmaBuff; ub_sz = idata->udata.u.ProcInput.BuffSz; @@ -525,7 +549,7 @@ static enum BC_STATUS bc_cproc_proc_inpu sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, 0, 0, 1, &dio_hnd); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("dio map - %d\n", sts); + dev_err(dev, "dio map - %d \n", sts); return sts; } @@ -539,17 +563,18 @@ static enum BC_STATUS bc_cproc_proc_inpu return sts; } -static enum BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { + struct device *dev = chddev(); void *ubuff; uint32_t ub_sz, uv_off; bool en_422; struct crystalhd_dio_req *dio_hnd = NULL; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } @@ -559,21 +584,21 @@ static enum BC_STATUS bc_cproc_add_cap_b en_422 = idata->udata.u.RxBuffs.b422Mode; sts = bc_cproc_check_inbuffs(0, ubuff, ub_sz, uv_off, en_422); + if (sts != BC_STS_SUCCESS) return sts; sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, uv_off, en_422, 0, &dio_hnd); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("dio map - %d\n", sts); + dev_err(dev, "dio map - %d \n", sts); return sts; } if (!dio_hnd) return BC_STS_ERROR; - sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio_hnd, - (ctx->state == BC_LINK_READY)); + sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio_hnd, (ctx->state == BC_LINK_READY)); if ((sts != BC_STS_SUCCESS) && (sts != BC_STS_BUSY)) { crystalhd_unmap_dio(ctx->adp, dio_hnd); return sts; @@ -582,45 +607,50 @@ static enum BC_STATUS bc_cproc_add_cap_b return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_fmt_change(struct crystalhd_cmd *ctx, +static BC_STATUS bc_cproc_fmt_change(struct crystalhd_cmd *ctx, struct crystalhd_dio_req *dio) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; - sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio, 0); + sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio, 0); if (sts != BC_STS_SUCCESS) return sts; ctx->state |= BC_LINK_FMT_CHG; if (ctx->state == BC_LINK_READY) - sts = crystalhd_hw_start_capture(&ctx->hw_ctx); + sts = crystalhd_hw_start_capture(ctx->hw_ctx); return sts; } -static enum BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { + struct device *dev = chddev(); struct crystalhd_dio_req *dio = NULL; - enum BC_STATUS sts = BC_STS_SUCCESS; - struct BC_DEC_OUT_BUFF *frame; + BC_STATUS sts = BC_STS_SUCCESS; + BC_DEC_OUT_BUFF *frame; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } + if (ctx->state & BC_LINK_SUSPEND) + return BC_STS_PWR_MGMT; + if (!(ctx->state & BC_LINK_CAP_EN)) { - BCMLOG(BCMLOG_DBG, "Capture not enabled..%x\n", ctx->state); + dev_dbg(dev, "Capture not enabled..%x\n", ctx->state); return BC_STS_ERR_USAGE; } frame = &idata->udata.u.DecOutData; - sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, &frame->PibInfo, &dio); + sts = crystalhd_hw_get_cap_buffer(ctx->hw_ctx, &frame->PibInfo, &dio); if (sts != BC_STS_SUCCESS) - return (ctx->state & BC_LINK_SUSPEND) ? - BC_STS_IO_USER_ABORT : sts; + return (ctx->state & BC_LINK_SUSPEND) ? BC_STS_PWR_MGMT : sts; + + dev_dbg(dev, "Got Picture\n"); frame->Flags = dio->uinfo.comp_flags; @@ -640,26 +670,43 @@ static enum BC_STATUS bc_cproc_fetch_fra return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_start_capture(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_start_capture(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { ctx->state |= BC_LINK_CAP_EN; + + if( idata->udata.u.RxCap.PauseThsh ) + ctx->hw_ctx->PauseThreshold = idata->udata.u.RxCap.PauseThsh; + else + ctx->hw_ctx->PauseThreshold = HW_PAUSE_THRESHOLD; + + if( idata->udata.u.RxCap.ResumeThsh ) + ctx->hw_ctx->ResumeThreshold = idata->udata.u.RxCap.ResumeThsh; + else + ctx->hw_ctx->ResumeThreshold = HW_RESUME_THRESHOLD; + + printk(KERN_DEBUG "start_capture: pause_th:%d, resume_th:%d\n", ctx->hw_ctx->PauseThreshold, ctx->hw_ctx->ResumeThreshold); + + ctx->hw_ctx->DrvTotalFrmCaptured = 0; + + ctx->hw_ctx->DefaultPauseThreshold = ctx->hw_ctx->PauseThreshold; /* used to restore on FMTCH */ + + ctx->hw_ctx->pfnNotifyHardware(ctx->hw_ctx, BC_EVENT_START_CAPTURE); + if (ctx->state == BC_LINK_READY) - return crystalhd_hw_start_capture(&ctx->hw_ctx); + return crystalhd_hw_start_capture(ctx->hw_ctx); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - struct crystalhd_dio_req *dio = NULL; - enum BC_STATUS sts = BC_STS_SUCCESS; - struct BC_DEC_OUT_BUFF *frame; - uint32_t count; + struct device *dev = chddev(); + struct crystalhd_rx_dma_pkt *rpkt; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } @@ -667,37 +714,43 @@ static enum BC_STATUS bc_cproc_flush_cap return BC_STS_ERR_USAGE; /* We should ack flush even when we are in paused/suspend state */ - if (!(ctx->state & BC_LINK_READY)) - return crystalhd_hw_stop_capture(&ctx->hw_ctx); +/* if (!(ctx->state & BC_LINK_READY)) */ +/* return crystalhd_hw_stop_capture(&ctx->hw_ctx); */ - ctx->state &= ~(BC_LINK_CAP_EN|BC_LINK_FMT_CHG); - - frame = &idata->udata.u.DecOutData; - for (count = 0; count < BC_RX_LIST_CNT; count++) { - - sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, - &frame->PibInfo, &dio); - if (sts != BC_STS_SUCCESS) - break; - - crystalhd_unmap_dio(ctx->adp, dio); + dev_dbg(dev, "number of rx success %u and failure %u\n", ctx->hw_ctx->stats.rx_success, ctx->hw_ctx->stats.rx_errors); + if(idata->udata.u.FlushRxCap.bDiscardOnly) { + /* just flush without unmapping and then resume */ + crystalhd_hw_stop_capture(ctx->hw_ctx, false); + while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_actq)) != NULL) + crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); + + while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_rdyq)) != NULL) + crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); + crystalhd_hw_start_capture(ctx->hw_ctx); + } else { + ctx->state &= ~(BC_LINK_CAP_EN|BC_LINK_FMT_CHG); + crystalhd_hw_stop_capture(ctx->hw_ctx, true); } - return crystalhd_hw_stop_capture(&ctx->hw_ctx); + return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_get_stats(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_get_stats(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - struct BC_DTS_STATS *stats; + BC_DTS_STATS *stats; struct crystalhd_hw_stats hw_stats; + uint32_t pic_width; + uint8_t flags = 0; + bool readTxOnly = false; + unsigned long irqflags; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } - crystalhd_hw_stats(&ctx->hw_ctx, &hw_stats); + crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); stats = &idata->udata.u.drvStat; stats->drvRLL = hw_stats.rdyq_count; @@ -710,63 +763,152 @@ static enum BC_STATUS bc_cproc_get_stats stats->TxFifoBsyCnt = hw_stats.cin_busy; stats->pauseCount = hw_stats.pause_cnt; - if (ctx->pwr_state_change) - stats->pwr_state_change = 1; + /* Indicate that we are checking stats on the input buffer for a single threaded application */ + /* this will prevent the HW from going to low power because we assume that once we have told the application */ + /* that we have space in the HW, the app is going to try to DMA. And if we block that DMA, a single threaded application */ + /* will deadlock */ + if(stats->DrvNextMDataPLD & BC_BIT(31)) + { + flags |= 0x08; + /* Also for single threaded applications, check to see if we have reduced the power down */ + /* pause threshold to too low and increase it if the RLL is close to the threshold */ +/* if(pDrvStat->drvRLL >= pDevExt->pHwExten->PauseThreshold) + pDevExt->pHwExten->PauseThreshold++; + PeekNextTS = TRUE;*/ + } + + /* also indicate that we are just checking stats and not posting */ + /* This allows multi-threaded applications to be placed into low power state */ + /* because eveentually the RX thread will wake up the HW when needed */ + flags |= 0x04; + + stats->pwr_state_change = ctx->pwr_state_change; + if (ctx->state & BC_LINK_PAUSED) stats->DrvPauseTime = 1; + /* use bit 29 of the input status to indicate that we are trying to read VC1 status */ + /* This is important for the BCM70012 which uses a different input queue for VC1 */ + if(stats->DrvcpbEmptySize & BC_BIT(29)) + flags = 0x2; + /* Bit 30 is used to indicate that we are reading only the TX stats and to not touch the Ready list */ + if(stats->DrvcpbEmptySize & BC_BIT(30)) + readTxOnly = true; + + spin_lock_irqsave(&ctx->hw_ctx->lock, irqflags); + ctx->hw_ctx->pfnCheckInputFIFO(ctx->hw_ctx, 0, &stats->DrvcpbEmptySize, + false, &flags); + spin_unlock_irqrestore(&ctx->hw_ctx->lock, irqflags); + + /* status peek ahead to retreive the next decoded frame timestamp */ +/* if (!readTxOnly && stats->drvRLL && (stats->DrvNextMDataPLD & BC_BIT(31))) { */ + if (!readTxOnly && stats->drvRLL) { + dev_dbg(chddev(), "Have Pictures %d\n", stats->drvRLL); + pic_width = stats->DrvNextMDataPLD & 0xffff; + stats->DrvNextMDataPLD = 0; + if (pic_width <= 1920) { + /* get fetch lock to make sure that fetch is not in progress as wel peek */ + if(down_interruptible(&ctx->hw_ctx->fetch_sem)) + goto get_out; + if(ctx->hw_ctx->pfnPeekNextDeodedFr(ctx->hw_ctx,&stats->DrvNextMDataPLD, &stats->picNumFlags, pic_width)) { + /* Check in case we dropped a picture here */ + crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); + stats->drvRLL = hw_stats.rdyq_count; + stats->drvFLL = hw_stats.freeq_count; + } + up(&ctx->hw_ctx->fetch_sem); + dev_dbg(chddev(), "peeking done\n"); + } + } + +get_out: return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_reset_stats(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +static BC_STATUS bc_cproc_reset_stats(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) { - crystalhd_hw_stats(&ctx->hw_ctx, NULL); + crystalhd_hw_stats(ctx->hw_ctx, NULL); return BC_STS_SUCCESS; } -static enum BC_STATUS bc_cproc_chg_clk(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +/** + * + * bc_cproc_release_user - Close Application Handle + * + * Used to be crystalhd_user_close + * + * @ctx: Command layer contextx. + * @uc: User ID context. + * + * Return: + * status + * + * Closer aplication handle and release app specific + * resources. + * + * Move to IOCTL based implementation called from the RELEASE IOCTL + */ +BC_STATUS bc_cproc_release_user(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { - struct BC_CLOCK *clock; - uint32_t oldClk; - enum BC_STATUS sts = BC_STS_SUCCESS; + + struct device *dev = chddev(); + uint32_t mode; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } - clock = &idata->udata.u.clockValue; - oldClk = ctx->hw_ctx.core_clock_mhz; - ctx->hw_ctx.core_clock_mhz = clock->clk; + if (ctx->user[idata->u_id].mode == DTS_MODE_INV) { + dev_err(dev, "Handle is already closed\n"); + return BC_STS_ERR_USAGE; + } + + mode = ctx->user[idata->u_id].mode; + + ctx->user[idata->u_id].mode = DTS_MODE_INV; + ctx->user[idata->u_id].in_use = 0; - if (ctx->state & BC_LINK_READY) { - sts = crystalhd_hw_set_core_clock(&ctx->hw_ctx); - if (sts == BC_STS_CLK_NOCHG) - ctx->hw_ctx.core_clock_mhz = oldClk; + dev_info(chddev(), "Closing user[%x] handle via ioctl with mode %x\n", idata->u_id, mode); + + if (((mode & 0xFF) == DTS_DIAG_MODE) || + ((mode & 0xFF) == DTS_PLAYBACK_MODE) || + ((bc_get_userhandle_count(ctx) == 0) && (ctx->hw_ctx != NULL))) { + ctx->cin_wait_exit = 1; + /* Stop the HW Capture just in case flush did not get called before stop */ + ctx->pwr_state_change = BC_HW_RUNNING; + crystalhd_hw_stop_capture(ctx->hw_ctx, true); + crystalhd_hw_free_dma_rings(ctx->hw_ctx); + crystalhd_destroy_dio_pool(ctx->adp); + crystalhd_delete_elem_pool(ctx->adp); + ctx->state = BC_LINK_INVALID; + crystalhd_hw_close(ctx->hw_ctx, ctx->adp); + kfree(ctx->hw_ctx); + ctx->hw_ctx = NULL; } - clock->clk = ctx->hw_ctx.core_clock_mhz; + if(ctx->adp->cfg_users > 0) + ctx->adp->cfg_users--; - return sts; + return BC_STS_SUCCESS; } /*=============== Cmd Proc Table.. ======================================*/ static const struct crystalhd_cmd_tbl g_crystalhd_cproc_tbl[] = { { BCM_IOC_GET_VERSION, bc_cproc_get_version, 0}, { BCM_IOC_GET_HWTYPE, bc_cproc_get_hwtype, 0}, - { BCM_IOC_REG_RD, bc_cproc_reg_rd, 0}, - { BCM_IOC_REG_WR, bc_cproc_reg_wr, 0}, - { BCM_IOC_FPGA_RD, bc_cproc_link_reg_rd, 0}, - { BCM_IOC_FPGA_WR, bc_cproc_link_reg_wr, 0}, - { BCM_IOC_MEM_RD, bc_cproc_mem_rd, 0}, - { BCM_IOC_MEM_WR, bc_cproc_mem_wr, 0}, + { BCM_IOC_REG_RD, bc_cproc_reg_rd, 0}, + { BCM_IOC_REG_WR, bc_cproc_reg_wr, 0}, + { BCM_IOC_FPGA_RD, bc_cproc_link_reg_rd, 0}, + { BCM_IOC_FPGA_WR, bc_cproc_link_reg_wr, 0}, + { BCM_IOC_MEM_RD, bc_cproc_mem_rd, 0}, + { BCM_IOC_MEM_WR, bc_cproc_mem_wr, 0}, { BCM_IOC_RD_PCI_CFG, bc_cproc_cfg_rd, 0}, { BCM_IOC_WR_PCI_CFG, bc_cproc_cfg_wr, 1}, { BCM_IOC_FW_DOWNLOAD, bc_cproc_download_fw, 1}, - { BCM_IOC_FW_CMD, bc_cproc_do_fw_cmd, 1}, + { BCM_IOC_FW_CMD, bc_cproc_do_fw_cmd, 1}, { BCM_IOC_PROC_INPUT, bc_cproc_proc_input, 1}, { BCM_IOC_ADD_RXBUFFS, bc_cproc_add_cap_buff, 1}, { BCM_IOC_FETCH_RXBUFF, bc_cproc_fetch_frame, 1}, @@ -775,12 +917,11 @@ static const struct crystalhd_cmd_tbl g_ { BCM_IOC_GET_DRV_STAT, bc_cproc_get_stats, 0}, { BCM_IOC_RST_DRV_STAT, bc_cproc_reset_stats, 0}, { BCM_IOC_NOTIFY_MODE, bc_cproc_notify_mode, 0}, - { BCM_IOC_CHG_CLK, bc_cproc_chg_clk, 0}, - { BCM_IOC_END, NULL}, + { BCM_IOC_RELEASE, bc_cproc_release_user, 0}, + { BCM_IOC_END, NULL}, }; /*=============== Cmd Proc Functions.. ===================================*/ - /** * crystalhd_suspend - Power management suspend request. * @ctx: Command layer context. @@ -798,16 +939,17 @@ static const struct crystalhd_cmd_tbl g_ * * Current gstreamer frame work does not provide any power management * related notification to user mode decoder plug-in. As a work-around - * we pass on the power management notification to our plug-in by completing + * we pass on the power mangement notification to our plug-in by completing * all outstanding requests with BC_STS_IO_USER_ABORT return code. */ -enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata) +BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { - enum BC_STATUS sts = BC_STS_SUCCESS; + struct device *dev = chddev(); + BC_STATUS sts = BC_STS_SUCCESS; + struct crystalhd_rx_dma_pkt *rpkt = NULL; if (!ctx || !idata) { - BCMLOG_ERR("Invalid Parameters\n"); + dev_err(dev, "Invalid Parameters\n"); return BC_STS_ERROR; } @@ -815,31 +957,42 @@ enum BC_STATUS crystalhd_suspend(struct return BC_STS_SUCCESS; if (ctx->state == BC_LINK_INVALID) { - BCMLOG(BCMLOG_DBG, "Nothing To Do Suspend Success\n"); + dev_dbg(dev, "Nothing To Do Suspend Success\n"); return BC_STS_SUCCESS; } - ctx->state |= BC_LINK_SUSPEND; + dev_dbg(dev, "State before suspend is %x\n", ctx->state); - bc_cproc_mark_pwr_state(ctx); + bc_cproc_mark_pwr_state(ctx, BC_HW_SUSPEND); /* going to suspend */ if (ctx->state & BC_LINK_CAP_EN) { - sts = bc_cproc_flush_cap_buffs(ctx, idata); - if (sts != BC_STS_SUCCESS) - return sts; + // Clean any pending RX + crystalhd_hw_stop_capture(ctx->hw_ctx, false); + while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_actq)) != NULL) + crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); + + while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_rdyq)) != NULL) + crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); } if (ctx->tx_list_id) { - sts = crystalhd_hw_cancel_tx(&ctx->hw_ctx, ctx->tx_list_id); + sts = crystalhd_hw_cancel_tx(ctx->hw_ctx, ctx->tx_list_id); if (sts != BC_STS_SUCCESS) return sts; } + else + { + // Even if there is no active TX DMA need to stop and reset TX DMA pointers + ctx->hw_ctx->pfnStopTxDMA(ctx->hw_ctx); + } - sts = crystalhd_hw_suspend(&ctx->hw_ctx); + ctx->state = BC_LINK_SUSPEND; + + sts = crystalhd_hw_suspend(ctx->hw_ctx); if (sts != BC_STS_SUCCESS) return sts; - BCMLOG(BCMLOG_DBG, "BCM70012 suspend success\n"); + dev_dbg(dev, "Crystal HD suspend success\n"); return BC_STS_SUCCESS; } @@ -860,11 +1013,19 @@ enum BC_STATUS crystalhd_suspend(struct * start a new playback session from the pre-suspend clip position. * */ -enum BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx) +BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx) { - BCMLOG(BCMLOG_DBG, "crystalhd_resume Success %x\n", ctx->state); + BC_STATUS sts = BC_STS_SUCCESS; + + sts = crystalhd_hw_resume(ctx->hw_ctx); + if (sts != BC_STS_SUCCESS) + return sts; - bc_cproc_mark_pwr_state(ctx); + bc_cproc_mark_pwr_state(ctx, BC_HW_RESUME); /* Starting resume */ + + ctx->state = BC_LINK_RESUME; + + dev_dbg(chddev(), "crystalhd_resume Success %x\n", ctx->state); return BC_STS_SUCCESS; } @@ -881,66 +1042,43 @@ enum BC_STATUS crystalhd_resume(struct c * application specific resources. HW layer initialization * is done for the first open request. */ -enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, - struct crystalhd_user **user_ctx) +BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, + struct crystalhd_user **user_ctx) { + struct device *dev = chddev(); struct crystalhd_user *uc; if (!ctx || !user_ctx) { - BCMLOG_ERR("Invalid arg..\n"); + dev_err(dev, "Invalid arg..\n"); return BC_STS_INV_ARG; } uc = bc_cproc_get_uid(ctx); if (!uc) { - BCMLOG(BCMLOG_INFO, "No free user context...\n"); + dev_info(dev, "No free user context...\n"); return BC_STS_BUSY; } - BCMLOG(BCMLOG_INFO, "Opening new user[%x] handle\n", uc->uid); - - crystalhd_hw_open(&ctx->hw_ctx, ctx->adp); + dev_info(dev, "Opening new user[%x] handle\n", uc->uid); - uc->in_use = 1; - - *user_ctx = uc; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_user_close - Close application handle. - * @ctx: Command layer contextx. - * @uc: User ID context. - * - * Return: - * status - * - * Closer application handle and release app specific - * resources. - */ -enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, - struct crystalhd_user *uc) -{ - uint32_t mode = uc->mode; - - ctx->user[uc->uid].mode = DTS_MODE_INV; - ctx->user[uc->uid].in_use = 0; - ctx->cin_wait_exit = 1; - ctx->pwr_state_change = 0; + uc->mode = DTS_MODE_INV; + uc->in_use = 0; - BCMLOG(BCMLOG_INFO, "Closing user[%x] handle\n", uc->uid); + if(ctx->hw_ctx == NULL) { + ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); + if(ctx->hw_ctx != NULL) + memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); + else + return BC_STS_ERROR; - if ((mode == DTS_DIAG_MODE) || (mode == DTS_PLAYBACK_MODE)) { - crystalhd_hw_free_dma_rings(&ctx->hw_ctx); - crystalhd_destroy_dio_pool(ctx->adp); - } else if (bc_cproc_get_user_count(ctx)) { - return BC_STS_SUCCESS; + crystalhd_hw_open(ctx->hw_ctx, ctx->adp); } - crystalhd_hw_close(&ctx->hw_ctx); + uc->in_use = 1; + + *user_ctx = uc; - ctx->state = BC_LINK_INVALID; + ctx->pwr_state_change = BC_HW_RUNNING; return BC_STS_SUCCESS; } @@ -955,18 +1093,19 @@ enum BC_STATUS crystalhd_user_close(stru * * Called at the time of driver load. */ -enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, +BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp) { + struct device *dev = &adp->pdev->dev; int i = 0; if (!ctx || !adp) { - BCMLOG_ERR("Invalid arg!!\n"); + dev_err(dev, "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->adp) - BCMLOG(BCMLOG_DBG, "Resetting Cmd context delete missing..\n"); + dev_dbg(dev, "Resetting Cmd context delete missing..\n"); ctx->adp = adp; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { @@ -975,9 +1114,16 @@ enum BC_STATUS crystalhd_setup_cmd_conte ctx->user[i].mode = DTS_MODE_INV; } + ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); + + memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); + /*Open and Close the Hardware to put it in to sleep state*/ - crystalhd_hw_open(&ctx->hw_ctx, ctx->adp); - crystalhd_hw_close(&ctx->hw_ctx); + crystalhd_hw_open(ctx->hw_ctx, ctx->adp); + crystalhd_hw_close(ctx->hw_ctx, ctx->adp); + kfree(ctx->hw_ctx); + ctx->hw_ctx = NULL; + return BC_STS_SUCCESS; } @@ -990,9 +1136,9 @@ enum BC_STATUS crystalhd_setup_cmd_conte * * Called at the time of driver un-load. */ -enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) +BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) { - BCMLOG(BCMLOG_DBG, "Deleting Command context..\n"); + dev_dbg(chddev(), "Deleting Command context..\n"); ctx->adp = NULL; @@ -1012,29 +1158,29 @@ enum BC_STATUS crystalhd_delete_cmd_cont * mode of operation and returns the function pointer * from the cproc table. */ -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, - uint32_t cmd, struct crystalhd_user *uc) +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, + struct crystalhd_user *uc) { + struct device *dev = chddev(); crystalhd_cmd_proc cproc = NULL; unsigned int i, tbl_sz; if (!ctx) { - BCMLOG_ERR("Invalid arg.. Cmd[%d]\n", cmd); + dev_err(dev, "Invalid arg.. Cmd[%d]\n", cmd); return NULL; } if ((cmd != BCM_IOC_GET_DRV_STAT) && (ctx->state & BC_LINK_SUSPEND)) { - BCMLOG_ERR("Invalid State [suspend Set].. Cmd[%d]\n", cmd); + dev_err(dev, "Invalid State [suspend Set].. Cmd[%x]\n", cmd); return NULL; } - tbl_sz = sizeof(g_crystalhd_cproc_tbl) / - sizeof(struct crystalhd_cmd_tbl); + tbl_sz = sizeof(g_crystalhd_cproc_tbl) / sizeof(struct crystalhd_cmd_tbl); for (i = 0; i < tbl_sz; i++) { if (g_crystalhd_cproc_tbl[i].cmd_id == cmd) { if ((uc->mode == DTS_MONITOR_MODE) && (g_crystalhd_cproc_tbl[i].block_mon)) { - BCMLOG(BCMLOG_INFO, "Blocking cmd %d\n", cmd); + dev_dbg(dev, "Blocking cmd %d \n", cmd); break; } cproc = g_crystalhd_cproc_tbl[i].cmd_proc; @@ -1050,7 +1196,7 @@ crystalhd_cmd_proc crystalhd_get_cmd_pro * @ctx: Command layer contextx. * * Return: - * TRUE: If interrupt from bcm70012 device. + * TRUE: If interrupt from CrystalHD device. * * * ISR entry point from OS layer. @@ -1058,9 +1204,13 @@ crystalhd_cmd_proc crystalhd_get_cmd_pro bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx) { if (!ctx) { - BCMLOG_ERR("Invalid arg..\n"); + printk(KERN_ERR "%s: Invalid arg..\n", __func__); return false; } - return crystalhd_hw_interrupt(ctx->adp, &ctx->hw_ctx); + /* If HW has not been initialized then all interrupts are spurious */ + if ((ctx->hw_ctx == NULL) || (ctx->hw_ctx->pfnFindAndClearIntr == NULL)) + return false; + + return ctx->hw_ctx->pfnFindAndClearIntr(ctx->adp, ctx->hw_ctx); } --- crystalhd~/crystalhd_cmds.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_cmds.h 2011-03-14 23:02:54.000000000 +0300 @@ -29,20 +29,24 @@ /* * NOTE:: This is the main interface file between the Linux layer - * and the hardware layer. This file will use the definitions + * and the harware layer. This file will use the definitions * from _dts_glob and dts_defs etc.. which are defined for * windows. */ -#include "crystalhd.h" +#include "crystalhd_hw.h" +#include "crystalhd_misc.h" -enum crystalhd_state { +extern struct device * chddev(void); + +enum _crystalhd_state{ BC_LINK_INVALID = 0x00, BC_LINK_INIT = 0x01, BC_LINK_CAP_EN = 0x02, BC_LINK_FMT_CHG = 0x04, BC_LINK_SUSPEND = 0x10, BC_LINK_PAUSED = 0x20, + BC_LINK_RESUME = 0x40, BC_LINK_READY = (BC_LINK_INIT | BC_LINK_CAP_EN | BC_LINK_FMT_CHG), }; @@ -62,12 +66,11 @@ struct crystalhd_cmd { spinlock_t ctx_lock; uint32_t tx_list_id; uint32_t cin_wait_exit; - uint32_t pwr_state_change; - struct crystalhd_hw hw_ctx; + uint32_t pwr_state_change; /* 0 is running, 1 is going to suspend, 2 is going to resume */ + struct crystalhd_hw *hw_ctx; }; -typedef enum BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *, - struct crystalhd_ioctl_data *); +typedef BC_STATUS (*crystalhd_cmd_proc)(struct crystalhd_cmd *, crystalhd_ioctl_data *); struct crystalhd_cmd_tbl { uint32_t cmd_id; @@ -75,18 +78,14 @@ struct crystalhd_cmd_tbl { uint32_t block_mon; }; -enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, - struct crystalhd_ioctl_data *idata); -enum BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, - uint32_t cmd, struct crystalhd_user *uc); -enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, - struct crystalhd_user **user_ctx); -enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, - struct crystalhd_user *uc); -enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, - struct crystalhd_adp *adp); -enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); + +BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata); +BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, + struct crystalhd_user *uc); +BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx); +BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp); +BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx); #endif --- crystalhd~/crystalhd_flea_ddr.c 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_flea_ddr.c 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,734 @@ +/*************************************************************************** + * Copyright (c) 2005-2010, Broadcom Corporation. + * + * Name: crystalhd_flea_ddr . c + * + * Description: + * BCM70015 generic DDR routines + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include "crystalhd_hw.h" +#include "crystalhd_flea_ddr.h" + +/*#include "bchp_ddr23_ctl_regs_0.h" */ +/*#include "bchp_ddr23_phy_byte_lane_0.h" */ +/*#include "bchp_ddr23_phy_byte_lane_1.h" */ +/*#include "bchp_ddr23_phy_control_regs.h" */ +/*#include "bchp_pri_arb_control_regs.h" */ +/*#include "bchp_pri_client_regs.h" */ + +/* RTS Programming Values for all Clients */ +/* column legend */ +/* [0]: 1=Program, 0=Default; */ +/* [1]: Blockout Count; */ +/* [2]: Critical Period; */ +/* [3]: Priority; */ +/* [4]: Access Mode */ +/* Default mode for clients is best effort */ + +uint32_t rts_prog_vals[21][5] = { + {1, 130, 130, 6, 1}, /* Deblock ( 0) */ + {1, 1469, 1469, 9, 1}, /* Cabac ( 1) */ + {1, 251, 251, 4, 1}, /* Iloop ( 2) */ + {1, 842, 842, 5, 1}, /* Oloop ( 3) */ + {1, 1512, 1512, 10, 1}, /* Symb_Int ( 4) */ + {1, 43, 43, 14, 1}, /* Mcomp ( 5) */ + {1, 1318, 1318, 11, 1}, /* XPT_0 ( 6) */ + {1, 4320, 4320, 16, 1}, /* XPT_1 ( 7) */ + {1, 5400, 5400, 17, 0}, /* XPT_2 ( 8) */ + {1, 1080, 1080, 18, 1}, /* ARM ( 9) */ + {1, 691, 691, 7, 0}, /* MEM_DMA (10) */ + {1, 1382, 1382, 15, 0}, /* SHARF (11) */ + {1, 346, 346, 2, 0}, /* BVN (12) */ + {1, 1728, 1728, 13, 1}, /* RxDMA3 (13) */ + {1, 864, 864, 8, 1}, /* TxDMA (14) */ + {1, 173, 173, 3, 1}, /* MetaDMA (15) */ + {1, 2160, 2160, 19, 1}, /* DirectDMA (16) */ + {1, 10800, 10800, 20, 1}, /* MSA (17) */ + {1, 216, 216, 1, 1}, /* TRACE (18) */ + {1, 1598, 1598, 12, 0}, /* refresh1 (19) */ + { 0, 0, 0, 0, 0}, /*(20) */ +}; + +void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode) +{ + uint32_t PLL_NDIV_INT[2]; + uint32_t PLL_M1DIV[2]; + int32_t i; + uint32_t tmp; + uint32_t config; + uint32_t timeout; + uint32_t skip_init[2]; /* completely skip initialization */ + /*uint32_t offset[2]; */ + uint32_t skip_pll_setup; + uint32_t poll_cnt; + + skip_init[0] = 0; + skip_init[1] = 0; + + /* If the test mode is not 0 then skip the PLL setups too. */ + if (tmode != 0){ + skip_pll_setup = 1; + } + else { + skip_pll_setup = 0; + } + + /* Use this scratch register in DDR0 - which should reset to 0 - as a simple symaphore for the test */ + /* to monitor if and when the Initialization of the DDR is complete */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0); + + if (!skip_pll_setup) { + for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, + (0 << 0) | /*PWRDWN */ + (0 << 1) | /*REFCOMP_PWRDWN */ + (1 << 2) | /*ARESET */ + (1 << 3) | /*DRESET */ + (0 << 4) | /*ENB_CLKOUT */ + (0 << 5) | /*BYPEN ??? */ + (0 << 6) | /*PWRDWN_CH1 */ + (0 << 8) | /*DLY_CH1 */ + (0 << 10)| /*VCO_RNG */ + (1 << 31) /*DIV2 CLK RESET */ + ); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER, + (1 << 0) | /*P1DIV */ + (1 << 4) | /*P2DIV */ + (PLL_NDIV_INT[i] << 8) | /*NDIV_INT */ + (1 << 24) /*BYPASS_SDMOD */ + ); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER, + (PLL_M1DIV[i] << 24) /*M1DIV */ + ); + + config = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + config &= 0xfffffffb; /*clear ARESET */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); + } + + /*poll for lock */ + for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); + while((timeout>0) && ((tmp & 0x1) == 0)){ + msleep_interruptible(1); + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); + timeout--; + } + if (timeout<=0) + printk("Timed out waiting for DDR Controller PLL %d to lock\n",i); + } + + /*deassert PLL digital reset */ + for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + config &= 0xfffffff7; /*clear DRESET */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); + } + + /*deassert reset of logic */ + for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + config &= 0x7fffffff; /*clear logic reset */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); + } + } /* end (skip_pll_setup) */ + + /*run VDL calibration for all byte lanes */ + for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); + tmp = ( + (1 << 0) | /*calib_fast */ + (1 << 1) /*calib_once */ + ); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); + + + if (!skip_pll_setup){ /*VDLs might not lock if clocks are bypassed */ + timeout=100; + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); + while((timeout>0) && ((tmp & 0x3) == 0x0)){ + msleep_interruptible(1); + timeout--; + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); + } + if ((tmp & 0x3) != 0x3) + printk("VDL calibration did not finish or did not lock!\n"); + timeout=100; + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); + while((timeout>0) && ((tmp & 0x3) == 0x0)){ + msleep_interruptible(1); + timeout--; + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); + } + if ((tmp & 0x3) != 0x3) + printk("VDL calibration did not finish or did not lock!\n"); + + if(timeout<=0){ + printk("DDR PHY %d VDL Calibration failed\n",i); + } + } + else { + msleep_interruptible(1); + } + + /*clear VDL calib settings */ + tmp = 0; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); + + /*override the ADDR/CTRL VDLs with results from Bytelane #0 */ + /*if tmode other than zero then set the VDL compensations to max values of 0x1ff. */ + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); + tmp = (tmp >> 4) & 0x3ff; + /* If in other than tmode 0 then set the VDL override settings to max. */ + if (tmode) { + tmp = 0x3ff; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3, 0x1003f); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK); + } + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE, + (((tmp & 0x3f0) >> 4) << 0) | /* step override value */ + (1 << 16) | /* override enable */ + (1 << 20) /* override force ; no update vdl required */ + ); + + /* NAREN added support for ZQ Calibration */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, 0); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK); + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); + + poll_cnt = 0; + while(1) + { + if(!(tmp & BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK)) + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); + else + break; + + if(poll_cnt++ > 100) + break; + } + + if(tmode) { + /* Set fields addr_ovr_en and dq_pvr_en to '1'. Set all *_override_val fields to 0xf - ZQ_PVT_COMP_CTL */ + tmp = ( ( 1 << 25) | /* addr_ovr_en */ + ( 1 << 24) | /* dq_ovr_en */ + (0xf << 12) | /* addr_pd_override_val */ + (0xf << 8) | /* addr_nd_override_val */ + (0xf << 4) | /* dq_pd_override_val */ + (0xf << 0) ); /* dq_nd_override_val */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, tmp); + /* Drive_PAD_CTL register. Set field selrxdrv and slew to 0; */ + tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL); + tmp &= (0xfffffffe); /*clear bits 0 and 1. */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL,tmp); + } + }/*for(i=0.. */ +} + +void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, + int32_t port, + int32_t ddr3, + int32_t speed_grade, + int32_t col, + int32_t bank, + int32_t row, + uint32_t tmode) +{ + /*uint32_t offset; */ + /*uint32_t arb_refresh_addr; */ + uint32_t port_int; + + uint32_t data; + + /*DDR2 Parameters */ + uint8_t tRCD = 0; + uint8_t tRP = 0; + uint8_t tRRD = 0; + uint8_t tWR = 0; + uint8_t tWTR = 0; + uint8_t tCAS = 0; + uint8_t tWL = 0; + uint8_t tRTP = 0; + uint8_t tRAS = 0; + uint8_t tFAW = 0; + uint8_t tRFC = 0; + uint8_t INTLV_BYTES = 0; + uint8_t INTLV_DISABLE = 0; + uint8_t CTRL_BITS = 0; + uint8_t ALLOW_PICTMEM_RD = 0; + uint8_t DIS_DQS_ODT = 0; + uint8_t CS0_ONLY = 0; + uint8_t EN_ODT_EARLY = 0; + uint8_t EN_ODT_LATE = 0; + uint8_t USE_CHR_HGT = 0; + uint8_t DIS_ODT = 0; + uint8_t EN_2T_TIMING = 0; + uint8_t CWL = 0; + uint8_t DQ_WIDTH = 0; + + uint8_t DM_IDLE_MODE = 0; + uint8_t CTL_IDLE_MODE = 0; + uint8_t DQ_IDLE_MODE = 0; + + uint8_t DIS_LATENCY_CTRL = 0; + + uint8_t PSPLIT = 0; + uint8_t DSPLIT = 0; + + /* For each controller port, 0 and 1. */ + for (port_int=0; port_int < 1; ++port_int) { +#if 0 + printk("******************************************************\n"); + printk("* Configuring DDR23 at addr=0x%x, speed grade [%s]\n",0, + ((speed_grade == DDR2_667MHZ) && (tmode == 0)) ? "667MHZ": + ((speed_grade == DDR2_533MHZ) && (tmode == 0)) ? "533MHZ": + ((speed_grade == DDR2_400MHZ) && (tmode == 0)) ? "400MHZ": + ((speed_grade == DDR2_333MHZ) && (tmode == 0)) ? "333MHZ": + ((speed_grade == DDR2_266MHZ) && (tmode == 0)) ? "266MHZ": "400MHZ" ); +#endif + /* Written in this manner to prevent table lookup in Memory for embedded MIPS code. */ + /* Cannot use memory until it is inited! Case statements with greater than 5 cases use memory tables */ + /* when optimized. Tony O 9/18/07 */ + /* Note if not in test mode 0, choose the slowest clock speed. */ + if (speed_grade == DDR2_200MHZ) { + tRCD = 3; + tRP = 3; + tRRD = 2; + tWR = 3; + tWTR = 2; + tCAS = 4; + tWL = 3; + tRTP = 2; + tRAS = 8; + tFAW = 10; + if (bank == BANK_SIZE_4) + tRFC = 21; + else /*BANK_SIZE_8 */ + tRFC = 26; + } + else if (speed_grade == DDR2_266MHZ ) { + tRCD = 4; + tRP = 4; + tRRD = 3; + tWR = 4; + tWTR = 2; + tCAS = 4; + tWL = 3; + tRTP = 2; + tRAS = 11; + tFAW = 14; + if (bank == BANK_SIZE_4) + tRFC = 28; + else /*BANK_SIZE_8 */ + tRFC = 34; + } + else if (speed_grade == DDR2_333MHZ) { + tRCD = 4; + tRP = 4; + tRRD = 4; + tWR = 5; + tWTR = 3; + tCAS = 4; + tWL = 3; + tRTP = 3; + tRAS = 14; + tFAW = 17; + if (bank == BANK_SIZE_4) + tRFC = 35; + else /*BANK_SIZE_8 */ + tRFC = 43; + } + else if ((speed_grade == DDR2_400MHZ) || (tmode != 0)) { /* -25E timing */ + tRCD = 6; + tRP = 6; + tRRD = 4; + tWR = 6; + tWTR = 4; + tCAS = ddr3 ? 6 : 5; + tWL = ddr3 ? 5 : 4; + tRTP = 3; + tRAS = 18; + tFAW = 20; + if (bank == BANK_SIZE_4) + tRFC = 42; + else /*BANK_SIZE_8 */ + tRFC = 52; + CWL = tWL - 5; + } + else if (speed_grade == DDR2_533MHZ) { /* -187E timing */ + tRCD = 7; + tRP = 7; + tRRD = 6; + tWR = 8; + tWTR = 4; + tCAS = 7; + tWL = tCAS - 1; + tRTP = 4; + tRAS = 22; + tFAW = 24; + tRFC = 68; + CWL = tWL - 5; + } + else if (speed_grade == DDR2_667MHZ) { /* -15E timing */ + tRCD = 9; + tRP = 9; + tRRD = 5;/* 4/5 */ + tWR = 10; + tWTR = 5; + tCAS = 9; + tWL = 7; + tRTP = 5; + tRAS = 24; + tFAW = 30; /* 20/30 */ + tRFC = 74; + CWL = tWL - 5; + } + else + printk("init: CANNOT HAPPEN - Memory DDR23 Ctrl_init failure. Incorrect speed grade type [%d]\n", speed_grade); + + CTRL_BITS = 0; /* Control Bit for CKE signal */ + EN_2T_TIMING = 0; + INTLV_DISABLE = ddr3 ? 1:0; /* disable for DDR3, enable for DDR2 */ + INTLV_BYTES = 0; + ALLOW_PICTMEM_RD = 0; + DIS_DQS_ODT = 0; + CS0_ONLY = 0; + EN_ODT_EARLY = 0; + EN_ODT_LATE = 0; + USE_CHR_HGT = 0; + DIS_ODT = 0; + + /*Power Saving Controls */ + DM_IDLE_MODE = 0; + CTL_IDLE_MODE = 0; + DQ_IDLE_MODE = 0; + + /*Latency Control Setting */ + DIS_LATENCY_CTRL = 0; + + /* ****** Start of Grain/Flea specific fixed settings ***** */ + CS0_ONLY = 1 ; /* 16-bit mode only */ + INTLV_DISABLE = 1 ; /* Interleave is always disabled */ + DQ_WIDTH = 16 ; + /* ****** End of Grain specific fixed settings ***** */ + +#if 0 + printk("* DDR23 Config: CAS: %d, tRFC: %d, INTLV: %d, WIDTH: %d\n", + tCAS,tRFC,INTLV_BYTES,DQ_WIDTH); + printk("******************************************************\n"); +#endif + /*Disable refresh */ + data = ((0x68 << 0) | /*Refresh period */ + (0x0 << 12) /*disable refresh */ + ); + + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, data); + + /* DecSd_Ddr2Param1 */ + data = 0; + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trcd, tRCD); /* trcd */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trp, tRP); /* trp */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trrd, tRRD); /* trrd */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twr, tWR); /* twr */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twtr, tWTR); /* twtr */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, tcas, tCAS); /* tcas */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twl, tWL); /* twl */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trtp, tRTP); /* trtp */ + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS1, data ); + + /*DecSd_Ddr2Param3 - deassert reset only */ + data = 0; + /*DEBUG_PRINT(PARAMS3, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); + + /* Reset must be deasserted 500us before CKE. This needs */ + /* to be reflected in the CFE. (add delay here) */ + + /*DecSd_Ddr2Param2 */ + data = 0; + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tras, tRAS); /* tras */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tfaw, tFAW); /* tfaw */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, trfc, tRFC); /* trfc */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, bank_bits, bank & 1); /* 0 = bank size of 4K == 2bits, 1 = bank size of 8k == 3 bits */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, allow_pictmem_rd, ALLOW_PICTMEM_RD); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, cs0_only, CS0_ONLY); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, dis_itlv, INTLV_DISABLE); /* #disable interleave */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, il_sel, INTLV_BYTES); /* #bytes per interleave */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, sd_col_bits, col & 3); /* column bits, 0 = 9, 1= 10, 2 or 3 = 11 bits */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, clke, CTRL_BITS); /* Control Bit for CKE signal */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, use_chr_hgt, USE_CHR_HGT); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, row_bits, row & 1); /* row size 1 is 16K for 2GB device, otherwise 0 and 8k sized */ + + /*DEBUG_PRINT(PARAMS2, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, data ); + + /*DecSd_Ddr2Param3. */ + data = 0; + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_en, DIS_ODT ? 0 : 1); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_le_adj, EN_ODT_EARLY ? 1 : 0); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_te_adj, EN_ODT_LATE ? 1 : 0); + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, cmd_2t, EN_2T_TIMING ? 1: 0); /* 2T timing is disabled */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr_bl, ddr3 ? 1: 0); /* 0 for DDR2, 1 for DDR3 */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_mode, ddr3 ? 1:0); /* ddr3 preamble */ + SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr3_reset, ddr3 ? 0:1); /* ddr3 reset */ + + /*DEBUG_PRINT(PARAMS3, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); + } /* for( port_int......) */ + + data = 0; + SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, slew, 1); + SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, seltxdrv_ci, 1); + SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL, data ); + + data = 0; + SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, slew, 0); + SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, selrxdrv, 0); + SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, seltxdrv_ci, 0); + SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); + SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, rt60b, 0); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, data ); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, data ); + + data = 0; + + if (speed_grade == DDR2_667MHZ) { + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((2 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); + } else { + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((1 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); + } + + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK) | ((((DIS_DQS_ODT || DIS_ODT) ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK)); + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK)); + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK) | (((DIS_ODT ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK)); + data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK)); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, data); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, data); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); + + /* Disable unused clocks */ + + for (port_int=0; port_int<1; ++port_int) { /* For Grain */ + /* Changes for Grain/Flea */ + /*offset = 0; */ + /*arb_refresh_addr = BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0; */ + /*offset += GLOBAL_REG_RBUS_START; */ + /* Changes for Grain - till here */ + + if (ddr3) { + data = (CWL & 0x07) << 3; + /*DEBUG_PRINT(LOAD_EMODE2_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); + + data = 0; + /*DEBUG_PRINT(LOAD_EMODE3_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); + + data = 6; /* was 4; */ + /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); + + data = 0x1100; /* Reset DLL */ + data += ((tWR-4) << 9); + data += ((tCAS-4) << 4); + /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); + + + data = 0x0400; /* long calibration */ + /*DEBUG_PRINT(ZQ_CALIBRATE, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE, data ); + + msleep_interruptible(1); + } + else + { + /*DecSd_RegSdPrechCmd // Precharge */ + data = 0; + /*DEBUG_PRINT(PRECHARGE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); + + /*DEBUG_PRINT(PRECHARGE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); + + /*DecSd_RegSdLdModeCmd //Clear EMODE 2,3 */ + data = 0; + /*DEBUG_PRINT(LOAD_EMODE2_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); + + /*DEBUG_PRINT(LOAD_EMODE3_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); + + /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD */ + data = 0x3C0; + /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); + + /*DecSd_RegSdLdModeCmd */ + data = 0x102; /* Reset DLL */ + data += ((tWR-1) << 9); + data += (tCAS << 4); + /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); + + /*DecSd_RegSdPrechCmd // Precharge */ + data = 0; + /*DEBUG_PRINT(PRECHARGE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); + + /*DEBUG_PRINT(PRECHARGE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); + + /*DecSd_RegSdRefCmd // Refresh */ + data = 0x69; + /*DEBUG_PRINT(REFRESH_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); + + /*DEBUG_PRINT(REFRESH_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); + + /*DecSd_RegSdLdModeCmd */ + data = 0x002; /* Un-Reset DLL */ + data += ((tWR-1) << 9); + data += (tCAS << 4); + /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); + + /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD */ + data = 0x3C0; + /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); + + /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; disable OCD */ + data = 0x40; + /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); + } + + /*Enable refresh */ + data = ((0x68 << 0) | /*Refresh period */ + (0x1 << 12) /*enable refresh */ + ); + if (tmode == 0) { + /*MemSysRegWr(arb_refresh_addr + GLOBAL_REG_RBUS_START,data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0,data); + } + + /*offset = 0; */ + /*offset += GLOBAL_REG_RBUS_START; */ + + /* Use this scratch register in DDR0 as a simple symaphore for the test */ + /* to monitor if and when the Initialization of the DDR is complete. Seeing a non zero value */ + /* indicates DDR init complete. This code is ONLY for the MIPS. It has no affect in init.c */ + /* The MIPS executes this code and we wait until DDR 1 is inited before setting the semaphore. */ + if ( port_int == 1) + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0xff); + + /*Setup the Arbiter Data and Pict Buffer split if specified */ + if (port_int==0) { /*only need to do this once */ + /*where is the pict buff split (2 bits) */ + /*0 = always mem_a, 1 = (<128 is mem_a), 2 = (<64 is mem_a), 3 = always mem_b */ + PSPLIT = 0; + + /*0 = 32MB, 1 = 64MB, 2 = 128 MB, 3 = 256MB, 4=512MB */ + DSPLIT = 4; + + data = 0; + data += DSPLIT; + data += PSPLIT<< 4; + /* MemSysRegWr (PRI_ARB_CONTROL_REGS_CONC_CTL + offset, data ); */ + } + + if (DIS_LATENCY_CTRL == 1){ + /*set the work limit to the maximum */ + /*DEBUG_PRINT(LATENCY, data); */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LATENCY, 0x3ff ); + } + } /* for (port_int=0...... ) */ + + return; +} + +void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw) +{ + uint32_t addr_cnt; + uint32_t addr_ctrl; + uint32_t i; + + addr_cnt = BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT; + addr_ctrl = BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL; + + /*Go through the various clients and program them */ + for(i=0;i<21;i++){ + if (rts_prog_vals[i][0] > 0) { + hw->pfnWriteDevRegister(hw->adp, addr_cnt, + (rts_prog_vals[i][1]) | /*Blockout Count */ + (rts_prog_vals[i][2] << 16) /*Critical Period */ + ); + hw->pfnWriteDevRegister(hw->adp, addr_ctrl, + (rts_prog_vals[i][3]) | /*Priority Level */ + (rts_prog_vals[i][4] << 8) /*Access Mode */ + ); + } + addr_cnt+=8; + addr_ctrl+=8; + } +} --- crystalhd~/crystalhd_flea_ddr.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_flea_ddr.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,73 @@ +/*************************************************************************** + * Copyright (c) 2005-2010, Broadcom Corporation. + * + * Name: crystalhd_flea_ddr . h + * + * Description: + * BCM70015 generic DDR routines + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#undef BRCM_ALIGN +#define BRCM_ALIGN(c,r,f) 0 + +#define MEM_SYS_NUM_DDR_PLLS 2; + +/*extern uint32_t rts_prog_vals[][5]; */ + +enum eDDR2_SPEED_GRADE { + DDR2_400MHZ = 0x0, + DDR2_333MHZ = 0x1, + DDR2_266MHZ = 0x2, + DDR2_200MHZ = 0x3, + DDR2_533MHZ = 0x4, + DDR2_667MHZ = 0x5 +}; + +enum eSD_COL_SIZE { + COL_BITS_9 = 0x0, + COL_BITS_10 = 0x1, + COL_BITS_11 = 0x2, +}; + +enum eSD_BANK_SIZE { + BANK_SIZE_4 = 0x0, + BANK_SIZE_8 = 0x1, +}; + +enum eSD_ROW_SIZE { + ROW_SIZE_8K = 0x0, + ROW_SIZE_16K = 0x1, +}; + +/*DDR PHY PLL init routine */ +void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode); + +/*DDR controller init routine */ +void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, + int32_t port, + int32_t ddr3, + int32_t speed_grade, + int32_t col, + int32_t bank, + int32_t row, + uint32_t tmode ); + +/*RTS Init routines */ +void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw); --- crystalhd~/crystalhd_fleafuncs.c 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_fleafuncs.c 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,2955 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_fleafuncs.c + * + * Description: + * BCM70015 Linux driver HW layer. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include +#include +#include +#include +#include +#include "crystalhd_hw.h" +#include "crystalhd_fleafuncs.h" +#include "crystalhd_lnx.h" +#include "FleaDefs.h" +#include "crystalhd_flea_ddr.h" + +#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) + +void crystalhd_flea_core_reset(struct crystalhd_hw *hw) +{ + unsigned int pollCnt=0,regVal=0; + + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_core_reset]: Starting core reset\n"); + + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL, 0x01); + + pollCnt=0; + while (1) + { + pollCnt++; + regVal=0; + + msleep_interruptible(1); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL); + + if(!(regVal & 0x01)) + { + /* + -- Bit is 0, Reset is completed. Which means that + -- wait for sometime and then allow other accesses. + */ + msleep_interruptible(1); + break; + } + + if(pollCnt > MAX_VALID_POLL_CNT) + { + printk("!!FATAL ERROR!! Core Reset Failure\n"); + break; + } + } + + msleep_interruptible(5); + + return; +} + +void crystalhd_flea_disable_interrupts(struct crystalhd_hw *hw) +{ + union FLEA_INTR_BITS_COMMON IntrMaskReg; + /* + -- Mask everything except the reserved bits. + */ + IntrMaskReg.WholeReg =0xffffffff; + IntrMaskReg.Reserved1=0; + IntrMaskReg.Reserved2=0; + IntrMaskReg.Reserved3=0; + IntrMaskReg.Reserved4=0; + + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_SET_REG, IntrMaskReg.WholeReg); + + return; +} + +void crystalhd_flea_enable_interrupts(struct crystalhd_hw *hw) +{ + union FLEA_INTR_BITS_COMMON IntrMaskReg; + /* + -- Clear The Mask for everything except the reserved bits. + */ + IntrMaskReg.WholeReg =0xffffffff; + IntrMaskReg.Reserved1=0; + IntrMaskReg.Reserved2=0; + IntrMaskReg.Reserved3=0; + IntrMaskReg.Reserved4=0; + + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_CLR_REG, IntrMaskReg.WholeReg); + + return; +} + +void crystalhd_flea_clear_interrupts(struct crystalhd_hw *hw) +{ + union FLEA_INTR_BITS_COMMON IntrStsValue; + + IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); + + if(IntrStsValue.WholeReg) + { + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); + } + + return; +} + +bool crystalhd_flea_detect_ddr3(struct crystalhd_hw *hw) +{ + uint32_t regVal = 0; + + /*Set the Multiplexer to select the GPIO-6*/ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0); + + /*Make sure that the bits-24:27 are reset*/ + if(regVal & 0x0f000000) + { + regVal = regVal & 0xf0ffffff; /*Clear bit 24-27 for selecting GPIO_06*/ + hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, regVal); + } + + regVal=0; + /*Set the Direction of GPIO-6*/ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_IODIR_LO); + + if(!(regVal & BC_BIT(6))) + { + /*Set the Bit number 6 to make the GPIO6 as input*/ + regVal |= BC_BIT(6); + hw->pfnWriteDevRegister(hw->adp, BCHP_GIO_IODIR_LO, regVal); + } + + regVal=0; + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_DATA_LO); + + /*If this bit is clear then have DDR-3 else we have DDR-2*/ + if(!(regVal & BC_BIT(6))) + { + dev_dbg(&hw->adp->pdev->dev,"DDR-3 Detected\n"); + return true; + } + dev_dbg(&hw->adp->pdev->dev,"DDR-2 Detected\n"); + return false; +} + +void crystalhd_flea_init_dram(struct crystalhd_hw *hw) +{ + int32_t ddr2_speed_grade[2]; + uint32_t sd_0_col_size, sd_0_bank_size, sd_0_row_size; + uint32_t sd_1_col_size, sd_1_bank_size, sd_1_row_size; + uint32_t ddr3_mode[2]; + uint32_t regVal; + bool bDDR3Detected=false; /*Should be filled in using the detection logic. Default to DDR2 */ + + /* On all designs we are using DDR2 or DDR3 x16 and running at a max of 400Mhz */ + /* Only one bank of DDR supported. The other is a dummy */ + + ddr2_speed_grade[0] = DDR2_400MHZ; + ddr2_speed_grade[1] = DDR2_400MHZ; + sd_0_col_size = COL_BITS_10; + sd_0_bank_size = BANK_SIZE_8; + sd_0_row_size = ROW_SIZE_8K; /* DDR2 */ + /* sd_0_row_size = ROW_SIZE_16K; // DDR3 */ + sd_1_col_size = COL_BITS_10; + sd_1_bank_size = BANK_SIZE_8; + sd_1_row_size = ROW_SIZE_8K; + ddr3_mode[0] = 0; + ddr3_mode[1] = 0; + + bDDR3Detected = crystalhd_flea_detect_ddr3(hw); + if(bDDR3Detected) + { + ddr3_mode[0] = 1; + sd_0_row_size = ROW_SIZE_16K; /* DDR3 */ + sd_1_row_size = ROW_SIZE_16K; /* DDR3 */ + + } + + /* Step 1. PLL Init */ + crystalhd_flea_ddr_pll_config(hw, ddr2_speed_grade, 1, 0); /* only need to configure PLLs in TM0 */ + + /* Step 2. DDR CTRL Init */ + crystalhd_flea_ddr_ctrl_init(hw, 0, ddr3_mode[0], ddr2_speed_grade[0], sd_0_col_size, sd_0_bank_size, sd_0_row_size, 0); + + /* Step 3 RTS Init - Real time scheduling memory arbiter */ + crystalhd_flea_ddr_arb_rts_init(hw); + + /* NAREN turn off ODT. The REF1 and SV1 and most customer designs allow this. */ + /* IF SOMEONE COMPLAINS ABOUT MEMORY OR DATA CORRUPTION LOOK HERE FIRST */ + + /*hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, 0x02, false); */ + + /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3); + regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, regVal);*/ + + /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL); + regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL); + regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, regVal);*/ + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE); + regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, regVal); + + return; +} + +uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) +{ + uint32_t baseAddr = reg_off >> 16; + void *regAddr; + + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return 0; + } + + if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) /* Direct Mapped Region */ + { + regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); + if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return 0; + } + return readl(regAddr); + } + else /* non directly mapped region */ + { + if(adp->pci_i2o_len < 0xFFFF) { + printk("Un-expected mapped region size\n"); + return 0; + } + regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; + writel(reg_off | 0x10000000, regAddr); + regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; + return readl(regAddr); + } +} + +void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +{ + uint32_t baseAddr = reg_off >> 16; + void *regAddr; + + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return; + } + + if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) /* Direct Mapped Region */ + { + regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); + if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return ; + } + writel(val, regAddr); + } + else /* non directly mapped region */ + { + if(adp->pci_i2o_len < 0xFFFF) { + printk("Un-expected mapped region size\n"); + return; + } + regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; + writel(reg_off | 0x10000000, regAddr); + regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; + writel(val, regAddr); + } +} + +/** +* crystalhd_flea_mem_rd - Read data from DRAM area. +* @adp: Adapter instance +* @start_off: Start offset. +* @dw_cnt: Count in dwords. +* @rd_buff: Buffer to copy the data from dram. +* +* Return: +* Status. +* +* Dram read routine. +*/ +BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, + uint32_t dw_cnt, uint32_t *rd_buff) +{ + uint32_t ix = 0; + uint32_t addr = start_off, base; + + if (!hw || !rd_buff) { + printk(KERN_ERR "%s: Invalid arg\n", __func__); + return BC_STS_INV_ARG; + } + + if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { + /*printk(KERN_ERR "%s: Flea power down, cann't read memory.\n", __func__); */ + return BC_STS_BUSY; + } + + if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { + printk(KERN_ERR "Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); + return BC_STS_ERROR; + } + + /* Set the base addr for the 512kb window */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, + (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); + + for (ix = 0; ix < dw_cnt; ix++) { + rd_buff[ix] = readl(hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); + base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; + addr += 4; /* DWORD access at all times */ + if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { + /* Set the base addr for next 512kb window */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, + (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); + } + } + return BC_STS_SUCCESS; +} + +/** +* crystalhd_flea_mem_wr - Write data to DRAM area. +* @adp: Adapter instance +* @start_off: Start offset. +* @dw_cnt: Count in dwords. +* @wr_buff: Data Buffer to be written. +* +* Return: +* Status. +* +* Dram write routine. +*/ +BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, + uint32_t dw_cnt, uint32_t *wr_buff) +{ + uint32_t ix = 0; + uint32_t addr = start_off, base; + uint32_t temp; + + if (!hw || !wr_buff) { + printk(KERN_ERR "%s: Invalid arg\n", __func__); + return BC_STS_INV_ARG; + } + + if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { + /*printk(KERN_ERR "%s: Flea power down, cann't write memory.\n", __func__); */ + return BC_STS_BUSY; + } + + if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { + printk("Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); + return BC_STS_ERROR; + } + + /* Set the base addr for the 512kb window */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, + (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); + + for (ix = 0; ix < dw_cnt; ix++) { + writel(wr_buff[ix], hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); + base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; + addr += 4; /* DWORD access at all times */ + if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { + /* Set the base addr for next 512kb window */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, + (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); + } + } + + /*Dummy Read To Flush Memory Arbitrator*/ + crystalhd_flea_mem_rd(hw, start_off, 1, &temp); + return BC_STS_SUCCESS; +} + + +static +void crystalhd_flea_runtime_power_up(struct crystalhd_hw *hw) +{ + uint32_t regVal; + uint64_t currTick; + uint32_t totalTick_Hi; + uint32_t TickSpentInPD_Hi; + uint64_t temp_64; + long totalTick_Hi_f; + long TickSpentInPD_Hi_f; + + /*printk("RT PU \n"); */ + + /* NAREN This function restores clocks and power to the DRAM and to the core to bring the decoder back up to full operation */ + /* Start the DRAM controller clocks first */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + regVal &= ~(BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); + + /* Delay to allow the DRAM clock to stabilize */ + udelay(25); + + /* Power Up PHY and start clocks on DRAM device */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, + ~(BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK)); + + /* Delay to allow the PLL to lock */ + udelay(25); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK ); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK ); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK ); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); + + /* Start Refresh Cycles from controller */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); + regVal |= BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); + + /* turn off self-refresh */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); + regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); + + udelay(5); + + /* Issue refresh cycle */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); + + /* Enable the ARM AVD and BLINK clocks */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + + regVal &= ~(BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK); + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, 0x03000000); + + /* Start arbiter */ + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); + +#ifdef _POWER_HANDLE_AVD_WATCHDOG_ + /* Restore Watchdog timers */ + /* Make sure the timeouts do not happen */ + /*Outer Loop Watchdog timer */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, hw->OLWatchDogTimer); + + /*//Inner Loop Watchdog timer */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, hw->ILWatchDogTimer); + +#endif + + /*printk("RT Power Up Flea Complete\n"); */ + + rdtscll(currTick); + + hw->TickSpentInPD += (currTick - hw->TickStartInPD); + + temp_64 = (hw->TickSpentInPD)>>24; + TickSpentInPD_Hi = (uint32_t)(temp_64); + TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; + + temp_64 = (currTick - hw->TickCntDecodePU)>>24; + totalTick_Hi = (uint32_t)(temp_64); + totalTick_Hi_f = (long)totalTick_Hi; + + if( totalTick_Hi_f <= 0 ) + { + temp_64 = (hw->TickSpentInPD); + TickSpentInPD_Hi = (uint32_t)(temp_64); + TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; + + temp_64 = (currTick - hw->TickCntDecodePU); + totalTick_Hi = (uint32_t)(temp_64); + totalTick_Hi_f = (long)totalTick_Hi; + } + + if( totalTick_Hi_f <= 0 ) + { + printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); + hw->PDRatio = 60; + } + else + hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; + + /*printk("Ticks currently spent in PD: 0x%llx Total: 0x%llx Ratio %d,\n", */ + /* hw->TickSpentInPD, (currTick - hw->TickCntDecodePU), hw->PDRatio); */ + + /* NAREN check if the PD ratio is greater than 75. If so, try to increase the PauseThreshold to improve the ratio */ + /* never go higher than the default threshold */ + if((hw->PDRatio > 75) && (hw->PauseThreshold < hw->DefaultPauseThreshold)) + { + /*printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, incress PauseThreshold.\n", */ + /* hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); */ + hw->PauseThreshold++; + } + else + { + /*printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, don't incress PauseThreshold.\n", */ + /* hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); */ + } + + return; +} + +static +void crystalhd_flea_runtime_power_dn(struct crystalhd_hw *hw) +{ + uint32_t regVal; + uint32_t pollCnt; + + /*printk("RT PD \n"); */ + + hw->DrvPauseCnt++; + + /* NAREN This function stops the decoder clocks including the AVD, ARM and DRAM */ + /* It powers down the DRAM device and places the DRAM into self-refresh */ + +#ifdef _POWER_HANDLE_AVD_WATCHDOG_ + /* Make sure the timeouts do not happen */ + /* Because the AVD drops to a debug prompt and stops decoding if it hits any watchdogs */ + /*Outer Loop Watchdog timer */ + regVal = hw->pfnReadDevRegister(hw->adp, + BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR); + + hw->OLWatchDogTimer = regVal; + hw->pfnWriteDevRegister(hw->adp, + BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, + 0xffffffff); + + /*Inner Loop Watchdog timer */ + regVal = hw->pfnReadDevRegister(hw->adp, + BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR); + + hw->ILWatchDogTimer = regVal; + hw->pfnWriteDevRegister(hw->adp, + BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, + 0xffffffff); +#endif + + /* Stop memory arbiter first to freese memory access */ + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable); + + /* delay at least 15us for memory transactions to complete */ + /* udelay(15); */ + + /* Wait for MEMC to become idle. Continue even if we are no since worst case this would just mean higher power consumption */ + pollCnt=0; + while (pollCnt++ <= 400) /*200 */ + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); + + if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) + { + /* udelay(10); */ + break; + } + udelay(10); + } + + /*If we failed Start the arbiter and return*/ + if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK)) + { + printk("RT PD : failed Start the arbiter and return.\n"); + hw->pfnWriteDevRegister(hw->adp, + BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, + BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); + return; + } + + /* Disable the AVD, ARM and BLINK clocks*/ + /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + + regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regValE);*/ + + /* turn on self-refresh */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); + regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); + + /* Issue refresh cycle */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); + + /* Stop Refresh Cycles from controller */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); + regVal &= ~(BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK); + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); + + /* Check if we are in self-refresh. Continue even if we are no since worst case this would just mean higher power consumption */ + pollCnt=0; + while(pollCnt++ < 100) + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); + + if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) + break; + } + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + + regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); + + /* Power down PHY and stop clocks on DRAM */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + + regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + + regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); + regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); + regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); + regVal |= BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK | + BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK | + BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + regVal |= BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); + regVal |= BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); + + /* Finally clock off the DRAM controller */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + regVal |= BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); + + /* udelay(20); */ + + /*printk("RT Power Down Flea Complete\n"); */ + + /* Measure how much time we spend in idle */ + rdtscll(hw->TickStartInPD); + + return; +} + +bool crystalhd_flea_detect_fw_alive(struct crystalhd_hw *hw) +{ + uint32_t pollCnt = 0; + uint32_t hbCnt = 0; + uint32_t heartBeatReg1 = 0; + uint32_t heartBeatReg2 = 0; + bool bRetVal = false; + + heartBeatReg1 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); + while(1) + { + heartBeatReg2 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); + if(heartBeatReg1 != heartBeatReg2) { + hbCnt++; + heartBeatReg1 = heartBeatReg2; + } + + if(hbCnt >= HEART_BEAT_POLL_CNT) { + bRetVal = true; + break; + } + + pollCnt++; + if(pollCnt >= FLEA_MAX_POLL_CNT) { + bRetVal = false; + break; + } + + msleep_interruptible(1); + } + + return bRetVal; +} + +void crystalhd_flea_handle_PicQSts_intr(struct crystalhd_hw *hw) +{ + uint32_t newChBitmap=0; + + newChBitmap = hw->pfnReadDevRegister(hw->adp, RX_DMA_PIC_QSTS_MBOX); + + hw->PicQSts = newChBitmap; + + /* -- For link we were enabling the capture on format change + -- For Flea, we will get a PicQSts interrupt where we will + -- enable the capture. */ + + if(hw->RxCaptureState != 1) + { + hw->RxCaptureState = 1; + } +} + +void crystalhd_flea_update_tx_buff_info(struct crystalhd_hw *hw) +{ + TX_INPUT_BUFFER_INFO TxBuffInfo; + uint32_t ReadSzInDWords=0; + + ReadSzInDWords = (sizeof(TxBuffInfo) - sizeof(TxBuffInfo.Reserved))/4; + hw->pfnDevDRAMRead(hw, hw->TxBuffInfoAddr, ReadSzInDWords, (uint32_t*)&TxBuffInfo); + + if(TxBuffInfo.DramBuffAdd % 4) + { + printk("Tx Err:: DWORD UNAligned Tx Addr. Not Updating\n"); + return; + } + + hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd; + hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes; + hw->TxFwInputBuffInfo.Flags = TxBuffInfo.Flags; + hw->TxFwInputBuffInfo.HostXferSzInBytes = TxBuffInfo.HostXferSzInBytes; + hw->TxFwInputBuffInfo.SeqNum = TxBuffInfo.SeqNum; + + return; +} + +/* was HWFleaNotifyFllChange */ +void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) +{ + unsigned long flags = 0; + uint32_t freeListLen = 0; + /* + * When we are doing the cleanup we should update DRAM only if the + * firmware is running. So Detect the heart beat. + */ + if(bCleanupContext && (!crystalhd_flea_detect_fw_alive(hw))) + return; + + spin_lock_irqsave(&hw->lock, flags); + freeListLen = crystalhd_dioq_count(hw->rx_freeq); + hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &freeListLen); + spin_unlock_irqrestore(&hw->lock, flags); + + return; +} + + +static +void crystalhd_flea_init_power_state(struct crystalhd_hw *hw) +{ + hw->FleaEnablePWM = false; /* enable by default */ + hw->FleaPowerState = FLEA_PS_NONE; +} + +static +bool crystalhd_flea_set_power_state(struct crystalhd_hw *hw, + enum FLEA_POWER_STATES NewState) +{ + bool StChangeSuccess=false; + uint32_t tempFLL = 0; + uint32_t freeListLen = 0; + BC_STATUS sts; + struct crystalhd_rx_dma_pkt *rx_pkt = NULL; + + freeListLen = crystalhd_dioq_count(hw->rx_freeq); + + switch(NewState) + { + case FLEA_PS_ACTIVE: + { + /*Transition to Active State*/ + if(hw->FleaPowerState == FLEA_PS_LP_PENDING) + { + StChangeSuccess = true; + hw->FleaPowerState = FLEA_PS_ACTIVE; + /* Write the correct FLL to FW */ + hw->pfnDevDRAMWrite(hw, + hw->FleaFLLUpdateAddr, + 1, + &freeListLen); + /* We need to check to post here because we may never get a context to post otherwise */ + if(hw->PicQSts != 0) + { + rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); + if (rx_pkt) + sts = hw->pfnPostRxSideBuff(hw, rx_pkt); + } + /*printk(" Success\n"); */ + + }else if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE){ + crystalhd_flea_runtime_power_up(hw); + StChangeSuccess = true; + hw->FleaPowerState = FLEA_PS_ACTIVE; + /* Write the correct FLL to FW */ + hw->pfnDevDRAMWrite(hw, + hw->FleaFLLUpdateAddr, + 1, + &freeListLen); + /* Now check if we missed processing PiQ and TXFIFO interrupts when we were in power down */ + if (hw->PwrDwnPiQIntr) + { + crystalhd_flea_handle_PicQSts_intr(hw); + hw->PwrDwnPiQIntr = false; + } + /* We need to check to post here because we may never get a context to post otherwise */ + if(hw->PicQSts != 0) + { + rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); + if (rx_pkt) + sts = hw->pfnPostRxSideBuff(hw, rx_pkt); + } + if (hw->PwrDwnTxIntr) + { + crystalhd_flea_update_tx_buff_info(hw); + hw->PwrDwnTxIntr = false; + } + + } + break; + } + + case FLEA_PS_LP_PENDING: + { + if(hw->FleaPowerState != FLEA_PS_ACTIVE) + { + break; + } + + /*printk(" Success\n"); */ + + StChangeSuccess = true; + /* Write 0 FLL to FW to prevent it from sending PQ*/ + hw->pfnDevDRAMWrite(hw, + hw->FleaFLLUpdateAddr, + 1, + &tempFLL); + hw->FleaPowerState = FLEA_PS_LP_PENDING; + break; + } + + case FLEA_PS_LP_COMPLETE: + { + if( (hw->FleaPowerState == FLEA_PS_ACTIVE) || + (hw->FleaPowerState == FLEA_PS_LP_PENDING)) { + /* Write 0 FLL to FW to prevent it from sending PQ*/ + hw->pfnDevDRAMWrite(hw, + hw->FleaFLLUpdateAddr, + 1, + &tempFLL); + crystalhd_flea_runtime_power_dn(hw); + StChangeSuccess = true; + hw->FleaPowerState = FLEA_PS_LP_COMPLETE; + + } + break; + } + default: + break; + } + + return StChangeSuccess; +} + +/* +* Look At Different States and List Status and decide on +* Next Logical State To Be In. +*/ +static +void crystalhd_flea_set_next_power_state(struct crystalhd_hw *hw, + enum FLEA_STATE_CH_EVENT PowerEvt) +{ + enum FLEA_POWER_STATES NextPS; + NextPS = hw->FleaPowerState; + + if( hw->FleaEnablePWM == false ) + { + hw->FleaPowerState = FLEA_PS_ACTIVE; + return; + } + +/* printk("Trying Power State Transition from %x Because Of Event:%d \n", */ +/* hw->FleaPowerState, */ +/* PowerEvt); */ + + if(PowerEvt == FLEA_EVT_STOP_DEVICE) + { + hw->FleaPowerState = FLEA_PS_STOPPED; + return; + } + + if(PowerEvt == FLEA_EVT_START_DEVICE) + { + hw->FleaPowerState = FLEA_PS_ACTIVE; + return; + } + + switch(hw->FleaPowerState) + { + case FLEA_PS_ACTIVE: + { + if(PowerEvt == FLEA_EVT_FLL_CHANGE) + { + /*Ready List Was Decremented. */ + /*printk("1:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", */ + /* hw->TxList0Sts, */ + /* hw->TxList1Sts, */ + /* hw->EmptyCnt, */ + /* hw->rx_list_sts[0], */ + /* hw->rx_list_sts[1], */ + /* hw->FwCmdCnt); */ + + if( (hw->TxList0Sts == ListStsFree) && + (hw->TxList1Sts == ListStsFree) && + (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ + (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ + (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && + (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && + (!hw->FwCmdCnt)) + { + NextPS = FLEA_PS_LP_COMPLETE; + }else{ + NextPS = FLEA_PS_LP_PENDING; + } + } + + break; + } + + case FLEA_PS_LP_PENDING: + { + if( (PowerEvt == FLEA_EVT_FW_CMD_POST) || + (PowerEvt == FLEA_EVT_FLL_CHANGE)) + { + NextPS = FLEA_PS_ACTIVE; + }else if(PowerEvt == FLEA_EVT_CMD_COMP){ + + /*printk("2:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x STAppFIFOEmpty:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", */ + /* hw->TxList0Sts, */ + /* hw->TxList1Sts, */ + /* hw->EmptyCnt, */ + /* hw->SingleThreadAppFIFOEmpty, */ + /* hw->rx_list_sts[0], */ + /* hw->rx_list_sts[1], */ + /* hw->FwCmdCnt); */ + + if( (hw->TxList0Sts == ListStsFree) && + (hw->TxList1Sts == ListStsFree) && + (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ + (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ + (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && + (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && + (!hw->FwCmdCnt)) + { + NextPS = FLEA_PS_LP_COMPLETE; + } + } + break; + } + case FLEA_PS_LP_COMPLETE: + { + if( (PowerEvt == FLEA_EVT_FLL_CHANGE) || + (PowerEvt == FLEA_EVT_FW_CMD_POST)) + { + NextPS = FLEA_PS_ACTIVE; + } + + break; + } + default: + { + printk("Invalid Flea Power State %x\n", + hw->FleaPowerState); + + break; + } + } + + if(hw->FleaPowerState != NextPS) + { + printk("%s:State Transition [FromSt:%x ToSt:%x] Because Of Event:%d \n", + __FUNCTION__, + hw->FleaPowerState, + NextPS, + PowerEvt); + + crystalhd_flea_set_power_state(hw,NextPS); + } + + return; +} + +/* was FleaSetRxPicFireAddr */ +#if 0 +static +void crystalhd_flea_set_rx_pic_fire_addr(struct crystalhd_hw *hw, uint32_t BorshContents) +{ + hw->FleaRxPicDelAddr = BorshContents + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; + hw->FleaFLLUpdateAddr = BorshContents + 1 + HOST_TO_FW_FLL_ADDR; + + return; +} +#endif + +void crystalhd_flea_init_temperature_measure (struct crystalhd_hw *hw, bool bTurnOn) +{ + hw->TemperatureRegVal=0; + + if(bTurnOn) { + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x3); + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x203); + } else { + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x103); + } + + return; +} + +/* was HwFleaUpdateTempInfo */ +void crystalhd_flea_update_temperature(struct crystalhd_hw *hw) +{ + uint32_t regVal = 0; + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_TEMP_MON_STATUS); + hw->TemperatureRegVal = regVal; + + return; +} + +/** +* crystalhd_flea_download_fw - Write data to DRAM area. +* @adp: Adapter instance +* @pBuffer: Buffer pointer for the FW data. +* @buffSz: data size in bytes. +* +* Return: +* Status. +* +* Flea firmware download routine. +*/ +BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw *hw, uint8_t *pBuffer, uint32_t buffSz) +{ + uint32_t pollCnt=0,regVal=0; + uint32_t borchStachAddr=0; + uint32_t *pCmacSig=NULL,cmacOffset=0,i=0; + /*uint32_t BuffSz = (BuffSzInDWords * 4); */ + /*uint32_t HBCnt=0; */ + + bool bRetVal = true; + bool bSecure = true; // Default production cards. Can be false only for internal Broadcom dev cards + + dev_dbg(&hw->adp->pdev->dev, "[%s]: Sz:%d\n", __func__, buffSz); + +/* + *-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING + *-- Step 2. Poll for SCRAM_KEY_DONE_INT. + *-- Step 3. Write the BORCH and STARCH addresses. + *-- Step 4. Write the firmware to DRAM. + *-- Step 5. Write the CMAC to SCRUB->CMAC registers. + *-- Step 6. Write the ARM run bit to 1. + *-- Step 7. Poll for BOOT verification done interrupt. + */ + + /* First validate that we got data in the FW buffer */ + if (buffSz == 0) + return BC_STS_ERROR; + +/*-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING. */ +/* Can we set both the bits at the same time?? Security Arch Doc describes the steps */ +/* and the first step is to enable scrubbing and then scrambling. */ + + if(bSecure) + { + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 1. Enable scrubbing\n"); + + /* Enable Scrubbing */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE); + regVal |= SCRUB_ENABLE_BIT; + hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); + + /* Enable Scrambling */ + regVal |= DRAM_SCRAM_ENABLE_BIT; + hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); + + + //-- Step 2. Poll for SCRAM_KEY_DONE_INT. + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Poll for SCRAM_KEY_DONE_INT\n"); + + pollCnt=0; + while(pollCnt < FLEA_MAX_POLL_CNT) + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); + + if(regVal & SCRAM_KEY_DONE_INT_BIT) + break; + + pollCnt++; + msleep_interruptible(1); /*1 Milli Sec delay*/ + } + + /* -- Will Assert when we do not see SCRAM_KEY_DONE_INTERRUPT */ + if(!(regVal & SCRAM_KEY_DONE_INT_BIT)) + { + dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Did not get scram key done interrupt.\n"); + return BC_STS_ERROR; + } + } + + /*Clear the interrupts by writing the register value back*/ + regVal &= 0x00FFFFFF; /*Mask off the reserved bits.[24-31] */ + hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); + +/*-- Step 3. Write the BORCH and STARCH addresses. */ + borchStachAddr = GetScrubEndAddr(buffSz); + if(!bSecure) + borchStachAddr = (buffSz - 1) & BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, borchStachAddr); + hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, borchStachAddr); + + /* + * Now the command address is + * relative to firmware file size. + */ + /*FWIFSetFleaCmdAddr(pHWExt->pFwExt, */ + /* borchStachAddr+1+DDRADDR_4_FWCMDS); */ + + hw->fwcmdPostAddr = borchStachAddr+1+DDRADDR_4_FWCMDS; + hw->fwcmdPostMbox = FW_CMD_POST_MBOX; + hw->fwcmdRespMbox = FW_CMD_RES_MBOX; + /*FleaSetRxPicFireAddr(pHWExt,borchStachAddr); */ + hw->FleaRxPicDelAddr = borchStachAddr + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; + hw->FleaFLLUpdateAddr = borchStachAddr + 1 + HOST_TO_FW_FLL_ADDR; + + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 3. Write the BORCH and STARCH addresses. %x:%x, %x:%x\n", + BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, + borchStachAddr, + BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, + borchStachAddr ); + +/*-- Step 4. Write the firmware to DRAM. [Without the Signature, 32-bit access to DRAM] */ + + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 4. Write the firmware to DRAM. Sz:%d Bytes\n", + buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE); + + if(bSecure) + hw->pfnDevDRAMWrite(hw, FW_DOWNLOAD_START_ADDR, (buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE)/4, (uint32_t *)pBuffer); + else + hw->pfnDevDRAMWrite(hw, FW_DOWNLOAD_START_ADDR, buffSz/4, (uint32_t*)pBuffer); + +/* -- Step 5. Write the signature to CMAC register. */ +/* +-- This is what we need to write to CMAC registers. +================================================================================== +Register Offset Boot Image CMAC + Value +================================================================================== +BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c CMAC Bits[31:0] +BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 CMAC Bits[63:32] +BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 CMAC Bits[95:64] +BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 CMAC Bits[127:96] +================================================================================== +*/ + + if(bSecure) + { + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 5. Write the signature to CMAC register.\n"); + cmacOffset = buffSz - FLEA_FW_SIG_LEN_IN_BYTES; + pCmacSig = (uint32_t *) &pBuffer[cmacOffset]; + + for(i=0;i < FLEA_FW_SIG_LEN_IN_DWORD;i++) + { + uint32_t offSet = (BCHP_SCRUB_CTRL_BI_CMAC_127_96 - (i * 4)); + + hw->pfnWriteDevRegister(hw->adp, offSet, cpu_to_be32(*pCmacSig)); + + pCmacSig++; + } + } + +/*-- Step 6. Write the ARM run bit to 1. */ +/* We need a write back because we do not want to change other bits */ + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 6. Write the ARM run bit to 1.\n"); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL); + regVal |= ARM_RUN_REQ_BIT; + hw->pfnWriteDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL, regVal); + + if(bSecure) + { + /* -- Step 7. Poll for Boot Verification done/failure interrupt.*/ + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Poll for Boot Verification done/failure interrupt.\n"); + pollCnt=0; + while(1) + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); + + if(regVal & BOOT_VER_FAIL_BIT ) + { + dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Error bit occured. RetVal:%x\n", regVal); + + bRetVal = false; + break; + } + + if(regVal & BOOT_VER_DONE_BIT) + { + dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Done RetVal:%x\n", regVal); + + bRetVal = true; /*This is the only place we return TRUE from*/ + break; + } + + pollCnt++; + if( pollCnt >= FLEA_MAX_POLL_CNT ) + { + dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Both done and failure bits are not set.\n"); + bRetVal = false; + break; + } + + msleep_interruptible(5); /*5 Milli Sec delay*/ + } + + if( !bRetVal ) + { + dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Firmware image signature failure.\n"); + return BC_STS_ERROR; + } + + /*Clear the interrupts by writing the register value back*/ + regVal &= 0x00FFFFFF; //Mask off the reserved bits.[24-31] + hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); + + msleep_interruptible(10); /*10 Milli Sec delay*/ + } + else + bRetVal = true; + + /* + -- It was seen on Dell390 systems that the firmware command was fired before the + -- firmware was actually ready to accept the firmware commands. The driver did + -- not recieve a response for the firmware commands and this was causing the DIL to timeout + -- ,reclaim the resources and crash. The following code looks for the heartbeat and + -- to make sure that we return from this function only when we get the heart beat making sure + -- that the firmware is running. + */ + + bRetVal = crystalhd_flea_detect_fw_alive(hw); + if( !bRetVal ) + { + dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 8. Detect firmware heart beat failed.\n"); + return BC_STS_ERROR; + } + + dev_dbg(&hw->adp->pdev->dev, "[%s]: Complete.\n", __func__); + return BC_STS_SUCCESS; +} + +bool crystalhd_flea_start_device(struct crystalhd_hw *hw) +{ + uint32_t regVal = 0; + bool bRetVal = false; + + /* + -- Issue Core reset to bring in the default values in place + */ + crystalhd_flea_core_reset(hw); + + /* + -- If the gisb arbitar register is not set to some other value + -- and the firmware crashes, we see a NMI since the hardware did + -- not respond to a register read at all. The PCI-E trace confirms the problem. + -- Right now we are setting the register values to 0x7e00 and will check later + -- what should be the correct value to program. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); + + /* + -- Disable all interrupts + */ + crystalhd_flea_clear_interrupts(hw); + crystalhd_flea_disable_interrupts(hw); + + /* + -- Enable the option for getting the done count in + -- Rx DMA engine. + */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG); + regVal |= 0x10; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG, regVal); + + /* + -- Enable the TX DMA Engine once on startup. + -- This is a new bit added. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x01); + + /* + -- Enable the RX3 DMA Engine once on startup. + -- This is a new bit added. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x01); + + /* + -- Set the Run bit for RX-Y and RX-UV DMA engines. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x01); + + /* + -- Make sure Early L1 is disabled - NAREN - This will not prevent the device from entering L1 under active mode + */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL); + regVal &= ~BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL, regVal); + + crystalhd_flea_init_dram(hw); + + msleep_interruptible(5); + + /* Enable the Single Shot Transaction on PCI by disabling the */ + /* bit 29 of transaction configuration register */ + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION); + regVal &= (~(BC_BIT(29))); + hw->pfnWriteDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION, regVal); + + crystalhd_flea_init_temperature_measure(hw,true); + + crystalhd_flea_init_power_state(hw); + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_START_DEVICE); + + /* + -- Enable all interrupts + */ + crystalhd_flea_clear_interrupts(hw); + crystalhd_flea_enable_interrupts(hw); + + /* + -- This is the only time we set this pointer for Flea. + -- Since there is no stop the pointer is not reset anytime.... + -- except for fatal errors. + */ + hw->rx_list_post_index = 0; + hw->RxCaptureState = 0; + + msleep_interruptible(1); + + return bRetVal; +} + + +bool crystalhd_flea_stop_device(struct crystalhd_hw *hw) +{ + uint32_t regVal=0, pollCnt=0; + + /* + -- Issue the core reset so that we + -- make sure there is nothing running. + */ + crystalhd_flea_core_reset(hw); + + crystalhd_flea_init_temperature_measure(hw, false); + + /* + -- If the gisb arbitrater register is not set to some other value + -- and the firmware crashes, we see a NMI since the hardware did + -- not respond to a register read at all. The PCI-E trace confirms the problem. + -- Right now we are setting the register values to 0x7e00 and will check later + -- what should be the correct value to program. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); + + /* + -- Disable the TX DMA Engine once on shutdown. + -- This is a new bit added. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x0); + + /* + -- Disable the RX3 DMA Engine once on Stop. + -- This is a new bit added. + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x0); + + /* + -- Clear the RunStop Bit For RX DMA Control + */ + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x0); + + hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, 0x0); + + /* * Wait for MEMC to become idle */ + pollCnt=0; + while (1) + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); + + if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) + break; + + pollCnt++; + if(pollCnt >= 100) + break; + + msleep_interruptible(1); + } + + /*First Disable the AVD and ARM before disabling the DRAM*/ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + + regVal = BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); + + /* + -- Disable the interrupt after disabling the ARM and AVD. + -- We should be able to access the registers because we still + -- have not disabled the clock for blink block. We disable the + -- blick 108 abd 216 clock at the end of this function. + */ + crystalhd_flea_clear_interrupts(hw); + crystalhd_flea_disable_interrupts(hw); + + /*Now try disabling the DRAM.*/ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); + + regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; + + /* * disable CKE */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); + + /* * issue refresh command */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); + + pollCnt=0; + while(1) + { + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); + + if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) + break; + + pollCnt++; + if(pollCnt >= 100) + break; + + msleep_interruptible(1); + } + + /* * Enable DDR clock, DM and READ_ENABLE pads power down and force into the power down */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | + BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK); + + /* * Power down BL LDO cells */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, + BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, + BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); + + /* * Enable DDR control signal pad power down and force into the power down */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, + BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | + BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK); + + /* * Disable ddr phy clock */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, + BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); + + /* * Disable PLL output */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, + regVal & ~BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK); + + /* * Power down addr_ctl LDO cells */ + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, + BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); + + /* * Power down the PLL */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); + + hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, + regVal | BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); + + /* shut down the PLL1 */ + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL); + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL, + regVal | BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK); + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL0_ARM_DIV, 0xff); + + regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); + + regVal |= BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK | + BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK | + BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK | + BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK; + + hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); + + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_STOP_DEVICE); + return true; +} + +bool +crystalhd_flea_wake_up_hw(struct crystalhd_hw *hw) +{ + if(hw->FleaPowerState != FLEA_PS_ACTIVE) + { + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); + } + + /* Now notify HW of the number of entries in the Free List */ + /* This starts up the channel bitmap delivery */ + crystalhd_flea_notify_fll_change(hw, false); + + hw->WakeUpDecodeDone = true; + + return true; +} + +bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags) +{ + uint32_t regVal=0; + TX_INPUT_BUFFER_INFO *pTxBuffInfo; + uint32_t FlagsAddr=0; + + *empty_sz = 0; +/* *DramAddrOut=0; */ + + + /* Add condition here to wake up the HW in case some application is trying to do TX before starting RX - like FP */ + /* To prevent deadlocks. We are called here from Synchronized context so we can safely call this directly */ + + if(hw->WakeUpDecodeDone != true) + { + /* Only wake up the HW if we are either being called from a single threaded app - like FP */ + /* or if we are not checking for the input buffer size as just a test */ + if(*flags == 0) + crystalhd_flea_wake_up_hw(hw); + else { + *empty_sz = 2 * 1024 * 1024; /* FW Buffer size */ + /**DramAddrOut=0; */ + *flags=0; + return false; + } + } + + /* if we have told the app that we have buffer empty then we cannot go to low power */ + if((hw->FleaPowerState != FLEA_PS_ACTIVE) && !hw->SingleThreadAppFIFOEmpty) + { + /**TxBuffSzOut=0; */ + /**DramAddrOut=0; */ + *empty_sz = 0; + *flags=0; + /*printk("PD can't Tx\n"); */ + return true; /*Indicate FULL*/ + } + + + if(hw->TxFwInputBuffInfo.Flags & DFW_FLAGS_TX_ABORT) + { + *empty_sz=0; + /**DramAddrOut=0; */ + *flags |= DFW_FLAGS_TX_ABORT; + return true; + } + + if( (hw->TxFwInputBuffInfo.DramBuffSzInBytes < needed_sz) + ||(!hw->TxFwInputBuffInfo.DramBuffAdd)) + { + *empty_sz=0; + /**DramAddrOut=0; */ + *flags=0; + return true; /*Indicate FULL*/ + } + + if(hw->TxFwInputBuffInfo.DramBuffAdd % 4) + { + /* + -- Indicate Full if we get a non-dowrd aligned address. + -- This will avoid us posting the command to firmware and + -- The TX will timeout and we will close the application properly. + -- This avoids a illegal operation as far as the TX is concerned. + */ + printk("TxSDRAM-Destination Address Not DWORD Aligned:%x\n",hw->TxFwInputBuffInfo.DramBuffAdd); + return true; + } + + /* + -- We got everything correctly from the firmware and hence we should be + -- able to do the DMA. Indicate what app wants to hear. + -- Firmware SAYS: I AM HUNGRY, GIVE ME FOOD. :) + */ + *empty_sz=hw->TxFwInputBuffInfo.DramBuffSzInBytes; + /**dramAddrOut=pHWExt->TxFwInputBuffInfo.DramBuffAdd; */ +/* printk("empty size is %d\n", *empty_sz); */ + + /* If we are just checking stats and are not actually going to DMA, don't increment */ + /* But we have to account for single threaded apps */ + if((*flags & 0x08) == 0x08) + { + /* This is a synchronized function */ + /* NAREN - In single threaded mode, if we have less than a defined size of buffer */ + /* ask the firmware to wrap around. To prevent deadlocks. */ + if(hw->TxFwInputBuffInfo.DramBuffSzInBytes < TX_WRAP_THRESHOLD) + { + pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); + FlagsAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->Flags)); + /* Read Modify the Flags to ask the FW to WRAP */ + hw->pfnDevDRAMRead(hw,FlagsAddr,1,®Val); + regVal |= DFW_FLAGS_WRAP; + hw->pfnDevDRAMWrite(hw,FlagsAddr,1,®Val); + + /* Indicate Busy to the application because we have to get new buffers from FW */ + *empty_sz=0; + /* *DramAddrOut=0; */ + *flags=0; + /* Wait for the next interrupt from the HW */ + hw->TxFwInputBuffInfo.DramBuffSzInBytes = 0; + hw->TxFwInputBuffInfo.DramBuffAdd = 0; + return true; + } + else + hw->SingleThreadAppFIFOEmpty = true; + } + else if((*flags & 0x04) != 0x04) + hw->EmptyCnt++; /*OS_INTERLOCK_INCREMENT(&pHWExt->EmptyCnt); */ + + /* Different from our Windows implementation */ + /* set bit 7 of the flags field to indicate that we have to use the destination address for TX */ + *flags |= BC_BIT(7); + + return false; /*Indicate Empty*/ +} + +BC_STATUS crystalhd_flea_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) +{ + BC_STATUS sts = BC_STS_SUCCESS; + struct DecRspChannelStartVideo *st_rsp = NULL; + struct C011_TS_CMD *pGenRsp = NULL; + struct DecRspChannelChannelOpen *pRsp = NULL; + + pGenRsp = (struct C011_TS_CMD *) fw_cmd->rsp; + + switch (fw_cmd->cmd[0]) { + case eCMD_C011_DEC_CHAN_STREAM_OPEN: + hw->channelNum = pGenRsp->ulParams[2]; + + dev_dbg(&hw->adp->pdev->dev, "Snooped Stream Open Cmd For ChNo:%x\n", hw->channelNum); + break; + case eCMD_C011_DEC_CHAN_OPEN: + pRsp = (struct DecRspChannelChannelOpen *)pGenRsp; + hw->channelNum = pRsp->ChannelID; + + /* used in Flea to update the Tx Buffer stats */ + hw->TxBuffInfoAddr = pRsp->transportStreamCaptureAddr; + hw->TxFwInputBuffInfo.DramBuffAdd=0; + hw->TxFwInputBuffInfo.DramBuffSzInBytes=0; + hw->TxFwInputBuffInfo.Flags=0; + hw->TxFwInputBuffInfo.HostXferSzInBytes=0; + hw->TxFwInputBuffInfo.SeqNum=0; + + /* NAREN Init power management states here when we start the channel */ + hw->PwrDwnTxIntr = false; + hw->PwrDwnPiQIntr = false; + hw->EmptyCnt = 0; + hw->SingleThreadAppFIFOEmpty = false; + + dev_dbg(&hw->adp->pdev->dev, "Snooped ChOpen Cmd For ChNo:%x TxBuffAddr:%x\n", + hw->channelNum, + hw->TxBuffInfoAddr); + break; + case eCMD_C011_DEC_CHAN_START_VIDEO: + st_rsp = (struct DecRspChannelStartVideo *)fw_cmd->rsp; + hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; + hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; + + dev_dbg(&hw->adp->pdev->dev, "Snooping CHAN_START_VIDEO command to get the Addr of Del/Rel Queue\n"); + dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", + hw->pib_del_Q_addr, hw->pib_rel_Q_addr); + break; + default: + break; + } + return sts; +} + +BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) +{ + struct device *dev; + uint32_t cnt = 0, cmd_res_addr; + uint32_t *cmd_buff, *res_buff; + wait_queue_head_t fw_cmd_event; + int rc = 0; + BC_STATUS sts; + unsigned long flags; + + crystalhd_create_event(&fw_cmd_event); + + if (!hw || !fw_cmd) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "%s entered\n", __func__); + + cmd_buff = fw_cmd->cmd; + res_buff = fw_cmd->rsp; + + if (!cmd_buff || !res_buff) { + dev_err(dev, "Invalid Parameters for F/W Command\n"); + return BC_STS_INV_ARG; + } + + hw->fwcmd_evt_sts = 0; + hw->pfw_cmd_event = &fw_cmd_event; + hw->FwCmdCnt++; + + if(hw->FleaPowerState != FLEA_PS_ACTIVE) + { + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FW_CMD_POST); + } + + spin_lock_irqsave(&hw->lock, flags); + + /*Write the command to the memory*/ + hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); + + /*Memory Read for memory arbitrator flush*/ + hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); + + /* Write the command address to mailbox */ + hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); + + spin_unlock_irqrestore(&hw->lock, flags); + + msleep_interruptible(50); + + /* FW commands should complete even if we got a signal from the upper layer */ + crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, + 20000, rc, true); + + if (!rc) { + sts = BC_STS_SUCCESS; + } else if (rc == -EBUSY) { + dev_err(dev, "Firmware command T/O\n"); + sts = BC_STS_TIMEOUT; + } else if (rc == -EINTR) { + dev_info(dev, "FwCmd Wait Signal - Can Never Happen\n"); + sts = BC_STS_IO_USER_ABORT; + } else { + dev_err(dev, "FwCmd IO Error.\n"); + sts = BC_STS_IO_ERROR; + } + + if (sts != BC_STS_SUCCESS) { + dev_err(dev, "FwCmd Failed.\n"); + return sts; + } + + spin_lock_irqsave(&hw->lock, flags); + + /*Get the Responce Address*/ + cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); + + /*Read the Response*/ + hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); + + spin_unlock_irqrestore(&hw->lock, flags); + + if (res_buff[2] != 0) { + dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); + return BC_STS_FW_CMD_ERR; + } + + sts = crystalhd_flea_fw_cmd_post_proc(hw, fw_cmd); + if (sts != BC_STS_SUCCESS) + dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); + + return sts; + +} + +void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) +{ + uint32_t y_dn_sz_reg, uv_dn_sz_reg; + + if (!list_index) { + y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT; + uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT; + } else { + y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT; + uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT; + } + + *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); + *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); + + return ; +} + +BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state) +{ + /*printk("%s: Set flea to power down.\n", __func__); */ + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); + return BC_STS_SUCCESS; +} + +bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth) +{ + unsigned long flags = 0; + struct crystalhd_dioq *ioq; + struct crystalhd_elem *tmp; + struct crystalhd_rx_dma_pkt *rpkt; + + *meta_payload = 0; + + ioq = hw->rx_rdyq; + spin_lock_irqsave(&ioq->lock, flags); + + if ((ioq->count > 0) && (ioq->head != (struct crystalhd_elem *)&ioq->head)) { + tmp = ioq->head; + spin_unlock_irqrestore(&ioq->lock, flags); + rpkt = (struct crystalhd_rx_dma_pkt *)tmp->data; + if (rpkt) { + flea_GetPictureInfo(hw, rpkt, picNumFlags, meta_payload); + /*printk("%s: flea_GetPictureInfo Pic#:%d\n", __func__, PicNumber); */ + } + return true; + } + spin_unlock_irqrestore(&ioq->lock, flags); + + return false; + +} + +void crystalhd_flea_clear_rx_errs_intrs(struct crystalhd_hw *hw) +/* +-- Clears all the errors and interrupt on RX DMA engine. +*/ +{ + uint32_t ulRegVal; + union FLEA_INTR_BITS_COMMON IntrToClear,IntrSts; + + IntrToClear.WholeReg = 0; + IntrSts.WholeReg = 0; + + IntrSts.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); + if(IntrSts.WholeReg) + { + ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, ulRegVal); + ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, ulRegVal); + + IntrToClear.L0UVRxDMADone = IntrSts.L0UVRxDMADone; + IntrToClear.L0UVRxDMAErr = IntrSts.L0UVRxDMAErr; + IntrToClear.L0YRxDMADone = IntrSts.L0YRxDMADone; + IntrToClear.L0YRxDMAErr = IntrSts.L0YRxDMAErr; + IntrToClear.L1UVRxDMADone = IntrSts.L1UVRxDMADone; + IntrToClear.L1UVRxDMAErr = IntrSts.L1UVRxDMAErr; + IntrToClear.L1YRxDMADone = IntrSts.L1YRxDMADone; + IntrToClear.L1YRxDMAErr = IntrSts.L1YRxDMAErr; + + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrToClear.WholeReg); + + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); + } + return; +} + + +void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw) +{ + union FLEA_INTR_BITS_COMMON IntrStsValue; + bool failedL0 = true, failedL1 = true; + uint32_t pollCnt = 0; + + hw->RxCaptureState = 2; + + if((hw->rx_list_sts[0] == sts_free) && (hw->rx_list_sts[1] == sts_free)) { + hw->RxCaptureState = 0; + hw->RxSeqNum = 0; + return; /* Nothing to be done */ + } + + if(hw->rx_list_sts[0] == sts_free) + failedL0 = false; + if(hw->rx_list_sts[1] == sts_free) + failedL1 = false; + + while(1) + { + IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); + + if(hw->rx_list_sts[0] != sts_free) { + if( (IntrStsValue.L0YRxDMADone) || (IntrStsValue.L0YRxDMAErr) || + (IntrStsValue.L0UVRxDMADone) || (IntrStsValue.L0UVRxDMAErr) ) + { + failedL0 = false; + } + } + else + failedL0 = false; + + if(hw->rx_list_sts[1] != sts_free) { + if( (IntrStsValue.L1YRxDMADone) || (IntrStsValue.L1YRxDMAErr) || + (IntrStsValue.L1UVRxDMADone) || (IntrStsValue.L1UVRxDMAErr) ) + { + failedL1 = false; + } + } + else + failedL1 = false; + + msleep_interruptible(10); + + if(pollCnt >= MAX_VALID_POLL_CNT) + break; + + if((failedL0 == false) && (failedL1 == false)) + break; + + pollCnt++; + } + + if(failedL0 || failedL1) + printk("Failed to stop RX DMA\n"); + + hw->RxCaptureState = 0; + hw->RxSeqNum = 0; + + crystalhd_flea_clear_rx_errs_intrs(hw); +} + +BC_STATUS crystalhd_flea_hw_fire_rxdma(struct crystalhd_hw *hw, + struct crystalhd_rx_dma_pkt *rx_pkt) +{ + struct device *dev; + addr_64 desc_addr; + unsigned long flags; + PIC_DELIVERY_HOST_INFO PicDeliInfo; + uint32_t BuffSzInDwords; + + if (!hw || !rx_pkt) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { + dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); + return BC_STS_INV_ARG; + } + + if(hw->RxCaptureState != 1) { + dev_err(dev, "Capture not enabled\n"); + return BC_STS_BUSY; + } + + spin_lock_irqsave(&hw->rx_lock, flags); + if (hw->rx_list_sts[hw->rx_list_post_index]) { + dev_dbg(dev, "HW list is busy\n"); + spin_unlock_irqrestore(&hw->rx_lock, flags); + return BC_STS_BUSY; + } + + if (!TEST_BIT(hw->PicQSts, hw->channelNum)) { + /* NO pictures available for this channel */ + dev_dbg(dev, "No Picture Available for DMA\n"); + spin_unlock_irqrestore(&hw->rx_lock, flags); + return BC_STS_BUSY; + } + + CLEAR_BIT(hw->PicQSts, hw->channelNum); + + desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; + + PicDeliInfo.ListIndex = hw->rx_list_post_index; + PicDeliInfo.RxSeqNumber = hw->RxSeqNum; + PicDeliInfo.HostDescMemLowAddr_Y = desc_addr.low_part; + PicDeliInfo.HostDescMemHighAddr_Y = desc_addr.high_part; + + if (rx_pkt->uv_phy_addr) { + /* Program the UV descriptor */ + desc_addr.full_addr = rx_pkt->uv_phy_addr; + PicDeliInfo.HostDescMemLowAddr_UV = desc_addr.low_part; + PicDeliInfo.HostDescMemHighAddr_UV = desc_addr.high_part; + } + + rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; + if (rx_pkt->uv_phy_addr) + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; + hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; + + spin_unlock_irqrestore(&hw->rx_lock, flags); + + crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); + + BuffSzInDwords = (sizeof (PicDeliInfo) - sizeof(PicDeliInfo.Reserved))/4; + + /* + -- Write the parameters in DRAM. + */ + spin_lock_irqsave(&hw->lock, flags); + hw->pfnDevDRAMWrite(hw, hw->FleaRxPicDelAddr, BuffSzInDwords, (uint32_t*)&PicDeliInfo); + hw->pfnWriteDevRegister(hw->adp, RX_POST_MAILBOX, hw->channelNum); + spin_unlock_irqrestore(&hw->lock, flags); + + hw->RxSeqNum++; + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) +{ + BC_STATUS sts = crystalhd_flea_hw_fire_rxdma(hw, rx_pkt); + + if (sts != BC_STS_SUCCESS) + crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, false, rx_pkt->pkt_tag); + + hw->pfnNotifyFLLChange(hw, false); + + return sts; +} + +void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) +{ + uint32_t dma_cntrl; + uint32_t first_desc_u_addr, first_desc_l_addr; + TX_INPUT_BUFFER_INFO TxBuffInfo; + uint32_t WrAddr=0, WrSzInDWords=0; + + hw->EmptyCnt--; + hw->SingleThreadAppFIFOEmpty = false; + + /* For FLEA, first update the HW with the DMA parameters */ + WrSzInDWords = (sizeof(TxBuffInfo.DramBuffAdd) + + sizeof(TxBuffInfo.DramBuffSzInBytes) + + sizeof(TxBuffInfo.HostXferSzInBytes))/4; + + /*Make the DramBuffSz as Zero skip first ULONG*/ + WrAddr = hw->TxBuffInfoAddr; + hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd = 0; + hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes = 0; + TxBuffInfo.HostXferSzInBytes = hw->TxFwInputBuffInfo.HostXferSzInBytes; + + hw->pfnDevDRAMWrite(hw, WrAddr, WrSzInDWords, (uint32_t *)&TxBuffInfo); + + if (list_id == 0) { + first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0; + first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0; + } else { + first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1; + first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1; + } + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { + dma_cntrl |= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; + hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); + + hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); + /* Be sure we set the valid bit ^^^^ */ + + return; +} + +BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw) +{ + struct device *dev; + uint32_t dma_cntrl, cnt = 30; + uint32_t l1 = 1, l2 = 1; + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "Stopping TX DMA Engine..\n"); + + if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { + hw->TxList0Sts = ListStsFree; + hw->TxList1Sts = ListStsFree; + hw->tx_list_post_index = 0; + + dev_dbg(dev, "Already Stopped\n"); + return BC_STS_SUCCESS; + } + + crystalhd_flea_disable_interrupts(hw); + + /* Issue stop to HW */ + dma_cntrl &= ~BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; + hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + + dev_dbg(dev, "Cleared the DMA Start bit\n"); + + /* Poll for 3seconds (30 * 100ms) on both the lists..*/ + while ((l1 || l2) && cnt) { + + if (l1) { + l1 = hw->pfnReadFPGARegister(hw->adp, + BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0); + l1 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; + } + + if (l2) { + l2 = hw->pfnReadFPGARegister(hw->adp, + BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1); + l2 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; + } + + msleep_interruptible(100); + + cnt--; + } + + if (!cnt) { + dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); + crystalhd_flea_enable_interrupts(hw); + return BC_STS_ERROR; + } + + hw->TxList0Sts = ListStsFree; + hw->TxList1Sts = ListStsFree; + + hw->tx_list_post_index = 0; + dev_dbg(dev, "stopped TX DMA..\n"); + crystalhd_flea_enable_interrupts(hw); + + return BC_STS_SUCCESS; +} + +static void crystalhd_flea_update_tx_done_to_fw(struct crystalhd_hw *hw) +{ + struct device *dev; + uint32_t regVal = 0; + uint32_t seqNumAddr = 0; + uint32_t seqVal = 0; + TX_INPUT_BUFFER_INFO *pTxBuffInfo; + + dev = &hw->adp->pdev->dev; + /* + -- first update the sequence number and then update the + -- scratch. + */ + pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); + seqNumAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->SeqNum)); + + /*Read the seqnece number */ + hw->pfnDevDRAMRead(hw, seqNumAddr, 1, ®Val); + + seqVal = regVal; + regVal++; + + /*Increment and Write back to same memory location. */ + hw->pfnDevDRAMWrite(hw, seqNumAddr, 1, ®Val); + + regVal = hw->pfnReadDevRegister(hw->adp, INDICATE_TX_DONE_REG); + regVal++; + hw->pfnWriteDevRegister(hw->adp, INDICATE_TX_DONE_REG, regVal); + + dev_dbg(dev, "TxUpdate[SeqNum DRAM Addr:%x] SeqNum:%x ScratchValue:%x\n", + seqNumAddr, seqVal, regVal); + + return; +} + +bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + /* reset list index.*/ + hw->tx_list_post_index = 0; + } + + tmp = err_sts & err_mask; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + /* reset list index.*/ + hw->tx_list_post_index = 0; + } + + tmp = err_sts & err_mask; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts) +{ + uint32_t err_sts; + + if (int_sts.L0TxDMADone) { + hw->TxList0Sts &= ~TxListWaitingForIntr; + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_SUCCESS); + } + + if (int_sts.L1TxDMADone) { + hw->TxList1Sts &= ~TxListWaitingForIntr; + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_SUCCESS); + } + + if (!(int_sts.L0TxDMAErr || int_sts.L1TxDMAErr)) + /* No error mask set.. */ + return; + + /* Handle Tx errors. */ + err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS); + + if (crystalhd_flea_tx_list0_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_ERROR); + + if (crystalhd_flea_tx_list1_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_ERROR); + + hw->stats.tx_errors++; +} + +bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw, + union FLEA_INTR_BITS_COMMON int_sts, + uint32_t y_err_sts, + uint32_t uv_err_sts) +{ + uint32_t tmp; + enum list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[0]; + + /* Y0 - DMA */ + tmp = y_err_sts & GET_Y0_ERR_MSK; + if (int_sts.L0YRxDMADone) + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + /* Can never happen for Flea */ + printk("FLEA fifo full - impossible\n"); + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV0 - DMA */ + tmp = uv_err_sts & GET_UV0_ERR_MSK; + if (int_sts.L0UVRxDMADone) + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + /* Can never happen for Flea */ + printk("FLEA fifo full - impossible\n"); + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y0_ERR_MSK) { + tmp = y_err_sts & GET_Y0_ERR_MSK; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV0_ERR_MSK) { + tmp = uv_err_sts & GET_UV0_ERR_MSK; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[0]); +} + +bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw, + union FLEA_INTR_BITS_COMMON int_sts, + uint32_t y_err_sts, + uint32_t uv_err_sts) +{ + uint32_t tmp; + enum list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[1]; + + /* Y1 - DMA */ + tmp = y_err_sts & GET_Y1_ERR_MSK; + if (int_sts.L1YRxDMADone) + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Can never happen for Flea */ + printk("FLEA fifo full - impossible\n"); + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV1 - DMA */ + tmp = uv_err_sts & GET_UV1_ERR_MSK; + if (int_sts.L1UVRxDMADone) + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Can never happen for Flea */ + printk("FLEA fifo full - impossible\n"); + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y1_ERR_MSK) { + tmp = y_err_sts & GET_Y1_ERR_MSK; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV1_ERR_MSK) { + tmp = uv_err_sts & GET_UV1_ERR_MSK; + hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[1]); +} + +void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON intr_sts) +{ + unsigned long flags; + uint32_t i, list_avail = 0; + BC_STATUS comp_sts = BC_STS_NO_DATA; + uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; + bool ret = 0; + + if (!hw) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return; + } + + if (!(intr_sts.L0YRxDMADone || intr_sts.L1YRxDMADone || intr_sts.L0UVRxDMADone || intr_sts.L1UVRxDMADone || + intr_sts.L0YRxDMAErr || intr_sts.L1YRxDMAErr || intr_sts.L0UVRxDMAErr || intr_sts.L1UVRxDMAErr)) + return; + + spin_lock_irqsave(&hw->rx_lock, flags); + + y_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); + uv_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); + + for (i = 0; i < DMA_ENGINE_CNT; i++) { + /* Update States..*/ + if (i == 0) + ret = crystalhd_flea_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); + else + ret = crystalhd_flea_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); + if (ret) { + switch (hw->rx_list_sts[i]) { + case sts_free: + comp_sts = BC_STS_SUCCESS; + list_avail = 1; + hw->stats.rx_success++; + break; + case rx_y_error: + case rx_uv_error: + case rx_sts_error: + /* We got error on both or Y or uv. */ + hw->stats.rx_errors++; + hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); + dev_info(&hw->adp->pdev->dev, "list_index:%x " + "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " + "UVDnSz:%x\n", i, hw->stats.rx_errors, + hw->stats.rx_errors + hw->stats.rx_success, + y_err_sts, uv_err_sts, intr_sts.WholeReg, + y_dn_sz, uv_dn_sz); + hw->rx_list_sts[i] = sts_free; + comp_sts = BC_STS_ERROR; + break; + default: + /* Wait for completion..*/ + comp_sts = BC_STS_NO_DATA; + break; + } + } + /* handle completion...*/ + if (comp_sts != BC_STS_NO_DATA) { + crystalhd_rx_pkt_done(hw, i, comp_sts); + comp_sts = BC_STS_NO_DATA; + } + } + + spin_unlock_irqrestore(&hw->rx_lock, flags); + + if (list_avail) + crystalhd_hw_start_capture(hw); +} + +bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) +{ + union FLEA_INTR_BITS_COMMON IntrStsValue; + bool bIntFound = false; + bool bPostRxBuff = false; + bool bSomeCmdDone = false; + struct crystalhd_rx_dma_pkt *rx_pkt; + + bool rc = false; + + if (!adp || !hw->dev_started) + return rc; + + IntrStsValue.WholeReg=0; + + IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); + + if(!IntrStsValue.WholeReg) + return rc; /*Not Our interrupt*/ + + /*If any of the bit is set we have a problem*/ + if(IntrStsValue.HaltIntr || IntrStsValue.PcieTgtCaAttn || IntrStsValue.PcieTgtUrAttn) + { + printk("Bad HW Error in CrystalHD Driver\n"); + return rc; + } + + /* Our interrupt */ + hw->stats.num_interrupts++; + rc = true; + + /* NAREN When In Power Down state, only interrupts possible are TXFIFO and PiQ */ + /* Save the state of these interrupts to process them when we resume from power down */ + if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE) + { + if(IntrStsValue.ArmMbox1Int) + { + hw->PwrDwnPiQIntr = true; + bIntFound = true; + } + + if(IntrStsValue.ArmMbox2Int) + { + hw->PwrDwnTxIntr = true; + bIntFound = true; + } + + /*Write End Of Interrupt for PCIE*/ + if(bIntFound) + { + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); + } + return (bIntFound); + } + + /* + -- Arm Mail box Zero interrupt is + -- BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 + */ + if(IntrStsValue.ArmMbox0Int) + { + /*HWFWCmdComplete(pHWExt,IntrBmp); */ + /*Set the Event and the status flag*/ + if (hw->pfw_cmd_event) { + hw->fwcmd_evt_sts = 1; + crystalhd_set_event(hw->pfw_cmd_event); + } + bIntFound = true; + bSomeCmdDone = true; + hw->FwCmdCnt--; + } + + /* Rx interrupts */ + crystalhd_flea_rx_isr(hw, IntrStsValue); + + if( IntrStsValue.L0YRxDMADone || IntrStsValue.L1YRxDMADone || IntrStsValue.L0UVRxDMADone || IntrStsValue.L1UVRxDMADone || IntrStsValue.L0YRxDMAErr || IntrStsValue.L1YRxDMAErr ) + { + bSomeCmdDone = true; + } + + + /* Tx interrupts*/ + crystalhd_flea_tx_isr(hw, IntrStsValue); + + /* + -- Indicate the TX Done to Flea Firmware. + */ + if(IntrStsValue.L0TxDMADone || IntrStsValue.L1TxDMADone || IntrStsValue.L0TxDMAErr || IntrStsValue.L1TxDMAErr) + { + crystalhd_flea_update_tx_done_to_fw(hw); + bSomeCmdDone = true; + } + /* + -- We are doing this here because we processed the interrupts. + -- We might want to change the PicQSts bitmap in any of the interrupts. + -- This should be done before trying to post the next RX buffer. + -- NOTE: ArmMbox1Int is BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 + */ + if(IntrStsValue.ArmMbox1Int) + { + /*pHWExt->FleaBmpIntrCnt++; */ + crystalhd_flea_update_temperature(hw); + crystalhd_flea_handle_PicQSts_intr(hw); + bPostRxBuff = true; + bIntFound = true; + } + + if(IntrStsValue.ArmMbox2Int) + { + crystalhd_flea_update_temperature(hw); + crystalhd_flea_update_tx_buff_info(hw); + bIntFound = true; + } + + /*Write End Of Interrupt for PCIE*/ + if(rc) + { + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); + hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); + } + + /* Try to post RX Capture buffer from ISR context */ + if(bPostRxBuff) { + rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); + if (rx_pkt) + hw->pfnPostRxSideBuff(hw, rx_pkt); + } + + if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) && (bSomeCmdDone)) + { + /*printk("interrupt_handle: current PS:%d, bSomeCmdDone%d\n", hw->FleaPowerState,bSomeCmdDone); */ + crystalhd_flea_set_next_power_state(hw, FLEA_EVT_CMD_COMP); + } + + /* NAREN place the device in low power mode if we have not started playing video */ + /*if((hw->FleaPowerState == FLEA_PS_ACTIVE) && (hw->WakeUpDecodeDone != true)) */ + /*{ */ + /* if((hw->ReadyListLen == 0) && (hw->FreeListLen == 0)) */ + /* { */ + /* crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); */ + /* printk("ISR Idle\n"); */ + /* } */ + /*} */ + + return rc; +} + +/* This function cannot be called from ISR context since it uses APIs that can sleep */ +bool flea_GetPictureInfo(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt * rx_pkt, + uint32_t *PicNumber, uint64_t *PicMetaData) +{ + struct device *dev = &hw->adp->pdev->dev; + uint32_t PicInfoLineNum = 0, offset = 0, size = 0; + PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; + uint32_t tmpYBuffData; + unsigned long res = 0; + uint32_t widthField = 0; + bool rtVal = true; + + void *tmpPicInfo = NULL; + struct crystalhd_dio_req *dio = rx_pkt->dio_req; + *PicNumber = 0; + *PicMetaData = 0; + + if (!dio) + goto getpictureinfo_err_nosem; + +/* if(down_interruptible(&hw->fetch_sem)) */ +/* goto getpictureinfo_err_nosem; */ + + tmpPicInfo = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); /* since copy_from_user can sleep anyway */ + if(tmpPicInfo == NULL) + goto getpictureinfo_err; + dio->pib_va = kmalloc(32, GFP_KERNEL); /* temp buffer of 32 bytes for the rest; */ + if(dio->pib_va == NULL) + goto getpictureinfo_err; + + offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_PIB_DATA_OFFSET_FROM_END; + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); + if (res != 0) + goto getpictureinfo_err; + PicInfoLineNum = *(uint32_t*)(dio->pib_va); + if (PicInfoLineNum > 1092) { + dev_err(dev, "Invalid Line Number[%x], DoneSz:0x%x Bytes\n", + (int)PicInfoLineNum, rx_pkt->dio_req->uinfo.y_done_sz * 4); + goto getpictureinfo_err; + } + + offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_WIDTH_OFFSET_FROM_END; + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); + if (res != 0) + goto getpictureinfo_err; + widthField = *(uint32_t*)(dio->pib_va); + + hw->PICWidth = widthField & 0x3FFFFFFF; /* bit 31 is FMT Change, bit 30 is EOS */ + if (hw->PICWidth > 2048) { + dev_err(dev, "Invalid width [%d]\n", hw->PICWidth); + goto getpictureinfo_err; + } + + /* calc pic info line offset */ + if (dio->uinfo.b422mode) { + size = 2 * sizeof(BC_PIC_INFO_BLOCK); + offset = (PicInfoLineNum * hw->PICWidth * 2) + 4; + } else { + size = sizeof(BC_PIC_INFO_BLOCK); + offset = (PicInfoLineNum * hw->PICWidth) + 4; + } + + res = copy_from_user(tmpPicInfo, (void *)(dio->uinfo.xfr_buff+offset), size); + if (res != 0) + goto getpictureinfo_err; + + pPicInfoLine = (PBC_PIC_INFO_BLOCK)(tmpPicInfo); + + *PicMetaData = pPicInfoLine->timeStamp; + + if(widthField & PIB_EOS_DETECTED_BIT) + { + dev_dbg(dev, "Got EOS flag.\n"); + hw->DrvEosDetected = 1; + *(uint32_t *)(dio->pib_va) = 0xFFFFFFFF; + res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); + if (res != 0) + goto getpictureinfo_err; + } + else + { + if( hw->DrvEosDetected == 1 ) + hw->DrvCancelEosFlag = 1; + + hw->DrvEosDetected = 0; + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff), 4); + if (res != 0) + goto getpictureinfo_err; + + tmpYBuffData = *(uint32_t *)(dio->pib_va); + pPicInfoLine->ycom = tmpYBuffData; + res = copy_to_user((void *)(dio->uinfo.xfr_buff+offset), tmpPicInfo, size); + if (res != 0) + goto getpictureinfo_err; + + *(uint32_t *)(dio->pib_va) = PicInfoLineNum; + res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); + if (res != 0) + goto getpictureinfo_err; + } + + if(widthField & PIB_FORMAT_CHANGE_BIT) + { + rx_pkt->flags = 0; + rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; + + rx_pkt->pib.picture_number = pPicInfoLine->picture_number; + rx_pkt->pib.width = pPicInfoLine->width; + rx_pkt->pib.height = pPicInfoLine->height; + rx_pkt->pib.chroma_format = pPicInfoLine->chroma_format; + rx_pkt->pib.pulldown = pPicInfoLine->pulldown; + rx_pkt->pib.flags = pPicInfoLine->flags; + rx_pkt->pib.sess_num = pPicInfoLine->sess_num; + rx_pkt->pib.aspect_ratio = pPicInfoLine->aspect_ratio; + rx_pkt->pib.colour_primaries = pPicInfoLine->colour_primaries; + rx_pkt->pib.picture_meta_payload = pPicInfoLine->picture_meta_payload; + rx_pkt->pib.frame_rate = pPicInfoLine->frame_rate; + rx_pkt->pib.custom_aspect_ratio_width_height = pPicInfoLine->custom_aspect_ratio_width_height; + rx_pkt->pib.n_drop = pPicInfoLine->n_drop; + rx_pkt->pib.ycom = pPicInfoLine->ycom; + hw->PICHeight = rx_pkt->pib.height; + hw->PICWidth = rx_pkt->pib.width; + hw->LastPicNo=0; + hw->LastTwoPicNo=0; + hw->PDRatio = 0; /* NAREN - reset PD ratio to start measuring for new clip */ + hw->PauseThreshold = hw->DefaultPauseThreshold; + hw->TickSpentInPD = 0; + rdtscll(hw->TickCntDecodePU); + + dev_dbg(dev, "[FMT CH] DoneSz:0x%x, PIB:%x %x %x %x %x %x %x %x %x %x\n", + rx_pkt->dio_req->uinfo.y_done_sz * 4, + rx_pkt->pib.picture_number, + rx_pkt->pib.aspect_ratio, + rx_pkt->pib.chroma_format, + rx_pkt->pib.colour_primaries, + rx_pkt->pib.frame_rate, + rx_pkt->pib.height, + rx_pkt->pib.width, + rx_pkt->pib.n_drop, + rx_pkt->pib.pulldown, + rx_pkt->pib.ycom); + rtVal = false; + } + + if(pPicInfoLine->flags & FLEA_DECODE_ERROR_FLAG) + { + *PicNumber = 0; + } else { + /* get pic number and flags */ + if (dio->uinfo.b422mode) + offset = (PicInfoLineNum * hw->PICWidth * 2); + else + offset = (PicInfoLineNum * hw->PICWidth); + + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 4); + if (res != 0) + goto getpictureinfo_err; + + *PicNumber = *(uint32_t *)(dio->pib_va); + } + + if(dio->pib_va) + kfree(dio->pib_va); + if(tmpPicInfo) + kfree(tmpPicInfo); + +/* up(&hw->fetch_sem); */ + + return rtVal; + +getpictureinfo_err: +/* up(&hw->fetch_sem); */ + +getpictureinfo_err_nosem: + if(dio->pib_va) + kfree(dio->pib_va); + if(tmpPicInfo) + kfree(tmpPicInfo); + + *PicNumber = 0; + *PicMetaData = 0; + + return false; +} + +uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void* pRxDMAReq) +{ + uint32_t PicNumber = 0,result = 0; + uint64_t PicMetaData = 0; + + if(flea_GetPictureInfo(hw, (struct crystalhd_rx_dma_pkt *)pRxDMAReq, + &PicNumber, &PicMetaData)) + result = PicNumber; + + return result; +} + +bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode) +{ + switch(EventCode) + { + case BC_EVENT_START_CAPTURE: + { + crystalhd_flea_wake_up_hw(hw); + break; + } + default: + break; + } + + return true; +} --- crystalhd~/crystalhd_fleafuncs.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_fleafuncs.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,62 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_fleafuncs . h + * + * Description: + * BCM70015 Linux driver hardware layer. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_FLEAFUNCS_H_ +#define _CRYSTALHD_FLEAFUNCS_H_ + +#include "FleaDefs.h" + +#define FW_CMD_BUFF_SZ 64 + +bool crystalhd_flea_start_device(struct crystalhd_hw *hw); +bool crystalhd_flea_stop_device(struct crystalhd_hw *hw); +bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); +uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); /* Done */ +void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); /* Done */ +bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags); +BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); /* Done */ +BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); /* Done */ +BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); +BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); +void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); +BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state); +bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); +BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); +void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); +void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw); +BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw); +bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); +bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); +void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts); +bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw,union FLEA_INTR_BITS_COMMON int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); +bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw,union FLEA_INTR_BITS_COMMON int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); +void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON intr_sts); +void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); +bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode); + +bool flea_GetPictureInfo(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt * rx_pkt, + uint32_t *PicNumber, uint64_t *PicMetaData); +#endif --- crystalhd~/crystalhd_fw_if.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_fw_if.h 2011-03-14 23:02:54.000000000 +0300 @@ -27,37 +27,41 @@ #ifndef _CRYSTALHD_FW_IF_H_ #define _CRYSTALHD_FW_IF_H_ +#include + /* TBD: Pull in only required defs into this file.. */ /* User Data Header */ -struct user_data { - struct user_data *next; - uint32_t type; - uint32_t size; +struct UD_HDR { + struct UD_HDR *next; + uint32_t type; + uint32_t size; }; + + /*------------------------------------------------------* * MPEG Extension to the PPB * *------------------------------------------------------*/ -struct ppb_mpeg { - uint32_t to_be_defined; - uint32_t valid; - - /* Always valid, defaults to picture size if no - sequence display extension in the stream. */ - uint32_t display_horizontal_size; - uint32_t display_vertical_size; - - /* MPEG_VALID_PANSCAN - Offsets are a copy values from the MPEG stream. */ - uint32_t offset_count; - int32_t horizontal_offset[3]; - int32_t vertical_offset[3]; - - /* MPEG_VALID_USERDATA - User data is in the form of a linked list. */ - int32_t userDataSize; - struct user_data *userData; +struct PPB_MPEG { + uint32_t to_be_defined; + uint32_t valid; + + /* Always valid, defaults to picture size if no + sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* MPEG_VALID_PANSCAN + Offsets are a copy values from the MPEG stream. */ + uint32_t offset_count; + int32_t horizontal_offset[3]; + int32_t vertical_offset[3]; + + /* MPEG_VALID_USERDATA + User data is in the form of a linked list. */ + int32_t userDataSize; + struct UD_HDR *userData; }; @@ -65,26 +69,26 @@ struct ppb_mpeg { /*------------------------------------------------------* * VC1 Extension to the PPB * *------------------------------------------------------*/ -struct ppb_vc1 { - uint32_t to_be_defined; - uint32_t valid; - - /* Always valid, defaults to picture size if no - sequence display extension in the stream. */ - uint32_t display_horizontal_size; - uint32_t display_vertical_size; - - /* VC1 pan scan windows */ - uint32_t num_panscan_windows; - int32_t ps_horiz_offset[4]; - int32_t ps_vert_offset[4]; - int32_t ps_width[4]; - int32_t ps_height[4]; - - /* VC1_VALID_USERDATA - User data is in the form of a linked list. */ - int32_t userDataSize; - struct user_data *userData; +struct PPB_VC1 { + uint32_t to_be_defined; + uint32_t valid; + + /* Always valid, defaults to picture size if no + sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* VC1 pan scan windows */ + uint32_t num_panscan_windows; + int32_t ps_horiz_offset[4]; + int32_t ps_vert_offset[4]; + int32_t ps_width[4]; + int32_t ps_height[4]; + + /* VC1_VALID_USERDATA + User data is in the form of a linked list. */ + int32_t userDataSize; + struct UD_HDR *userData; }; @@ -104,266 +108,280 @@ struct ppb_vc1 { /* maximum number of intervals(as many as 256 intervals?) */ #define MAX_FGT_VALUE_INTERVAL (256) -struct fgt_sei { - struct fgt_sei *next; - unsigned char - model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; - unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; - unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; - - unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */ - unsigned char model_id; /* Model id. */ - - /* +unused SE based on Thomson spec */ - unsigned char color_desc_flag; /* Separate color description flag. */ - unsigned char bit_depth_luma; /* Bit depth luma minus 8. */ - unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */ - unsigned char full_range_flag; /* Full range flag. */ - unsigned char color_primaries; /* Color primaries. */ - unsigned char transfer_charact; /* Transfer characteristics. */ - unsigned char matrix_coeff; /*< Matrix coefficients. */ - /* -unused SE based on Thomson spec */ - - unsigned char blending_mode_id; /* Blending mode. */ - unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ - unsigned char comp_flag[3]; /* Components [0,2] - parameters present flag. */ - unsigned char num_intervals_minus1[3]; /* Number of - intensity level intervals. */ - unsigned char num_model_values[3]; /* Number of model values. */ - uint16_t repetition_period; /* Repetition period (0-16384) */ - -}; - -struct ppb_h264 { - /* 'valid' specifies which fields (or sets of - * fields) below are valid. If the corresponding - * bit in 'valid' is NOT set then that field(s) - * is (are) not initialized. */ - uint32_t valid; - - int32_t poc_top; /* POC for Top Field/Frame */ - int32_t poc_bottom; /* POC for Bottom Field */ - uint32_t idr_pic_id; - - /* H264_VALID_PANSCAN */ - uint32_t pan_scan_count; - int32_t pan_scan_left[3]; - int32_t pan_scan_right[3]; - int32_t pan_scan_top[3]; - int32_t pan_scan_bottom[3]; - - /* H264_VALID_CT_TYPE */ - uint32_t ct_type_count; - uint32_t ct_type[3]; - - /* H264_VALID_SPS_CROP */ - int32_t sps_crop_left; - int32_t sps_crop_right; - int32_t sps_crop_top; - int32_t sps_crop_bottom; - - /* H264_VALID_VUI */ - uint32_t chroma_top; - uint32_t chroma_bottom; - - /* H264_VALID_USER */ - uint32_t user_data_size; - struct user_data *user_data; - - /* H264 VALID FGT */ - struct fgt_sei *pfgt; - -}; - -struct ppb { - /* Common fields. */ - uint32_t picture_number; /* Ordinal display number */ - uint32_t video_buffer; /* Video (picbuf) number */ - uint32_t video_address; /* Address of picbuf Y */ - uint32_t video_address_uv; /* Address of picbuf UV */ - uint32_t video_stripe; /* Picbuf stripe */ - uint32_t video_width; /* Picbuf width */ - uint32_t video_height; /* Picbuf height */ - - uint32_t channel_id; /* Decoder channel ID */ - uint32_t status; /* reserved */ - uint32_t width; /* pixels */ - uint32_t height; /* pixels */ - uint32_t chroma_format; /* see above */ - uint32_t pulldown; /* see above */ - uint32_t flags; /* see above */ - uint32_t pts; /* 32 LSBs of PTS */ - uint32_t protocol; /* protocolXXX (above) */ - - uint32_t frame_rate; /* see above */ - uint32_t matrix_coeff; /* see above */ - uint32_t aspect_ratio; /* see above */ - uint32_t colour_primaries; /* see above */ - uint32_t transfer_char; /* see above */ - uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ - uint32_t n_drop; /* Number of pictures to be dropped */ - - uint32_t custom_aspect_ratio_width_height; - /* upper 16-bits is Y and lower 16-bits is X */ - - uint32_t picture_tag; /* Indexing tag from BUD packets */ - uint32_t picture_done_payload; - uint32_t picture_meta_payload; - uint32_t reserved[1]; - - /* Protocol-specific extensions. */ - union { - struct ppb_h264 h264; - struct ppb_mpeg mpeg; - struct ppb_vc1 vc1; - } other; - -}; - -struct c011_pib { - uint32_t bFormatChange; - uint32_t resolution; - uint32_t channelId; - uint32_t ppbPtr; - int32_t ptsStcOffset; - uint32_t zeroPanscanValid; - uint32_t dramOutBufAddr; - uint32_t yComponent; - struct ppb ppb; - -}; - -struct dec_rsp_channel_start_video { - uint32_t command; - uint32_t sequence; - uint32_t status; - uint32_t picBuf; - uint32_t picRelBuf; - uint32_t picInfoDeliveryQ; - uint32_t picInfoReleaseQ; - uint32_t channelStatus; - uint32_t userDataDeliveryQ; - uint32_t userDataReleaseQ; - uint32_t transportStreamCaptureAddr; - uint32_t asyncEventQ; +struct FGT_SEI { + struct FGT_SEI *next; + unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; + unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; + unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; + + unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */ + unsigned char model_id; /* Model id. */ + + /* +unused SE based on Thomson spec */ + unsigned char color_desc_flag; /* Separate color descrition flag. */ + unsigned char bit_depth_luma; /* Bit depth luma minus 8. */ + unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */ + unsigned char full_range_flag; /* Full range flag. */ + unsigned char color_primaries; /* Color primaries. */ + unsigned char transfer_charact; /* Transfer characteristics. */ + unsigned char matrix_coeff; /*< Matrix coefficients. */ + /* -unused SE based on Thomson spec */ + + unsigned char blending_mode_id; /* Blending mode. */ + unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ + unsigned char comp_flag[3]; /* Components [0,2] parameters present flag. */ + unsigned char num_intervals_minus1[3]; /* Number of intensity level intervals. */ + unsigned char num_model_values[3]; /* Number of model values. */ + uint16_t repetition_period; /* Repetition period (0-16384) */ + +}; + +struct PPB_H264 { + /* 'valid' specifies which fields (or sets of + * fields) below are valid. If the corresponding + * bit in 'valid' is NOT set then that field(s) + * is (are) not initialized. */ + uint32_t valid; + + int32_t poc_top; /* POC for Top Field/Frame */ + int32_t poc_bottom; /* POC for Bottom Field */ + uint32_t idr_pic_id; + + /* H264_VALID_PANSCAN */ + uint32_t pan_scan_count; + int32_t pan_scan_left[3]; + int32_t pan_scan_right[3]; + int32_t pan_scan_top[3]; + int32_t pan_scan_bottom[3]; + + /* H264_VALID_CT_TYPE */ + uint32_t ct_type_count; + uint32_t ct_type[3]; + + /* H264_VALID_SPS_CROP */ + int32_t sps_crop_left; + int32_t sps_crop_right; + int32_t sps_crop_top; + int32_t sps_crop_bottom; + + /* H264_VALID_VUI */ + uint32_t chroma_top; + uint32_t chroma_bottom; + + /* H264_VALID_USER */ + uint32_t user_data_size; + struct UD_HDR *user_data; + + /* H264 VALID FGT */ + struct FGT_SEI *pfgt; + +}; + +struct PPB { + /* Common fields. */ + uint32_t picture_number; /* Ordinal display number */ + uint32_t video_buffer; /* Video (picbuf) number */ + uint32_t video_address; /* Address of picbuf Y */ + uint32_t video_address_uv; /* Address of picbuf UV */ + uint32_t video_stripe; /* Picbuf stripe */ + uint32_t video_width; /* Picbuf width */ + uint32_t video_height; /* Picbuf height */ + + uint32_t channel_id; /* Decoder channel ID */ + uint32_t status; /* reserved */ + uint32_t width; /* pixels */ + uint32_t height; /* pixels */ + uint32_t chroma_format; /* see above */ + uint32_t pulldown; /* see above */ + uint32_t flags; /* see above */ + uint32_t pts; /* 32 LSBs of PTS */ + uint32_t protocol; /* protocolXXX (above) */ + + uint32_t frame_rate; /* see above */ + uint32_t matrix_coeff; /* see above */ + uint32_t aspect_ratio; /* see above */ + uint32_t colour_primaries; /* see above */ + uint32_t transfer_char; /* see above */ + uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ + uint32_t n_drop; /* Number of pictures to be dropped */ + + uint32_t custom_aspect_ratio_width_height; + /* upper 16-bits is Y and lower 16-bits is X */ + + uint32_t picture_tag; /* Indexing tag from BUD packets */ + uint32_t picture_done_payload; + uint32_t picture_meta_payload; + uint32_t reserved[1]; + + /* Protocol-specific extensions. */ + union { + struct PPB_H264 h264; + struct PPB_MPEG mpeg; + struct PPB_VC1 vc1; + } other; + +}; + +struct C011_PIB { + uint32_t bFormatChange; + uint32_t resolution; + uint32_t channelId; + uint32_t ppbPtr; + int32_t ptsStcOffset; + uint32_t zeroPanscanValid; + uint32_t dramOutBufAddr; + uint32_t yComponent; + struct PPB ppb; + +}; + +struct C011_TS_CMD { + uint32_t eCmd; /* eC011_TS_CMD */ + uint32_t ulParams[63]; +}; + +struct DecRspChannelStartVideo { + uint32_t command; + uint32_t sequence; + uint32_t status; + uint32_t picBuf; + uint32_t picRelBuf; + uint32_t picInfoDeliveryQ; + uint32_t picInfoReleaseQ; + uint32_t channelStatus; + uint32_t userDataDeliveryQ; + uint32_t userDataReleaseQ; + uint32_t transportStreamCaptureAddr; + uint32_t asyncEventQ; + +}; +struct DecRspChannelChannelOpen { + uint32_t command; + uint32_t sequence; + uint32_t status; + uint32_t ChannelID; + uint32_t picBuf; + uint32_t picRelBuf; + uint32_t picInfoDeliveryQ; + uint32_t picInfoReleaseQ; + uint32_t channelStatus; + uint32_t userDataDeliveryQ; + uint32_t userDataReleaseQ; + uint32_t transportStreamCaptureAddr; + uint32_t asyncEventQ; }; #define eCMD_C011_CMD_BASE (0x73763000) /* host commands */ -enum c011_ts_cmd { - eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */ - eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */ - eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */ - - /* New API commands */ - /* General commands */ - eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, - eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, - eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, - eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, - eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, - eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, - - /* Decoding commands */ - eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, - eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, - eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, - eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, - eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, - eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, - eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, - eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, - eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, - eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, - eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, - eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, - eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, - eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, - eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, - eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, - eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, - eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, - eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, - eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, - eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, - eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, - eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, - eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, - eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, - eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, - eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, - eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, - eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, - eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, - eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, - eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, - eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, - eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, - eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, - eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, - eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, - eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, - eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, - eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, - eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, - eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, - eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, - eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, - eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, - eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, - eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + - 0x132, - eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, - eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, - eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, - eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, - eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, - eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, - eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, - eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, - eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, - eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, - eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, - eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, - eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, - eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, - eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + - 0x147, - eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, - eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, - eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST - = eCMD_C011_CMD_BASE + 0x150, - - /* Decoder RevD commands */ - eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color - space conversion */ - eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, - eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, - /* Note: 0x183 not implemented yet in Rev D main */ - eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + - 0x183, - - /* Decoder 7412 commands (7412-only) */ - eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, - eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, - eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, - - eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, - - /* Encoding commands */ - eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, - eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, - eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, - eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, - eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, +enum eC011_TS_CMD { + eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */ + eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */ + eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */ + + /* New API commands */ + /* General commands */ + eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, + eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, + eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, + eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, + eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, + eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, + + /* Decoding commands */ + eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, + eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, + eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, + eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, + eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, + eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, + eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, + eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, + eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, + eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, + eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, + eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, + eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, + eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, + eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, + eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, + eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, + eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, + eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, + eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, + eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, + eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, + eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, + eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, + eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, + eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, + eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, + eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, + eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, + eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, + eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, + eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, + eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, + eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, + eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, + eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, + eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, + eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, + eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, + eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, + eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, + eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, + eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, + eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, + eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, + eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, + eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, + eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, + eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, + eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, + eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, + eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, + eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, + eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, + eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, + eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, + eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, + eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, + eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, + eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, + eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, + eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, + eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, + eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, + eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, + eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, + eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, + eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST + = eCMD_C011_CMD_BASE + 0x150, + + /* Decoder RevD commands */ + eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color space conversion */ + eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, + eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, + /* Note: 0x183 not implemented yet in Rev D main */ + eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, + + /* Decoder 7412 commands (7412-only) */ + eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, + eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, + eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, + + eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, + + /* Encoding commands */ + eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, + eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, + eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, + eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, + eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, - eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, + eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, }; --- crystalhd~/crystalhd_hw.c 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_hw.c 2011-03-14 23:02:54.000000000 +0300 @@ -4,7 +4,9 @@ * Name: crystalhd_hw . c * * Description: - * BCM70010 Linux driver HW layer. + * BCM70012/BCM70015 Linux driver hardware layer. + * + * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. @@ -22,344 +24,122 @@ * along with this driver. If not, see . **********************************************************************/ -#include "crystalhd.h" - #include -#include #include +#include +#include +#include +#include "crystalhd_lnx.h" +#include "crystalhd_linkfuncs.h" +#include "crystalhd_fleafuncs.h" -/* Functions internal to this file */ - -static void crystalhd_enable_uarts(struct crystalhd_adp *adp) -{ - bc_dec_reg_wr(adp, UartSelectA, BSVS_UART_STREAM); - bc_dec_reg_wr(adp, UartSelectB, BSVS_UART_DEC_OUTER); -} - - -static void crystalhd_start_dram(struct crystalhd_adp *adp) -{ - bc_dec_reg_wr(adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) | - /* tras (40ns tras)/(5ns period) -1 ((15/5 - 1) << 4) | // trcd */ - ((15 / 5 - 1) << 7) | /* trp */ - ((10 / 5 - 1) << 10) | /* trrd */ - ((15 / 5 + 1) << 12) | /* twr */ - ((2 + 1) << 16) | /* twtr */ - ((70 / 5 - 2) << 19) | /* trfc */ - (0 << 23)); - - bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0); - bc_dec_reg_wr(adp, SDRAM_EXT_MODE, 2); - bc_dec_reg_wr(adp, SDRAM_MODE, 0x132); - bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0); - bc_dec_reg_wr(adp, SDRAM_REFRESH, 0); - bc_dec_reg_wr(adp, SDRAM_REFRESH, 0); - bc_dec_reg_wr(adp, SDRAM_MODE, 0x32); - /* setting the refresh rate here */ - bc_dec_reg_wr(adp, SDRAM_REF_PARAM, ((1 << 12) | 96)); -} - - -static bool crystalhd_bring_out_of_rst(struct crystalhd_adp *adp) -{ - union link_misc_perst_deco_ctrl rst_deco_cntrl; - union link_misc_perst_clk_ctrl rst_clk_cntrl; - uint32_t temp; - - /* - * Link clocks: MISC_PERST_CLOCK_CTRL Clear PLL power down bit, - * delay to allow PLL to lock Clear alternate clock, stop clock bits - */ - rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.pll_pwr_dn = 0; - crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.stop_core_clk = 0; - rst_clk_cntrl.sel_alt_clk = 0; - - crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - /* - * Bus Arbiter Timeout: GISB_ARBITER_TIMER - * Set internal bus arbiter timeout to 40us based on core clock speed - * (63MHz * 40us = 0x9D8) - */ - crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x9D8); - - /* - * Decoder clocks: MISC_PERST_DECODER_CTRL - * Enable clocks while 7412 reset is asserted, delay - * De-assert 7412 reset - */ - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, - MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.stop_bcm_7412_clk = 0; - rst_deco_cntrl.bcm7412_rst = 1; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, - rst_deco_cntrl.whole_reg); - msleep_interruptible(10); - - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, - MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.bcm7412_rst = 0; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, - rst_deco_cntrl.whole_reg); - msleep_interruptible(50); - - /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ - crystalhd_reg_wr(adp, OTP_CONTENT_MISC, 0); - - /* Clear bit 29 of 0x404 */ - temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION); - temp &= ~BC_BIT(29); - crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); - - /* 2.5V regulator must be set to 2.6 volts (+6%) */ - /* FIXME: jarod: what's the point of this reg read? */ - temp = crystalhd_reg_rd(adp, MISC_PERST_VREG_CTRL); - crystalhd_reg_wr(adp, MISC_PERST_VREG_CTRL, 0xF3); - - return true; -} - -static bool crystalhd_put_in_reset(struct crystalhd_adp *adp) -{ - union link_misc_perst_deco_ctrl rst_deco_cntrl; - union link_misc_perst_clk_ctrl rst_clk_cntrl; - uint32_t temp; - - /* - * Decoder clocks: MISC_PERST_DECODER_CTRL - * Assert 7412 reset, delay - * Assert 7412 stop clock - */ - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, - MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.stop_bcm_7412_clk = 1; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, - rst_deco_cntrl.whole_reg); - msleep_interruptible(50); - - /* Bus Arbiter Timeout: GISB_ARBITER_TIMER - * Set internal bus arbiter timeout to 40us based on core clock speed - * (6.75MHZ * 40us = 0x10E) - */ - crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x10E); - - /* Link clocks: MISC_PERST_CLOCK_CTRL - * Stop core clk, delay - * Set alternate clk, delay, set PLL power down - */ - rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.stop_core_clk = 1; - rst_clk_cntrl.sel_alt_clk = 1; - crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.pll_pwr_dn = 1; - crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - - /* - * Read and restore the Transaction Configuration Register - * after core reset - */ - temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION); - - /* - * Link core soft reset: MISC3_RESET_CTRL - * - Write BIT[0]=1 and read it back for core reset to take place - */ - crystalhd_reg_wr(adp, MISC3_RESET_CTRL, 1); - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC3_RESET_CTRL); - msleep_interruptible(50); - - /* restore the transaction configuration register */ - crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); - - return true; -} - -static void crystalhd_disable_interrupts(struct crystalhd_adp *adp) -{ - union intr_mask_reg intr_mask; - intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG); - intr_mask.mask_pcie_err = 1; - intr_mask.mask_pcie_rbusmast_err = 1; - intr_mask.mask_pcie_rgr_bridge = 1; - intr_mask.mask_rx_done = 1; - intr_mask.mask_rx_err = 1; - intr_mask.mask_tx_done = 1; - intr_mask.mask_tx_err = 1; - crystalhd_reg_wr(adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg); - - return; -} - -static void crystalhd_enable_interrupts(struct crystalhd_adp *adp) -{ - union intr_mask_reg intr_mask; - intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG); - intr_mask.mask_pcie_err = 1; - intr_mask.mask_pcie_rbusmast_err = 1; - intr_mask.mask_pcie_rgr_bridge = 1; - intr_mask.mask_rx_done = 1; - intr_mask.mask_rx_err = 1; - intr_mask.mask_tx_done = 1; - intr_mask.mask_tx_err = 1; - crystalhd_reg_wr(adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg); - - return; -} - -static void crystalhd_clear_errors(struct crystalhd_adp *adp) -{ - uint32_t reg; - - /* FIXME: jarod: wouldn't we want to write a 0 to the reg? - Or does the write clear the bits specified? */ - reg = crystalhd_reg_rd(adp, MISC1_Y_RX_ERROR_STATUS); - if (reg) - crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg); - - reg = crystalhd_reg_rd(adp, MISC1_UV_RX_ERROR_STATUS); - if (reg) - crystalhd_reg_wr(adp, MISC1_UV_RX_ERROR_STATUS, reg); - - reg = crystalhd_reg_rd(adp, MISC1_TX_DMA_ERROR_STATUS); - if (reg) - crystalhd_reg_wr(adp, MISC1_TX_DMA_ERROR_STATUS, reg); -} - -static void crystalhd_clear_interrupts(struct crystalhd_adp *adp) -{ - uint32_t intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS); - - if (intr_sts) { - crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts); - - /* Write End Of Interrupt for PCIE */ - crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1); - } -} - -static void crystalhd_soft_rst(struct crystalhd_adp *adp) -{ - uint32_t val; - - /* Assert c011 soft reset*/ - bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000001); - msleep_interruptible(50); - - /* Release c011 soft reset*/ - bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000000); - - /* Disable Stuffing..*/ - val = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL); - val |= BC_BIT(8); - crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, val); -} +#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) -static bool crystalhd_load_firmware_config(struct crystalhd_adp *adp) +BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp) { - uint32_t i = 0, reg; - - crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); - - crystalhd_reg_wr(adp, AES_CMD, 0); - crystalhd_reg_wr(adp, AES_CONFIG_INFO, - (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); - crystalhd_reg_wr(adp, AES_CMD, 0x1); - - /* FIXME: jarod: I've seen this fail, - and introducing extra delays helps... */ - for (i = 0; i < 100; ++i) { - reg = crystalhd_reg_rd(adp, AES_STATUS); - if (reg & 0x1) - return true; - msleep_interruptible(10); + struct device *dev; + if (!hw || !adp) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; } - return false; -} - - -static bool crystalhd_start_device(struct crystalhd_adp *adp) -{ - uint32_t dbg_options, glb_cntrl = 0, reg_pwrmgmt = 0; - - BCMLOG(BCMLOG_INFO, "Starting BCM70012 Device\n"); - - reg_pwrmgmt = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL); - reg_pwrmgmt &= ~ASPM_L1_ENABLE; - - crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt); + if (hw->dev_started) + return BC_STS_SUCCESS; - if (!crystalhd_bring_out_of_rst(adp)) { - BCMLOG_ERR("Failed To Bring Link Out Of Reset\n"); - return false; + dev = &adp->pdev->dev; + hw->PauseThreshold = BC_RX_LIST_CNT - 2; + hw->DefaultPauseThreshold = BC_RX_LIST_CNT - 2; + hw->ResumeThreshold = 3; + + /* Setup HW specific functions appropriately */ + if (adp->pdev->device == BC_PCI_DEVID_FLEA) { + dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Flea\n"); + hw->pfnStartDevice = crystalhd_flea_start_device; + hw->pfnStopDevice = crystalhd_flea_stop_device; + hw->pfnFindAndClearIntr = crystalhd_flea_hw_interrupt_handle; + hw->pfnReadDevRegister = crystalhd_flea_reg_rd; /* Done */ + hw->pfnWriteDevRegister = crystalhd_flea_reg_wr; /* Done */ + hw->pfnReadFPGARegister = crystalhd_flea_reg_rd; /* Done */ + hw->pfnWriteFPGARegister = crystalhd_flea_reg_wr; /* Done */ + hw->pfnCheckInputFIFO = crystalhd_flea_check_input_full; + hw->pfnDevDRAMRead = crystalhd_flea_mem_rd; /* Done */ + hw->pfnDevDRAMWrite = crystalhd_flea_mem_wr; /* Done */ + hw->pfnDoFirmwareCmd = crystalhd_flea_do_fw_cmd; + hw->pfnFWDwnld = crystalhd_flea_download_fw; + hw->pfnHWGetDoneSize = crystalhd_flea_get_dnsz; + hw->pfnIssuePause = crystalhd_flea_hw_pause; + hw->pfnPeekNextDeodedFr = crystalhd_flea_peek_next_decoded_frame; + hw->pfnPostRxSideBuff = crystalhd_flea_hw_post_cap_buff; + hw->pfnStartTxDMA = crystalhd_flea_start_tx_dma_engine; + hw->pfnStopTxDMA = crystalhd_flea_stop_tx_dma_engine; + hw->pfnStopRXDMAEngines = crystalhd_flea_stop_rx_dma_engine; + hw->pfnNotifyFLLChange = crystalhd_flea_notify_fll_change; + hw->pfnNotifyHardware = crystalhd_flea_notify_event; + } else { + dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Link\n"); + hw->pfnStartDevice = crystalhd_link_start_device; + hw->pfnStopDevice = crystalhd_link_stop_device; + hw->pfnFindAndClearIntr = crystalhd_link_hw_interrupt_handle; + hw->pfnReadDevRegister = link_dec_reg_rd; + hw->pfnWriteDevRegister = link_dec_reg_wr; + hw->pfnReadFPGARegister = crystalhd_link_reg_rd; + hw->pfnWriteFPGARegister = crystalhd_link_reg_wr; + hw->pfnCheckInputFIFO = crystalhd_link_check_input_full; + hw->pfnDevDRAMRead = crystalhd_link_mem_rd; + hw->pfnDevDRAMWrite = crystalhd_link_mem_wr; + hw->pfnDoFirmwareCmd = crystalhd_link_do_fw_cmd; + hw->pfnFWDwnld = crystalhd_link_download_fw; + hw->pfnHWGetDoneSize = crystalhd_link_get_dnsz; + hw->pfnIssuePause = crystalhd_link_hw_pause; + hw->pfnPeekNextDeodedFr = crystalhd_link_peek_next_decoded_frame; + hw->pfnPostRxSideBuff = crystalhd_link_hw_post_cap_buff; + hw->pfnStartTxDMA = crystalhd_link_start_tx_dma_engine; + hw->pfnStopTxDMA = crystalhd_link_stop_tx_dma_engine; + hw->pfnStopRXDMAEngines = crystalhd_link_stop_rx_dma_engine; + hw->pfnNotifyFLLChange = crystalhd_link_notify_fll_change; + hw->pfnNotifyHardware = crystalhd_link_notify_event; } - crystalhd_disable_interrupts(adp); - - crystalhd_clear_errors(adp); - - crystalhd_clear_interrupts(adp); - - crystalhd_enable_interrupts(adp); - - /* Enable the option for getting the total no. of DWORDS - * that have been transferred by the RXDMA engine - */ - dbg_options = crystalhd_reg_rd(adp, MISC1_DMA_DEBUG_OPTIONS_REG); - dbg_options |= 0x10; - crystalhd_reg_wr(adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options); + hw->adp = adp; + spin_lock_init(&hw->lock); + spin_lock_init(&hw->rx_lock); + sema_init(&hw->fetch_sem, 1); - /* Enable PCI Global Control options */ - glb_cntrl = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL); - glb_cntrl |= 0x100; - glb_cntrl |= 0x8000; - crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, glb_cntrl); + /* Seed for error checking and debugging. Random numbers */ + hw->tx_ioq_tag_seed = 0x70023070; + hw->rx_pkt_tag_seed = 0x70029070; - crystalhd_enable_interrupts(adp); + hw->stop_pending = 0; + hw->pfnStartDevice(hw); + hw->dev_started = true; - crystalhd_soft_rst(adp); - crystalhd_start_dram(adp); - crystalhd_enable_uarts(adp); + dev_dbg(dev, "Opening HW. hw:0x%lx, hw->adp:0x%lx\n", + (uintptr_t)hw, (uintptr_t)(hw->adp)); - return true; + return BC_STS_SUCCESS; } -static bool crystalhd_stop_device(struct crystalhd_adp *adp) +BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp) { - uint32_t reg; - - BCMLOG(BCMLOG_INFO, "Stopping BCM70012 Device\n"); - /* Clear and disable interrupts */ - crystalhd_disable_interrupts(adp); - crystalhd_clear_errors(adp); - crystalhd_clear_interrupts(adp); + if (!hw) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_SUCCESS; + } - if (!crystalhd_put_in_reset(adp)) - BCMLOG_ERR("Failed to Put Link To Reset State\n"); + if (!hw->dev_started) + return BC_STS_SUCCESS; - reg = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL); - reg |= ASPM_L1_ENABLE; - crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg); + /* Stop and DDR sleep will happen in here */ + /* Only stop the HW if we are the last user */ + if(adp->cfg_users == 1) + crystalhd_hw_suspend(hw); - /* Set PCI Clk Req */ - reg = crystalhd_reg_rd(adp, PCIE_CLK_REQ_REG); - reg |= PCI_CLK_REQ_ENABLE; - crystalhd_reg_wr(adp, PCIE_CLK_REQ_REG, reg); + hw->dev_started = false; - return true; + return BC_STS_SUCCESS; } -static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt( - struct crystalhd_hw *hw) +struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw) { unsigned long flags = 0; struct crystalhd_rx_dma_pkt *temp = NULL; @@ -380,7 +160,7 @@ static struct crystalhd_rx_dma_pkt *crys return temp; } -static void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, +void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *pkt) { unsigned long flags = 0; @@ -398,12 +178,12 @@ static void crystalhd_hw_free_rx_pkt(str * Call back from TX - IOQ deletion. * * This routine will release the TX DMA rings allocated - * during setup_dma rings interface. + * druing setup_dma rings interface. * * Memory is allocated per DMA ring basis. This is just * a place holder to be able to create the dio queues. */ -static void crystalhd_tx_desc_rel_call_back(void *context, void *data) +void crystalhd_tx_desc_rel_call_back(void *context, void *data) { } @@ -414,20 +194,18 @@ static void crystalhd_tx_desc_rel_call_b * back to our free pool. The actual cleanup of the DMA * ring descriptors happen during dma ring release. */ -static void crystalhd_rx_pkt_rel_call_back(void *context, void *data) +void crystalhd_rx_pkt_rel_call_back(void *context, void *data) { struct crystalhd_hw *hw = (struct crystalhd_hw *)context; struct crystalhd_rx_dma_pkt *pkt = (struct crystalhd_rx_dma_pkt *)data; if (!pkt || !hw) { - BCMLOG_ERR("Invalid arg - %p %p\n", hw, pkt); + printk(KERN_ERR "%s: Invalid arg - %p %p\n", __func__, hw, pkt); return; } if (pkt->dio_req) crystalhd_unmap_dio(hw->adp, pkt->dio_req); - else - BCMLOG_ERR("Missing dio_req: 0x%x\n", pkt->pkt_tag); crystalhd_hw_free_rx_pkt(hw, pkt); } @@ -438,12 +216,11 @@ static void crystalhd_rx_pkt_rel_call_ba q = NULL; \ } -static void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw) +void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw) { if (!hw) return; - BCMLOG(BCMLOG_DBG, "Deleting IOQs\n"); crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq); crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq); crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq); @@ -464,12 +241,12 @@ do { \ * TX - Active & Free * RX - Active, Ready and Free. */ -static enum BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw) +BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; if (!hw) { - BCMLOG_ERR("Invalid Arg!!\n"); + printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); return BC_STS_INV_ARG; } @@ -493,64 +270,134 @@ hw_create_ioq_err: return sts; } +BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) +{ + struct device *dev; + unsigned int i; + void *mem; + size_t mem_len; + dma_addr_t phy_addr; + BC_STATUS sts = BC_STS_SUCCESS; + struct crystalhd_rx_dma_pkt *rpkt; + + if (!hw || !hw->adp) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + sts = crystalhd_hw_create_ioqs(hw); + if (sts != BC_STS_SUCCESS) { + dev_err(dev, "Failed to create IOQs..\n"); + return sts; + } + + mem_len = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); + + for (i = 0; i < BC_TX_LIST_CNT; i++) { + mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); + if (mem) { + memset(mem, 0, mem_len); + } else { + dev_err(dev, "Insufficient Memory For TX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + /* rx_pkt_pool -- static memory allocation */ + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem; + hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr; + hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS * + sizeof(struct dma_descriptor); + hw->tx_pkt_pool[i].list_tag = 0; + + /* Add TX dma requests to Free Queue..*/ + sts = crystalhd_dioq_add(hw->tx_freeq, + &hw->tx_pkt_pool[i], false, 0); + if (sts != BC_STS_SUCCESS) { + crystalhd_hw_free_dma_rings(hw); + return sts; + } + } + + for (i = 0; i < BC_RX_LIST_CNT; i++) { + rpkt = kzalloc(sizeof(*rpkt), GFP_KERNEL); + if (!rpkt) { + dev_err(dev, "Insufficient Memory For RX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + + mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); + if (mem) { + memset(mem, 0, mem_len); + } else { + dev_err(dev, "Insufficient Memory For RX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + rpkt->desc_mem.pdma_desc_start = mem; + rpkt->desc_mem.phy_addr = phy_addr; + rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); + rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; + crystalhd_hw_free_rx_pkt(hw, rpkt); + } + + return BC_STS_SUCCESS; +} -static bool crystalhd_code_in_full(struct crystalhd_adp *adp, - uint32_t needed_sz, bool b_188_byte_pkts, uint8_t flags) +BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) { - uint32_t base, end, writep, readp; - uint32_t cpbSize, cpbFullness, fifoSize; + unsigned int i; + struct crystalhd_rx_dma_pkt *rpkt = NULL; - if (flags & 0x02) { /* ASF Bit is set */ - base = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Base); - end = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2End); - writep = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Wrptr); - readp = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Rdptr); - } else if (b_188_byte_pkts) { /*Encrypted 188 byte packets*/ - base = bc_dec_reg_rd(adp, REG_Dec_TsUser0Base); - end = bc_dec_reg_rd(adp, REG_Dec_TsUser0End); - writep = bc_dec_reg_rd(adp, REG_Dec_TsUser0Wrptr); - readp = bc_dec_reg_rd(adp, REG_Dec_TsUser0Rdptr); - } else { - base = bc_dec_reg_rd(adp, REG_DecCA_RegCinBase); - end = bc_dec_reg_rd(adp, REG_DecCA_RegCinEnd); - writep = bc_dec_reg_rd(adp, REG_DecCA_RegCinWrPtr); - readp = bc_dec_reg_rd(adp, REG_DecCA_RegCinRdPtr); + if (!hw || !hw->adp) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; } - cpbSize = end - base; - if (writep >= readp) - cpbFullness = writep - readp; - else - cpbFullness = (end - base) - (readp - writep); + /* Delete all IOQs.. */ + crystalhd_hw_delete_ioqs(hw); - fifoSize = cpbSize - cpbFullness; + for (i = 0; i < BC_TX_LIST_CNT; i++) { + if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) { + bc_kern_dma_free(hw->adp, + hw->tx_pkt_pool[i].desc_mem.sz, + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start, + hw->tx_pkt_pool[i].desc_mem.phy_addr); - if (fifoSize < BC_INFIFO_THRESHOLD) - return true; + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL; + } + } - if (needed_sz > (fifoSize - BC_INFIFO_THRESHOLD)) - return true; + dev_dbg(&hw->adp->pdev->dev, "Releasing RX Pkt pool\n"); + for (i = 0; i < BC_RX_LIST_CNT; i++) { + rpkt = crystalhd_hw_alloc_rx_pkt(hw); + if (!rpkt) + break; + bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz, + rpkt->desc_mem.pdma_desc_start, + rpkt->desc_mem.phy_addr); + kfree(rpkt); + } - return false; + return BC_STS_SUCCESS; } -static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, - uint32_t list_id, enum BC_STATUS cs) +BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, + uint32_t list_id, BC_STATUS cs) { struct tx_dma_pkt *tx_req; if (!hw || !list_id) { - BCMLOG_ERR("Invalid Arg..\n"); + printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); return BC_STS_INV_ARG; } - hw->pwr_lock--; - - tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch( - hw->tx_actq, list_id); + tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id); if (!tx_req) { if (cs != BC_STS_IO_USER_ABORT) - BCMLOG_ERR("Find and Fetch Did not find req\n"); + dev_err(&hw->adp->pdev->dev, "Find/Fetch: no req!\n"); return BC_STS_NO_DATA; } @@ -560,8 +407,8 @@ static enum BC_STATUS crystalhd_hw_tx_re tx_req->cb_event = NULL; tx_req->call_back = NULL; } else { - BCMLOG(BCMLOG_DBG, "Missing Tx Callback - %X\n", - tx_req->list_tag); + dev_dbg(&hw->adp->pdev->dev, "Missing Tx Callback - %X\n", + tx_req->list_tag); } /* Now put back the tx_list back in FreeQ */ @@ -570,146 +417,21 @@ static enum BC_STATUS crystalhd_hw_tx_re return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0); } -static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, - uint32_t err_sts) -{ - uint32_t err_mask, tmp; - unsigned long flags = 0; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - BCMLOG_ERR("Error on Tx-L0 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - spin_lock_irqsave(&hw->lock, flags); - /* reset list index.*/ - hw->tx_list_post_index = 0; - spin_unlock_irqrestore(&hw->lock, flags); - } - - tmp = err_sts & err_mask; - crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, - uint32_t err_sts) -{ - uint32_t err_mask, tmp; - unsigned long flags = 0; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - BCMLOG_ERR("Error on Tx-L1 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - spin_lock_irqsave(&hw->lock, flags); - /* reset list index.*/ - hw->tx_list_post_index = 0; - spin_unlock_irqrestore(&hw->lock, flags); - } - - tmp = err_sts & err_mask; - crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -static void crystalhd_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts) -{ - uint32_t err_sts; - - if (int_sts & INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, - BC_STS_SUCCESS); - - if (int_sts & INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, - BC_STS_SUCCESS); - - if (!(int_sts & (INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK | - INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK))) { - /* No error mask set.. */ - return; - } - - /* Handle Tx errors. */ - err_sts = crystalhd_reg_rd(hw->adp, MISC1_TX_DMA_ERROR_STATUS); - - if (crystalhd_tx_list0_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, - BC_STS_ERROR); - - if (crystalhd_tx_list1_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, - BC_STS_ERROR); - - hw->stats.tx_errors++; -} - -static void crystalhd_hw_dump_desc(struct dma_descriptor *p_dma_desc, - uint32_t ul_desc_index, uint32_t cnt) -{ - uint32_t ix, ll = 0; - - if (!p_dma_desc || !cnt) - return; - - /* FIXME: jarod: perhaps a modparam desc_debug to enable this, - rather than setting ll (log level, I presume) to non-zero? */ - if (!ll) - return; - - for (ix = ul_desc_index; ix < (ul_desc_index + cnt); ix++) { - BCMLOG(ll, - "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n", - ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"), - ul_desc_index, - p_dma_desc[ul_desc_index].buff_addr_high, - p_dma_desc[ul_desc_index].buff_addr_low, - p_dma_desc[ul_desc_index].next_desc_addr_high, - p_dma_desc[ul_desc_index].next_desc_addr_low, - p_dma_desc[ul_desc_index].xfer_size, - p_dma_desc[ul_desc_index].intr_enable, - p_dma_desc[ul_desc_index].last_rec_indicator); - } - -} - -static enum BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, - struct dma_descriptor *desc, - dma_addr_t desc_paddr_base, - uint32_t sg_cnt, uint32_t sg_st_ix, - uint32_t sg_st_off, uint32_t xfr_sz) +BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, + struct dma_descriptor *desc, + dma_addr_t desc_paddr_base, + uint32_t sg_cnt, uint32_t sg_st_ix, + uint32_t sg_st_off, uint32_t xfr_sz, + struct device *dev, uint32_t destDRAMaddr) { uint32_t count = 0, ix = 0, sg_ix = 0, len = 0, last_desc_ix = 0; dma_addr_t desc_phy_addr = desc_paddr_base; - union addr_64 addr_temp; + addr_64 addr_temp; + uint32_t curDRAMaddr = destDRAMaddr; if (!ioreq || !desc || !desc_paddr_base || !xfr_sz || - (!sg_cnt && !ioreq->uinfo.dir_tx)) { - BCMLOG_ERR("Invalid Args\n"); + (!sg_cnt && !ioreq->uinfo.dir_tx)) { + dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } @@ -721,8 +443,8 @@ static enum BC_STATUS crystalhd_hw_fill_ /* Get SGLE length */ len = crystalhd_get_sgle_len(ioreq, sg_ix); if (len % 4) { - BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix, - sg_cnt); + dev_err(dev, "unsupported len in sg %d %d %d\n", + len, sg_ix, sg_cnt); return BC_STS_NOT_IMPL; } /* Setup DMA desc with Phy addr & Length at current index. */ @@ -734,11 +456,10 @@ static enum BC_STATUS crystalhd_hw_fill_ memset(&desc[ix], 0, sizeof(desc[ix])); desc[ix].buff_addr_low = addr_temp.low_part; desc[ix].buff_addr_high = addr_temp.high_part; - desc[ix].dma_dir = ioreq->uinfo.dir_tx; + desc[ix].dma_dir = ioreq->uinfo.dir_tx; /* RX dma_dir = 0, TX dma_dir = 1 */ /* Chain DMA descriptor. */ - addr_temp.full_addr = desc_phy_addr + - sizeof(struct dma_descriptor); + addr_temp.full_addr = desc_phy_addr + sizeof(struct dma_descriptor); desc[ix].next_desc_addr_low = addr_temp.low_part; desc[ix].next_desc_addr_high = addr_temp.high_part; @@ -747,17 +468,22 @@ static enum BC_STATUS crystalhd_hw_fill_ /* Debug.. */ if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) { - BCMLOG_ERR( - "inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n", - len, ix, count, xfr_sz, sg_cnt); + dev_err(dev, "inv-len(%x) Ix(%d) count:%x xfr_sz:%x " + "sg_cnt:%d\n", len, ix, count, xfr_sz, sg_cnt); return BC_STS_ERROR; } /* Length expects Multiple of 4 */ desc[ix].xfer_size = (len / 4); - crystalhd_hw_dump_desc(desc, ix, 1); - count += len; + /* If TX fill in the destination DRAM address if needed */ + if(ioreq->uinfo.dir_tx) { + desc[ix].sdram_buff_addr = curDRAMaddr; + curDRAMaddr = destDRAMaddr + count; + } + else + desc[ix].sdram_buff_addr = 0; + desc_phy_addr += sizeof(struct dma_descriptor); } @@ -772,6 +498,13 @@ static enum BC_STATUS crystalhd_hw_fill_ desc[ix].xfer_size = 1; desc[ix].fill_bytes = 4 - ioreq->fb_size; count += ioreq->fb_size; + /* If TX fill in the destination DRAM address if needed */ + if(ioreq->uinfo.dir_tx) { + desc[ix].sdram_buff_addr = curDRAMaddr; + curDRAMaddr = destDRAMaddr + count; + } + else + desc[ix].sdram_buff_addr = 0; last_desc_ix++; } @@ -781,41 +514,40 @@ static enum BC_STATUS crystalhd_hw_fill_ desc[last_desc_ix].next_desc_addr_high = 0; desc[last_desc_ix].intr_enable = 1; - crystalhd_hw_dump_desc(desc, last_desc_ix, 1); - if (count != xfr_sz) { - BCMLOG_ERR("internal error sz curr:%x exp:%x\n", count, xfr_sz); + dev_err(dev, "interal error sz curr:%x exp:%x\n", + count, xfr_sz); return BC_STS_ERROR; } return BC_STS_SUCCESS; } -static enum BC_STATUS crystalhd_xlat_sgl_to_dma_desc( - struct crystalhd_dio_req *ioreq, - struct dma_desc_mem *pdesc_mem, - uint32_t *uv_desc_index) +BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq, + struct dma_desc_mem * pdesc_mem, + uint32_t *uv_desc_index, + struct device *dev, uint32_t destDRAMaddr) { struct dma_descriptor *desc = NULL; dma_addr_t desc_paddr_base = 0; uint32_t sg_cnt = 0, sg_st_ix = 0, sg_st_off = 0; uint32_t xfr_sz = 0; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; /* Check params.. */ if (!ioreq || !pdesc_mem || !uv_desc_index) { - BCMLOG_ERR("Invalid Args\n"); + dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } if (!pdesc_mem->sz || !pdesc_mem->pdma_desc_start || - !ioreq->sg || (!ioreq->sg_cnt && !ioreq->uinfo.dir_tx)) { - BCMLOG_ERR("Invalid Args\n"); + !ioreq->sg || (!ioreq->sg_cnt && !ioreq->uinfo.dir_tx)) { + dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } if ((ioreq->uinfo.dir_tx) && (ioreq->uinfo.uv_offset)) { - BCMLOG_ERR("UV offset for TX??\n"); + dev_err(dev, "%s: UV offset for TX??\n", __func__); return BC_STS_INV_ARG; } @@ -832,7 +564,7 @@ static enum BC_STATUS crystalhd_xlat_sgl } sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, - sg_st_ix, sg_st_off, xfr_sz); + sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); if ((sts != BC_STS_SUCCESS) || !ioreq->uinfo.uv_offset) return sts; @@ -840,7 +572,7 @@ static enum BC_STATUS crystalhd_xlat_sgl /* Prepare for UV mapping.. */ desc = &pdesc_mem->pdma_desc_start[sg_cnt]; desc_paddr_base = pdesc_mem->phy_addr + - (sg_cnt * sizeof(struct dma_descriptor)); + (sg_cnt * sizeof(struct dma_descriptor)); /* Done with desc addr.. now update sg stuff.*/ sg_cnt = ioreq->sg_cnt - ioreq->uinfo.uv_sg_ix; @@ -849,7 +581,7 @@ static enum BC_STATUS crystalhd_xlat_sgl sg_st_off = ioreq->uinfo.uv_sg_off; sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, - sg_st_ix, sg_st_off, xfr_sz); + sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); if (sts != BC_STS_SUCCESS) return sts; @@ -858,1239 +590,149 @@ static enum BC_STATUS crystalhd_xlat_sgl return sts; } -static void crystalhd_start_tx_dma_engine(struct crystalhd_hw *hw) +BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, + uint32_t list_index, + BC_STATUS comp_sts) { - uint32_t dma_cntrl; + struct crystalhd_rx_dma_pkt *rx_pkt = NULL; + uint32_t y_dw_dnsz, uv_dw_dnsz; + BC_STATUS sts = BC_STS_SUCCESS; + uint64_t currTick; - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } + uint32_t totalTick_Hi; + uint32_t TickSpentInPD_Hi; + uint64_t temp_64; + int32_t totalTick_Hi_f; + int32_t TickSpentInPD_Hi_f; - return; -} + if (!hw || list_index >= DMA_ENGINE_CNT) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } -/* _CHECK_THIS_ - * - * Verify if the Stop generates a completion interrupt or not. - * if it does not generate an interrupt, then add polling here. - */ -static enum BC_STATUS crystalhd_stop_tx_dma_engine(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl, cnt = 30; - uint32_t l1 = 1, l2 = 1; - unsigned long flags = 0; - - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); - - BCMLOG(BCMLOG_DBG, "Stopping TX DMA Engine..\n"); - - if (!(dma_cntrl & DMA_START_BIT)) { - BCMLOG(BCMLOG_DBG, "Already Stopped\n"); - return BC_STS_SUCCESS; - } - - crystalhd_disable_interrupts(hw->adp); - - /* Issue stop to HW */ - /* This bit when set gave problems. Please check*/ - dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - - BCMLOG(BCMLOG_DBG, "Cleared the DMA Start bit\n"); - - /* Poll for 3seconds (30 * 100ms) on both the lists..*/ - while ((l1 || l2) && cnt) { - - if (l1) { - l1 = crystalhd_reg_rd(hw->adp, - MISC1_TX_FIRST_DESC_L_ADDR_LIST0); - l1 &= DMA_START_BIT; - } - - if (l2) { - l2 = crystalhd_reg_rd(hw->adp, - MISC1_TX_FIRST_DESC_L_ADDR_LIST1); - l2 &= DMA_START_BIT; - } - - msleep_interruptible(100); - - cnt--; - } - - if (!cnt) { - BCMLOG_ERR("Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); - crystalhd_enable_interrupts(hw->adp); - return BC_STS_ERROR; - } - - spin_lock_irqsave(&hw->lock, flags); - hw->tx_list_post_index = 0; - spin_unlock_irqrestore(&hw->lock, flags); - BCMLOG(BCMLOG_DBG, "stopped TX DMA..\n"); - crystalhd_enable_interrupts(hw->adp); - - return BC_STS_SUCCESS; -} - -static uint32_t crystalhd_get_pib_avail_cnt(struct crystalhd_hw *hw) -{ - /* - * Position of the PIB Entries can be found at - * 0th and the 1st location of the Circular list. - */ - uint32_t Q_addr; - uint32_t pib_cnt, r_offset, w_offset; - - Q_addr = hw->pib_del_Q_addr; - - /* Get the Read Pointer */ - crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); - - /* Get the Write Pointer */ - crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); - - if (r_offset == w_offset) - return 0; /* Queue is empty */ - - if (w_offset > r_offset) - pib_cnt = w_offset - r_offset; - else - pib_cnt = (w_offset + MAX_PIB_Q_DEPTH) - - (r_offset + MIN_PIB_Q_DEPTH); - - if (pib_cnt > MAX_PIB_Q_DEPTH) { - BCMLOG_ERR("Invalid PIB Count (%u)\n", pib_cnt); - return 0; - } - - return pib_cnt; -} - -static uint32_t crystalhd_get_addr_from_pib_Q(struct crystalhd_hw *hw) -{ - uint32_t Q_addr; - uint32_t addr_entry, r_offset, w_offset; - - Q_addr = hw->pib_del_Q_addr; - - /* Get the Read Pointer 0Th Location is Read Pointer */ - crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); - - /* Get the Write Pointer 1st Location is Write pointer */ - crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); - - /* Queue is empty */ - if (r_offset == w_offset) - return 0; - - if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) - return 0; - - /* Get the Actual Address of the PIB */ - crystalhd_mem_rd(hw->adp, Q_addr + (r_offset * sizeof(uint32_t)), - 1, &addr_entry); - - /* Increment the Read Pointer */ - r_offset++; - - if (MAX_PIB_Q_DEPTH == r_offset) - r_offset = MIN_PIB_Q_DEPTH; - - /* Write back the read pointer to It's Location */ - crystalhd_mem_wr(hw->adp, Q_addr, 1, &r_offset); - - return addr_entry; -} - -static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, - uint32_t addr_to_rel) -{ - uint32_t Q_addr; - uint32_t r_offset, w_offset, n_offset; - - Q_addr = hw->pib_rel_Q_addr; - - /* Get the Read Pointer */ - crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); - - /* Get the Write Pointer */ - crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); - - if ((r_offset < MIN_PIB_Q_DEPTH) || - (r_offset >= MAX_PIB_Q_DEPTH)) - return false; - - n_offset = w_offset + 1; - - if (MAX_PIB_Q_DEPTH == n_offset) - n_offset = MIN_PIB_Q_DEPTH; - - if (r_offset == n_offset) - return false; /* should never happen */ - - /* Write the DRAM ADDR to the Queue at Next Offset */ - crystalhd_mem_wr(hw->adp, Q_addr + (w_offset * sizeof(uint32_t)), - 1, &addr_to_rel); - - /* Put the New value of the write pointer in Queue */ - crystalhd_mem_wr(hw->adp, Q_addr + sizeof(uint32_t), 1, &n_offset); - - return true; -} - -static void cpy_pib_to_app(struct c011_pib *src_pib, - struct BC_PIC_INFO_BLOCK *dst_pib) -{ - if (!src_pib || !dst_pib) { - BCMLOG_ERR("Invalid Arguments\n"); - return; - } - - dst_pib->timeStamp = 0; - dst_pib->picture_number = src_pib->ppb.picture_number; - dst_pib->width = src_pib->ppb.width; - dst_pib->height = src_pib->ppb.height; - dst_pib->chroma_format = src_pib->ppb.chroma_format; - dst_pib->pulldown = src_pib->ppb.pulldown; - dst_pib->flags = src_pib->ppb.flags; - dst_pib->sess_num = src_pib->ptsStcOffset; - dst_pib->aspect_ratio = src_pib->ppb.aspect_ratio; - dst_pib->colour_primaries = src_pib->ppb.colour_primaries; - dst_pib->picture_meta_payload = src_pib->ppb.picture_meta_payload; - dst_pib->frame_rate = src_pib->resolution; - return; -} - -static void crystalhd_hw_proc_pib(struct crystalhd_hw *hw) -{ - unsigned int cnt; - struct c011_pib src_pib; - uint32_t pib_addr, pib_cnt; - struct BC_PIC_INFO_BLOCK *AppPib; - struct crystalhd_rx_dma_pkt *rx_pkt = NULL; - - pib_cnt = crystalhd_get_pib_avail_cnt(hw); - - if (!pib_cnt) - return; - - for (cnt = 0; cnt < pib_cnt; cnt++) { - - pib_addr = crystalhd_get_addr_from_pib_Q(hw); - crystalhd_mem_rd(hw->adp, pib_addr, sizeof(struct c011_pib) / 4, - (uint32_t *)&src_pib); - - if (src_pib.bFormatChange) { - rx_pkt = (struct crystalhd_rx_dma_pkt *) - crystalhd_dioq_fetch(hw->rx_freeq); - if (!rx_pkt) - return; - rx_pkt->flags = 0; - rx_pkt->flags |= COMP_FLAG_PIB_VALID | - COMP_FLAG_FMT_CHANGE; - AppPib = &rx_pkt->pib; - cpy_pib_to_app(&src_pib, AppPib); - - BCMLOG(BCMLOG_DBG, - "App PIB:%x %x %x %x %x %x %x %x %x %x\n", - rx_pkt->pib.picture_number, - rx_pkt->pib.aspect_ratio, - rx_pkt->pib.chroma_format, - rx_pkt->pib.colour_primaries, - rx_pkt->pib.frame_rate, - rx_pkt->pib.height, - rx_pkt->pib.height, - rx_pkt->pib.n_drop, - rx_pkt->pib.pulldown, - rx_pkt->pib.ycom); - - crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, - rx_pkt->pkt_tag); - - } - - crystalhd_rel_addr_to_pib_Q(hw, pib_addr); - } -} - -static void crystalhd_start_rx_dma_engine(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl; - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - - return; -} - -static void crystalhd_stop_rx_dma_engine(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl = 0, count = 30; - uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if ((dma_cntrl & DMA_START_BIT)) { - dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if ((dma_cntrl & DMA_START_BIT)) { - dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - - /* Poll for 3seconds (30 * 100ms) on both the lists..*/ - while ((l0y || l0uv || l1y || l1uv) && count) { - - if (l0y) { - l0y = crystalhd_reg_rd(hw->adp, - MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); - l0y &= DMA_START_BIT; - if (!l0y) - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - } - - if (l1y) { - l1y = crystalhd_reg_rd(hw->adp, - MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); - l1y &= DMA_START_BIT; - if (!l1y) - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - } - - if (l0uv) { - l0uv = crystalhd_reg_rd(hw->adp, - MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); - l0uv &= DMA_START_BIT; - if (!l0uv) - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - } - - if (l1uv) { - l1uv = crystalhd_reg_rd(hw->adp, - MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); - l1uv &= DMA_START_BIT; - if (!l1uv) - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - } - msleep_interruptible(100); - count--; - } - - hw->rx_list_post_index = 0; - - BCMLOG(BCMLOG_SSTEP, "Capture Stop: %d List0:Sts:%x List1:Sts:%x\n", - count, hw->rx_list_sts[0], hw->rx_list_sts[1]); -} - -static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, - struct crystalhd_rx_dma_pkt *rx_pkt) -{ - uint32_t y_low_addr_reg, y_high_addr_reg; - uint32_t uv_low_addr_reg, uv_high_addr_reg; - union addr_64 desc_addr; - unsigned long flags; - - if (!hw || !rx_pkt) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { - BCMLOG_ERR("List Out Of bounds %x\n", hw->rx_list_post_index); - return BC_STS_INV_ARG; - } - - spin_lock_irqsave(&hw->rx_lock, flags); - /* FIXME: jarod: sts_free is an enum for 0, - in crystalhd_hw.h... yuk... */ - if (sts_free != hw->rx_list_sts[hw->rx_list_post_index]) { - spin_unlock_irqrestore(&hw->rx_lock, flags); - return BC_STS_BUSY; - } - - if (!hw->rx_list_post_index) { - y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0; - y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0; - uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0; - uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0; - } else { - y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1; - y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1; - uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1; - uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1; - } - rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; - if (rx_pkt->uv_phy_addr) - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; - hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; - spin_unlock_irqrestore(&hw->rx_lock, flags); - - crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, - rx_pkt->pkt_tag); - - crystalhd_start_rx_dma_engine(hw); - /* Program the Y descriptor */ - desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; - crystalhd_reg_wr(hw->adp, y_high_addr_reg, desc_addr.high_part); - crystalhd_reg_wr(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01); - - if (rx_pkt->uv_phy_addr) { - /* Program the UV descriptor */ - desc_addr.full_addr = rx_pkt->uv_phy_addr; - crystalhd_reg_wr(hw->adp, uv_high_addr_reg, - desc_addr.high_part); - crystalhd_reg_wr(hw->adp, uv_low_addr_reg, - desc_addr.low_part | 0x01); - } - - return BC_STS_SUCCESS; -} - -static enum BC_STATUS crystalhd_hw_post_cap_buff(struct crystalhd_hw *hw, - struct crystalhd_rx_dma_pkt *rx_pkt) -{ - enum BC_STATUS sts = crystalhd_hw_prog_rxdma(hw, rx_pkt); - - if (sts == BC_STS_BUSY) - crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, - false, rx_pkt->pkt_tag); - - return sts; -} - -static void crystalhd_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, - uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) -{ - uint32_t y_dn_sz_reg, uv_dn_sz_reg; - - if (!list_index) { - y_dn_sz_reg = MISC1_Y_RX_LIST0_CUR_BYTE_CNT; - uv_dn_sz_reg = MISC1_UV_RX_LIST0_CUR_BYTE_CNT; - } else { - y_dn_sz_reg = MISC1_Y_RX_LIST1_CUR_BYTE_CNT; - uv_dn_sz_reg = MISC1_UV_RX_LIST1_CUR_BYTE_CNT; - } - - *y_dw_dnsz = crystalhd_reg_rd(hw->adp, y_dn_sz_reg); - *uv_dw_dnsz = crystalhd_reg_rd(hw->adp, uv_dn_sz_reg); -} - -/* - * This function should be called only after making sure that the two DMA - * lists are free. This function does not check if DMA's are active, before - * turning off the DMA. - */ -static void crystalhd_hw_finalize_pause(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl, aspm; - - hw->stop_pending = 0; - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if (dma_cntrl & DMA_START_BIT) { - dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - - dma_cntrl = crystalhd_reg_rd(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if (dma_cntrl & DMA_START_BIT) { - dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, - MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - } - hw->rx_list_post_index = 0; - - aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); - aspm |= ASPM_L1_ENABLE; - /* NAREN BCMLOG(BCMLOG_INFO, "aspm on\n"); */ - crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); -} - -static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, - uint32_t list_index, enum BC_STATUS comp_sts) -{ - struct crystalhd_rx_dma_pkt *rx_pkt = NULL; - uint32_t y_dw_dnsz, uv_dw_dnsz; - enum BC_STATUS sts = BC_STS_SUCCESS; - - if (!hw || list_index >= DMA_ENGINE_CNT) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, - hw->rx_pkt_tag_seed + list_index); - if (!rx_pkt) { - BCMLOG_ERR( - "Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n", - hw->rx_list_post_index, hw->rx_list_sts[0], - hw->rx_list_sts[1], list_index, - hw->rx_pkt_tag_seed + list_index, comp_sts); - return BC_STS_INV_ARG; - } - - if (comp_sts == BC_STS_SUCCESS) { - crystalhd_get_dnsz(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz); - rx_pkt->dio_req->uinfo.y_done_sz = y_dw_dnsz; - rx_pkt->flags = COMP_FLAG_DATA_VALID; - if (rx_pkt->uv_phy_addr) - rx_pkt->dio_req->uinfo.uv_done_sz = uv_dw_dnsz; - crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true, - hw->rx_pkt_tag_seed + list_index); - return sts; - } - - /* Check if we can post this DIO again. */ - return crystalhd_hw_post_cap_buff(hw, rx_pkt); -} - -static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, - uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) -{ - uint32_t tmp; - enum list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[0]; - - /* Y0 - DMA */ - tmp = y_err_sts & GET_Y0_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV0 - DMA */ - tmp = uv_err_sts & GET_UV0_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & - MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y0_ERR_MSK) { - tmp = y_err_sts & GET_Y0_ERR_MSK; - crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV0_ERR_MSK) { - tmp = uv_err_sts & GET_UV0_ERR_MSK; - crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[0]); -} - -static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, - uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) -{ - uint32_t tmp; - enum list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[1]; - - /* Y1 - DMA */ - tmp = y_err_sts & GET_Y1_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - /* Add retry-support..*/ - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV1 - DMA */ - tmp = uv_err_sts & GET_UV1_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - /* Add retry-support*/ - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y1_ERR_MSK) { - tmp = y_err_sts & GET_Y1_ERR_MSK; - crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV1_ERR_MSK) { - tmp = uv_err_sts & GET_UV1_ERR_MSK; - crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[1]); -} - - -static void crystalhd_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) -{ - unsigned long flags; - uint32_t i, list_avail = 0; - enum BC_STATUS comp_sts = BC_STS_NO_DATA; - uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; - bool ret = false; - - if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); - return; - } - - if (!(intr_sts & GET_RX_INTR_MASK)) - return; - - y_err_sts = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_ERROR_STATUS); - uv_err_sts = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_ERROR_STATUS); - - for (i = 0; i < DMA_ENGINE_CNT; i++) { - /* Update States..*/ - spin_lock_irqsave(&hw->rx_lock, flags); - if (i == 0) - ret = crystalhd_rx_list0_handler(hw, intr_sts, - y_err_sts, uv_err_sts); - else - ret = crystalhd_rx_list1_handler(hw, intr_sts, - y_err_sts, uv_err_sts); - if (ret) { - switch (hw->rx_list_sts[i]) { - case sts_free: - comp_sts = BC_STS_SUCCESS; - list_avail = 1; - break; - case rx_y_error: - case rx_uv_error: - case rx_sts_error: - /* We got error on both or Y or uv. */ - hw->stats.rx_errors++; - crystalhd_get_dnsz(hw, i, &y_dn_sz, &uv_dn_sz); - /* FIXME: jarod: this is where - my mini pci-e card is tripping up */ - BCMLOG(BCMLOG_DBG, "list_index:%x rx[%d] Y:%x UV:%x Int:%x YDnSz:%x UVDnSz:%x\n", - i, hw->stats.rx_errors, y_err_sts, - uv_err_sts, intr_sts, y_dn_sz, - uv_dn_sz); - hw->rx_list_sts[i] = sts_free; - comp_sts = BC_STS_ERROR; - break; - default: - /* Wait for completion..*/ - comp_sts = BC_STS_NO_DATA; - break; - } - } - spin_unlock_irqrestore(&hw->rx_lock, flags); - - /* handle completion...*/ - if (comp_sts != BC_STS_NO_DATA) { - crystalhd_rx_pkt_done(hw, i, comp_sts); - comp_sts = BC_STS_NO_DATA; - } - } - - if (list_avail) { - if (hw->stop_pending) { - if ((hw->rx_list_sts[0] == sts_free) && - (hw->rx_list_sts[1] == sts_free)) - crystalhd_hw_finalize_pause(hw); - } else { - crystalhd_hw_start_capture(hw); - } - } -} - -static enum BC_STATUS crystalhd_fw_cmd_post_proc(struct crystalhd_hw *hw, - struct BC_FW_CMD *fw_cmd) -{ - enum BC_STATUS sts = BC_STS_SUCCESS; - struct dec_rsp_channel_start_video *st_rsp = NULL; - - switch (fw_cmd->cmd[0]) { - case eCMD_C011_DEC_CHAN_START_VIDEO: - st_rsp = (struct dec_rsp_channel_start_video *)fw_cmd->rsp; - hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; - hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; - BCMLOG(BCMLOG_DBG, "DelQAddr:%x RelQAddr:%x\n", - hw->pib_del_Q_addr, hw->pib_rel_Q_addr); - break; - case eCMD_C011_INIT: - if (!(crystalhd_load_firmware_config(hw->adp))) { - BCMLOG_ERR("Invalid Params.\n"); - sts = BC_STS_FW_AUTH_FAILED; - } - break; - default: - break; - } - return sts; -} - -static enum BC_STATUS crystalhd_put_ddr2sleep(struct crystalhd_hw *hw) -{ - uint32_t reg; - union link_misc_perst_decoder_ctrl rst_cntrl_reg; - - /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ - rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, - MISC_PERST_DECODER_CTRL); - - rst_cntrl_reg.bcm_7412_rst = 1; - crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, - rst_cntrl_reg.whole_reg); - msleep_interruptible(50); - - rst_cntrl_reg.bcm_7412_rst = 0; - crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, - rst_cntrl_reg.whole_reg); - - /* Close all banks, put DDR in idle */ - bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0); - - /* Set bit 25 (drop CKE pin of DDR) */ - reg = bc_dec_reg_rd(hw->adp, SDRAM_PARAM); - reg |= 0x02000000; - bc_dec_reg_wr(hw->adp, SDRAM_PARAM, reg); - - /* Reset the audio block */ - bc_dec_reg_wr(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1); - - /* Power down Raptor PLL */ - reg = bc_dec_reg_rd(hw->adp, DecHt_PllCCtl); - reg |= 0x00008000; - bc_dec_reg_wr(hw->adp, DecHt_PllCCtl, reg); - - /* Power down all Audio PLL */ - bc_dec_reg_wr(hw->adp, AIO_MISC_PLL_RESET, 0x1); - - /* Power down video clock (75MHz) */ - reg = bc_dec_reg_rd(hw->adp, DecHt_PllECtl); - reg |= 0x00008000; - bc_dec_reg_wr(hw->adp, DecHt_PllECtl, reg); - - /* Power down video clock (75MHz) */ - reg = bc_dec_reg_rd(hw->adp, DecHt_PllDCtl); - reg |= 0x00008000; - bc_dec_reg_wr(hw->adp, DecHt_PllDCtl, reg); - - /* Power down core clock (200MHz) */ - reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); - reg |= 0x00008000; - bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg); - - /* Power down core clock (200MHz) */ - reg = bc_dec_reg_rd(hw->adp, DecHt_PllBCtl); - reg |= 0x00008000; - bc_dec_reg_wr(hw->adp, DecHt_PllBCtl, reg); - - return BC_STS_SUCCESS; -} - -/************************************************ -** -*************************************************/ - -enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, - uint32_t sz) -{ - uint32_t reg_data, cnt, *temp_buff; - uint32_t fw_sig_len = 36; - uint32_t dram_offset = BC_FWIMG_ST_ADDR, sig_reg; - - - if (!adp || !buffer || !sz) { - BCMLOG_ERR("Invalid Params.\n"); - return BC_STS_INV_ARG; - } - - reg_data = crystalhd_reg_rd(adp, OTP_CMD); - if (!(reg_data & 0x02)) { - BCMLOG_ERR("Invalid hw config.. otp not programmed\n"); - return BC_STS_ERROR; - } - - reg_data = 0; - crystalhd_reg_wr(adp, DCI_CMD, 0); - reg_data |= BC_BIT(0); - crystalhd_reg_wr(adp, DCI_CMD, reg_data); - - reg_data = 0; - cnt = 1000; - msleep_interruptible(10); - - while (reg_data != BC_BIT(4)) { - reg_data = crystalhd_reg_rd(adp, DCI_STATUS); - reg_data &= BC_BIT(4); - if (--cnt == 0) { - BCMLOG_ERR("Firmware Download RDY Timeout.\n"); - return BC_STS_TIMEOUT; - } - } - - msleep_interruptible(10); - /* Load the FW to the FW_ADDR field in the DCI_FIRMWARE_ADDR */ - crystalhd_reg_wr(adp, DCI_FIRMWARE_ADDR, dram_offset); - temp_buff = (uint32_t *)buffer; - for (cnt = 0; cnt < (sz - fw_sig_len); cnt += 4) { - crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19)); - crystalhd_reg_wr(adp, DCI_FIRMWARE_DATA, *temp_buff); - dram_offset += 4; - temp_buff++; - } - msleep_interruptible(10); - - temp_buff++; - - sig_reg = (uint32_t)DCI_SIGNATURE_DATA_7; - for (cnt = 0; cnt < 8; cnt++) { - uint32_t swapped_data = *temp_buff; - swapped_data = bswap_32_1(swapped_data); - crystalhd_reg_wr(adp, sig_reg, swapped_data); - sig_reg -= 4; - temp_buff++; - } - msleep_interruptible(10); - - reg_data = 0; - reg_data |= BC_BIT(1); - crystalhd_reg_wr(adp, DCI_CMD, reg_data); - msleep_interruptible(10); - - reg_data = 0; - reg_data = crystalhd_reg_rd(adp, DCI_STATUS); - - if ((reg_data & BC_BIT(9)) == BC_BIT(9)) { - cnt = 1000; - while ((reg_data & BC_BIT(0)) != BC_BIT(0)) { - reg_data = crystalhd_reg_rd(adp, DCI_STATUS); - reg_data &= BC_BIT(0); - if (!(--cnt)) - break; - msleep_interruptible(10); - } - reg_data = 0; - reg_data = crystalhd_reg_rd(adp, DCI_CMD); - reg_data |= BC_BIT(4); - crystalhd_reg_wr(adp, DCI_CMD, reg_data); - - } else { - BCMLOG_ERR("F/w Signature mismatch\n"); - return BC_STS_FW_AUTH_FAILED; - } - - BCMLOG(BCMLOG_INFO, "Firmware Downloaded Successfully\n"); - return BC_STS_SUCCESS; -} - -enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, - struct BC_FW_CMD *fw_cmd) -{ - uint32_t cnt = 0, cmd_res_addr; - uint32_t *cmd_buff, *res_buff; - wait_queue_head_t fw_cmd_event; - int rc = 0; - enum BC_STATUS sts; - - crystalhd_create_event(&fw_cmd_event); - - if (!hw || !fw_cmd) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - cmd_buff = fw_cmd->cmd; - res_buff = fw_cmd->rsp; - - if (!cmd_buff || !res_buff) { - BCMLOG_ERR("Invalid Parameters for F/W Command\n"); - return BC_STS_INV_ARG; - } - - hw->pwr_lock++; - - hw->fwcmd_evt_sts = 0; - hw->pfw_cmd_event = &fw_cmd_event; - - /*Write the command to the memory*/ - crystalhd_mem_wr(hw->adp, TS_Host2CpuSnd, FW_CMD_BUFF_SZ, cmd_buff); - - /*Memory Read for memory arbitrator flush*/ - crystalhd_mem_rd(hw->adp, TS_Host2CpuSnd, 1, &cnt); - - /* Write the command address to mailbox */ - bc_dec_reg_wr(hw->adp, Hst2CpuMbx1, TS_Host2CpuSnd); - msleep_interruptible(50); - - crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, 20000, rc, 0); - - if (!rc) { - sts = BC_STS_SUCCESS; - } else if (rc == -EBUSY) { - BCMLOG_ERR("Firmware command T/O\n"); - sts = BC_STS_TIMEOUT; - } else if (rc == -EINTR) { - BCMLOG(BCMLOG_DBG, "FwCmd Wait Signal int.\n"); - sts = BC_STS_IO_USER_ABORT; - } else { - BCMLOG_ERR("FwCmd IO Error.\n"); - sts = BC_STS_IO_ERROR; - } - - if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("FwCmd Failed.\n"); - hw->pwr_lock--; - return sts; - } - - /*Get the Response Address*/ - cmd_res_addr = bc_dec_reg_rd(hw->adp, Cpu2HstMbx1); - - /*Read the Response*/ - crystalhd_mem_rd(hw->adp, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); - - hw->pwr_lock--; - - if (res_buff[2] != C011_RET_SUCCESS) { - BCMLOG_ERR("res_buff[2] != C011_RET_SUCCESS\n"); - return BC_STS_FW_CMD_ERR; + rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, + hw->rx_pkt_tag_seed + list_index); + if (!rx_pkt) { + dev_err(&hw->adp->pdev->dev, "Act-Q: PostIx:%x L0Sts:%x " + "L1Sts:%x current L:%x tag:%x comp:%x\n", + hw->rx_list_post_index, hw->rx_list_sts[0], + hw->rx_list_sts[1], list_index, + hw->rx_pkt_tag_seed + list_index, comp_sts); + return BC_STS_INV_ARG; } - sts = crystalhd_fw_cmd_post_proc(hw, fw_cmd); - if (sts != BC_STS_SUCCESS) - BCMLOG_ERR("crystalhd_fw_cmd_post_proc Failed.\n"); - - return sts; -} - -bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw) -{ - uint32_t intr_sts = 0; - uint32_t deco_intr = 0; - bool rc = false; - - if (!adp || !hw->dev_started) - return rc; + if (comp_sts == BC_STS_SUCCESS) + { + hw->DrvTotalFrmCaptured++; - hw->stats.num_interrupts++; - hw->pwr_lock++; - - deco_intr = bc_dec_reg_rd(adp, Stream2Host_Intr_Sts); - intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS); + hw->pfnHWGetDoneSize(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz); + rx_pkt->dio_req->uinfo.y_done_sz = y_dw_dnsz; + rx_pkt->flags = COMP_FLAG_DATA_VALID; + if (rx_pkt->uv_phy_addr) + rx_pkt->dio_req->uinfo.uv_done_sz = uv_dw_dnsz; + crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true, + hw->rx_pkt_tag_seed + list_index); - if (intr_sts) { - /* let system know we processed interrupt..*/ - rc = true; - hw->stats.dev_interrupts++; - } + if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) + { + /*printk("pre-PD state %x RLL %x Ptsh %x ratio %d currentPS %d\n", */ + /* hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->PauseThreshold, hw->PDRatio, hw->FleaPowerState); */ + if(hw->FleaPowerState == FLEA_PS_ACTIVE) + { + if(crystalhd_dioq_count(hw->rx_rdyq) >= hw->PauseThreshold) + { + hw->pfnIssuePause(hw, true); + hw->hw_pause_issued = true; + } + /* NAREN check if the PD ratio is less than 50. If so, try to reduce the PauseThreshold to improve the ratio */ + /* never go lower than 6 pictures */ + /* Only do this when we have some data to determine PDRatio */ + /* For now assume that if we have captured 100 pictures then we should have enough data for the analysis to start */ + if((hw->PDRatio < 50) && (hw->PauseThreshold > 6) && (hw->DrvTotalFrmCaptured > 100)) + { + /*printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u decress PauseThreshold\n", */ + /* hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); */ + hw->PauseThreshold--; + } + else { + rdtscll(currTick); + + temp_64 = (hw->TickSpentInPD)>>24; + TickSpentInPD_Hi = (uint32_t)(temp_64); + TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; + + temp_64 = (currTick - hw->TickCntDecodePU)>>24; + totalTick_Hi = (uint32_t)(temp_64); + totalTick_Hi_f = (int32_t)totalTick_Hi; + + if( totalTick_Hi_f <= 0 ) + { + temp_64 = (hw->TickSpentInPD); + TickSpentInPD_Hi = (uint32_t)(temp_64); + TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; + + temp_64 = (currTick - hw->TickCntDecodePU); + totalTick_Hi = (uint32_t)(temp_64); + totalTick_Hi_f = (int32_t)totalTick_Hi; + } + + if( totalTick_Hi_f <= 0 ) + { + printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); + hw->PDRatio = 60; + } + else + hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; - if (deco_intr && (deco_intr != 0xdeaddead)) { + /*printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u don't decress PauseThreshold\n", */ + /* hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); */ - if (deco_intr & 0x80000000) { - /*Set the Event and the status flag*/ - if (hw->pfw_cmd_event) { - hw->fwcmd_evt_sts = 1; - crystalhd_set_event(hw->pfw_cmd_event); + /*hw->PDRatio = ((uint32_t)(hw->TickSpentInPD))/((uint32_t)(currTick - hw->TickCntDecodePU)/100); */ + } } } - - if (deco_intr & BC_BIT(1)) - crystalhd_hw_proc_pib(hw); - - bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, deco_intr); - /* FIXME: jarod: No udelay? might this be - the real reason mini pci-e cards were stalling out? */ - bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, 0); - rc = true; - } - - /* Rx interrupts */ - crystalhd_rx_isr(hw, intr_sts); - - /* Tx interrupts*/ - crystalhd_tx_isr(hw, intr_sts); - - /* Clear interrupts */ - if (rc) { - if (intr_sts) - crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts); - - crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1); - } - - hw->pwr_lock--; - - return rc; -} - -enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, - struct crystalhd_adp *adp) -{ - if (!hw || !adp) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - if (hw->dev_started) - return BC_STS_SUCCESS; - - memset(hw, 0, sizeof(struct crystalhd_hw)); - - hw->adp = adp; - spin_lock_init(&hw->lock); - spin_lock_init(&hw->rx_lock); - /* FIXME: jarod: what are these magic numbers?!? */ - hw->tx_ioq_tag_seed = 0x70023070; - hw->rx_pkt_tag_seed = 0x70029070; - - hw->stop_pending = 0; - crystalhd_start_device(hw->adp); - hw->dev_started = true; - - /* set initial core clock */ - hw->core_clock_mhz = CLOCK_PRESET; - hw->prev_n = 0; - hw->pwr_lock = 0; - crystalhd_hw_set_core_clock(hw); - - return BC_STS_SUCCESS; -} - -enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw) -{ - if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - if (!hw->dev_started) - return BC_STS_SUCCESS; - - /* Stop and DDR sleep will happen in here */ - crystalhd_hw_suspend(hw); - hw->dev_started = false; - - return BC_STS_SUCCESS; -} - -enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) -{ - unsigned int i; - void *mem; - size_t mem_len; - dma_addr_t phy_addr; - enum BC_STATUS sts = BC_STS_SUCCESS; - struct crystalhd_rx_dma_pkt *rpkt; - - if (!hw || !hw->adp) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - sts = crystalhd_hw_create_ioqs(hw); - if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("Failed to create IOQs..\n"); - return sts; - } - - mem_len = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); - - for (i = 0; i < BC_TX_LIST_CNT; i++) { - mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); - if (mem) { - memset(mem, 0, mem_len); - } else { - BCMLOG_ERR("Insufficient Memory For TX\n"); - crystalhd_hw_free_dma_rings(hw); - return BC_STS_INSUFF_RES; - } - /* rx_pkt_pool -- static memory allocation */ - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem; - hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr; - hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS * - sizeof(struct dma_descriptor); - hw->tx_pkt_pool[i].list_tag = 0; - - /* Add TX dma requests to Free Queue..*/ - sts = crystalhd_dioq_add(hw->tx_freeq, - &hw->tx_pkt_pool[i], false, 0); - if (sts != BC_STS_SUCCESS) { - crystalhd_hw_free_dma_rings(hw); - return sts; - } - } - - for (i = 0; i < BC_RX_LIST_CNT; i++) { - rpkt = kzalloc(sizeof(*rpkt), GFP_KERNEL); - if (!rpkt) { - BCMLOG_ERR("Insufficient Memory For RX\n"); - crystalhd_hw_free_dma_rings(hw); - return BC_STS_INSUFF_RES; - } - - mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); - if (mem) { - memset(mem, 0, mem_len); - } else { - BCMLOG_ERR("Insufficient Memory For RX\n"); - crystalhd_hw_free_dma_rings(hw); - kfree(rpkt); - return BC_STS_INSUFF_RES; + else if( hw->hw_pause_issued == false ) + { +#if 0 + if(crystalhd_dioq_count(hw->rx_rdyq) > hw->PauseThreshold)/*HW_PAUSE_THRESHOLD */ + { + dev_info(&hw->adp->pdev->dev, "HW PAUSE\n"); + hw->pfnIssuePause(hw, true); + hw->hw_pause_issued = true; + } +#endif } - rpkt->desc_mem.pdma_desc_start = mem; - rpkt->desc_mem.phy_addr = phy_addr; - rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * - sizeof(struct dma_descriptor); - rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; - crystalhd_hw_free_rx_pkt(hw, rpkt); - } - - return BC_STS_SUCCESS; -} - -enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) -{ - unsigned int i; - struct crystalhd_rx_dma_pkt *rpkt = NULL; - - if (!hw || !hw->adp) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - /* Delete all IOQs.. */ - crystalhd_hw_delete_ioqs(hw); - - for (i = 0; i < BC_TX_LIST_CNT; i++) { - if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) { - bc_kern_dma_free(hw->adp, - hw->tx_pkt_pool[i].desc_mem.sz, - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start, - hw->tx_pkt_pool[i].desc_mem.phy_addr); - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL; - } + return sts; } - - BCMLOG(BCMLOG_DBG, "Releasing RX Pkt pool\n"); - do { - rpkt = crystalhd_hw_alloc_rx_pkt(hw); - if (!rpkt) - break; - bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz, - rpkt->desc_mem.pdma_desc_start, - rpkt->desc_mem.phy_addr); - kfree(rpkt); - } while (rpkt); - - return BC_STS_SUCCESS; + /* Check if we can post this DIO again. */ + return hw->pfnPostRxSideBuff(hw, rx_pkt); } -enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, +BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags) { + struct device *dev; struct tx_dma_pkt *tx_dma_packet = NULL; - uint32_t first_desc_u_addr, first_desc_l_addr; uint32_t low_addr, high_addr; - union addr_64 desc_addr; - enum BC_STATUS sts, add_sts; + addr_64 desc_addr; + BC_STATUS sts, add_sts; uint32_t dummy_index = 0; unsigned long flags; + uint8_t list_posted; + uint8_t local_flags = data_flags; bool rc; + uint32_t destDRAMaddr = 0; if (!hw || !ioreq || !call_back || !cb_event || !list_id) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } + dev = &hw->adp->pdev->dev; + /* * Since we hit code in busy condition very frequently, * we will check the code in status first before @@ -2098,35 +740,37 @@ enum BC_STATUS crystalhd_hw_post_tx(stru * * This will avoid the Q fetch/add in normal condition. */ - rc = crystalhd_code_in_full(hw->adp, ioreq->uinfo.xfr_len, - false, data_flags); + + rc = hw->pfnCheckInputFIFO(hw, ioreq->uinfo.xfr_len, + &dummy_index, false, &local_flags); + if (rc) { hw->stats.cin_busy++; return BC_STS_BUSY; } + if(local_flags & BC_BIT(7)) + destDRAMaddr = hw->TxFwInputBuffInfo.DramBuffAdd; + /* Get a list from TxFreeQ */ - tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch( - hw->tx_freeq); + tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq); if (!tx_dma_packet) { - BCMLOG_ERR("No empty elements..\n"); - return BC_STS_ERR_USAGE; + dev_err(dev, "No empty elements..\n"); + return BC_STS_INSUFF_RES; } sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, - &tx_dma_packet->desc_mem, - &dummy_index); + &tx_dma_packet->desc_mem, + &dummy_index, dev, destDRAMaddr); if (sts != BC_STS_SUCCESS) { add_sts = crystalhd_dioq_add(hw->tx_freeq, tx_dma_packet, false, 0); if (add_sts != BC_STS_SUCCESS) - BCMLOG_ERR("double fault..\n"); + dev_err(dev, "double fault..\n"); return sts; } - hw->pwr_lock++; - desc_addr.full_addr = tx_dma_packet->desc_mem.phy_addr; low_addr = desc_addr.low_part; high_addr = desc_addr.high_part; @@ -2137,21 +781,20 @@ enum BC_STATUS crystalhd_hw_post_tx(stru spin_lock_irqsave(&hw->lock, flags); - if (hw->tx_list_post_index == 0) { - first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST0; - first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST0; - } else { - first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST1; - first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST1; - } + list_posted = hw->tx_list_post_index; *list_id = tx_dma_packet->list_tag = hw->tx_ioq_tag_seed + hw->tx_list_post_index; - hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT; - spin_unlock_irqrestore(&hw->lock, flags); + if( hw->tx_list_post_index % DMA_ENGINE_CNT) { + hw->TxList1Sts |= TxListWaitingForIntr; + } + else { + hw->TxList0Sts |= TxListWaitingForIntr; + } + hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT; /* Insert in Active Q..*/ crystalhd_dioq_add(hw->tx_actq, tx_dma_packet, false, @@ -2162,12 +805,13 @@ enum BC_STATUS crystalhd_hw_post_tx(stru * the valid bit. So be ready for that. All * the initialization should happen before that. */ - crystalhd_start_tx_dma_engine(hw); - crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part); - crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | - 0x01); - /* Be sure we set the valid bit ^^^^ */ + /* Save the transfer length */ + hw->TxFwInputBuffInfo.HostXferSzInBytes = ioreq->uinfo.xfr_len; + + hw->pfnStartTxDMA(hw, list_posted, desc_addr); + + spin_unlock_irqrestore(&hw->lock, flags); return BC_STS_SUCCESS; } @@ -2181,35 +825,37 @@ enum BC_STATUS crystalhd_hw_post_tx(stru * * FIX_ME: Not Tested the actual condition.. */ -enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, - uint32_t list_id) +BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) { + unsigned long flags; if (!hw || !list_id) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } - crystalhd_stop_tx_dma_engine(hw); + spin_lock_irqsave(&hw->lock, flags); + hw->pfnStopTxDMA(hw); + spin_unlock_irqrestore(&hw->lock, flags); crystalhd_hw_tx_req_complete(hw, list_id, BC_STS_IO_USER_ABORT); return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, bool en_post) +BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, + struct crystalhd_dio_req *ioreq, bool en_post) { struct crystalhd_rx_dma_pkt *rpkt; uint32_t tag, uv_desc_ix = 0; - enum BC_STATUS sts; + BC_STATUS sts; if (!hw || !ioreq) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } rpkt = crystalhd_hw_alloc_rx_pkt(hw); if (!rpkt) { - BCMLOG_ERR("Insufficient resources\n"); + dev_err(&hw->adp->pdev->dev, "Insufficient resources\n"); return BC_STS_INSUFF_RES; } @@ -2217,7 +863,7 @@ enum BC_STATUS crystalhd_hw_add_cap_buff tag = rpkt->pkt_tag; sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, - &uv_desc_ix); + &uv_desc_ix, &hw->adp->pdev->dev, 0); if (sts != BC_STS_SUCCESS) return sts; @@ -2226,35 +872,60 @@ enum BC_STATUS crystalhd_hw_add_cap_buff /* Store the address of UV in the rx packet for post*/ if (uv_desc_ix) rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr + - (sizeof(struct dma_descriptor) * (uv_desc_ix + 1)); + (sizeof(struct dma_descriptor) * (uv_desc_ix + 1)); - if (en_post) - sts = crystalhd_hw_post_cap_buff(hw, rpkt); - else + if (en_post && !hw->hw_pause_issued) { + sts = hw->pfnPostRxSideBuff(hw, rpkt); + } + else { sts = crystalhd_dioq_add(hw->rx_freeq, rpkt, false, tag); + hw->pfnNotifyFLLChange(hw, false); + } return sts; } -enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, - struct BC_PIC_INFO_BLOCK *pib, - struct crystalhd_dio_req **ioreq) +BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, + struct C011_PIB *pib, + struct crystalhd_dio_req **ioreq) { struct crystalhd_rx_dma_pkt *rpkt; uint32_t timeout = BC_PROC_OUTPUT_TIMEOUT / 1000; uint32_t sig_pending = 0; - if (!hw || !ioreq || !pib) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } - rpkt = crystalhd_dioq_fetch_wait(hw->rx_rdyq, timeout, &sig_pending); + rpkt = crystalhd_dioq_fetch_wait(hw, timeout, &sig_pending); + + if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) + { + /*printk("pre-PU state %x RLL %x Rtsh %x, currentPS %d,\n", */ + /* hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->ResumeThreshold, hw->FleaPowerState); */ + if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) || + (hw->FleaPowerState == FLEA_PS_LP_COMPLETE)) + { + if(crystalhd_dioq_count(hw->rx_rdyq) <= hw->ResumeThreshold) + hw->pfnIssuePause(hw, false); /*Need this Notification For Flea*/ + hw->hw_pause_issued = false; + } + } + else if( hw->hw_pause_issued) + { +#if 0 + if(crystalhd_dioq_count(hw->rx_rdyq) < hw->PauseThreshold ) /*HW_RESUME_THRESHOLD */ + { + dev_info(&hw->adp->pdev->dev, "HW RESUME with rdy list %u \n",crystalhd_dioq_count(hw->rx_rdyq)); + hw->pfnIssuePause(hw, false); + hw->hw_pause_issued = false; + } +#endif + } + if (!rpkt) { if (sig_pending) { - BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n", - sig_pending); return BC_STS_IO_USER_ABORT; } else { return BC_STS_TIMEOUT; @@ -2264,7 +935,19 @@ enum BC_STATUS crystalhd_hw_get_cap_buff rpkt->dio_req->uinfo.comp_flags = rpkt->flags; if (rpkt->flags & COMP_FLAG_PIB_VALID) - memcpy(pib, &rpkt->pib, sizeof(*pib)); + { + pib->ppb.picture_number = rpkt->pib.picture_number; + pib->ppb.width = rpkt->pib.width; + pib->ppb.height = rpkt->pib.height; + pib->ppb.chroma_format = rpkt->pib.chroma_format; + pib->ppb.pulldown = rpkt->pib.pulldown; + pib->ppb.flags = rpkt->pib.flags; + pib->ptsStcOffset = rpkt->pib.sess_num; + pib->ppb.aspect_ratio = rpkt->pib.aspect_ratio; + pib->ppb.colour_primaries = rpkt->pib.colour_primaries; + pib->ppb.picture_meta_payload = rpkt->pib.picture_meta_payload; + pib->resolution = rpkt->pib.frame_rate; + } *ioreq = rpkt->dio_req; @@ -2273,14 +956,14 @@ enum BC_STATUS crystalhd_hw_get_cap_buff return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw) +BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw) { struct crystalhd_rx_dma_pkt *rx_pkt; - enum BC_STATUS sts; + BC_STATUS sts; uint32_t i; if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } @@ -2289,7 +972,7 @@ enum BC_STATUS crystalhd_hw_start_captur rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (!rx_pkt) return BC_STS_NO_DATA; - sts = crystalhd_hw_post_cap_buff(hw, rx_pkt); + sts = hw->pfnPostRxSideBuff(hw, rx_pkt); if (BC_STS_SUCCESS != sts) break; @@ -2298,87 +981,90 @@ enum BC_STATUS crystalhd_hw_start_captur return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw) +BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap) { void *temp = NULL; if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } - crystalhd_stop_rx_dma_engine(hw); + hw->pfnStopRXDMAEngines(hw); + + if(!unmap) + return BC_STS_SUCCESS; + /* Clear up Active, Ready and Free lists one by one and release resources */ do { - temp = crystalhd_dioq_fetch(hw->rx_freeq); + temp = crystalhd_dioq_fetch(hw->rx_actq); if (temp) crystalhd_rx_pkt_rel_call_back(hw, temp); } while (temp); - return BC_STS_SUCCESS; -} - -enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw) -{ - hw->stats.pause_cnt++; - hw->stop_pending = 1; + do { + temp = crystalhd_dioq_fetch(hw->rx_rdyq); + if (temp) + crystalhd_rx_pkt_rel_call_back(hw, temp); + } while (temp); - if ((hw->rx_list_sts[0] == sts_free) && - (hw->rx_list_sts[1] == sts_free)) - crystalhd_hw_finalize_pause(hw); + do { + temp = crystalhd_dioq_fetch(hw->rx_freeq); + if (temp) + crystalhd_rx_pkt_rel_call_back(hw, temp); + } while (temp); return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw) +BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) { - enum BC_STATUS sts; - uint32_t aspm; - - hw->stop_pending = 0; + if (!hw) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } - aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); - aspm &= ~ASPM_L1_ENABLE; -/* NAREN BCMLOG(BCMLOG_INFO, "aspm off\n"); */ - crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); + if (!hw->pfnStopDevice(hw)) { + dev_info(&hw->adp->pdev->dev, "Failed to Stop Device!!\n"); + return BC_STS_ERROR; + } - sts = crystalhd_hw_start_capture(hw); - return sts; + return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) +BC_STATUS crystalhd_hw_resume(struct crystalhd_hw *hw) { - enum BC_STATUS sts; - if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } - sts = crystalhd_put_ddr2sleep(hw); - if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("Failed to Put DDR To Sleep!!\n"); - return BC_STS_ERROR; - } + // Reset list state + hw->rx_list_sts[0] = sts_free; + hw->rx_list_sts[1] = sts_free; + hw->TxList0Sts = ListStsFree; + hw->TxList1Sts = ListStsFree; + hw->rx_list_post_index = 0; + hw->tx_list_post_index = 0; - if (!crystalhd_stop_device(hw->adp)) { - BCMLOG_ERR("Failed to Stop Device!!\n"); + if (hw->pfnStartDevice(hw)) { + dev_info(&hw->adp->pdev->dev, "Failed to Start Device!!\n"); return BC_STS_ERROR; } return BC_STS_SUCCESS; } -void crystalhd_hw_stats(struct crystalhd_hw *hw, - struct crystalhd_hw_stats *stats) +void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats) { if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return; } /* if called w/NULL stats, its a req to zero out the stats */ if (!stats) { + hw->DrvTotalFrmCaptured = 0; memset(&hw->stats, 0, sizeof(hw->stats)); return; } @@ -2387,70 +1073,3 @@ void crystalhd_hw_stats(struct crystalhd hw->stats.rdyq_count = crystalhd_dioq_count(hw->rx_rdyq); memcpy(stats, &hw->stats, sizeof(*stats)); } - -enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *hw) -{ - uint32_t reg, n, i; - uint32_t vco_mg, refresh_reg; - - if (!hw) { - BCMLOG_ERR("Invalid Arguments\n"); - return BC_STS_INV_ARG; - } - - /* FIXME: jarod: wha? */ - /*n = (hw->core_clock_mhz * 3) / 20 + 1; */ - n = hw->core_clock_mhz/5; - - if (n == hw->prev_n) - return BC_STS_CLK_NOCHG; - - if (hw->pwr_lock > 0) { - /* BCMLOG(BCMLOG_INFO,"pwr_lock is %u\n", hw->pwr_lock) */ - return BC_STS_CLK_NOCHG; - } - - i = n * 27; - if (i < 560) - vco_mg = 0; - else if (i < 900) - vco_mg = 1; - else if (i < 1030) - vco_mg = 2; - else - vco_mg = 3; - - reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); - - reg &= 0xFFFFCFC0; - reg |= n; - reg |= vco_mg << 12; - - BCMLOG(BCMLOG_INFO, "clock is moving to %d with n %d with vco_mg %d\n", - hw->core_clock_mhz, n, vco_mg); - - /* Change the DRAM refresh rate to accommodate the new frequency */ - /* refresh reg = ((refresh_rate * clock_rate)/16) - 1; rounding up*/ - refresh_reg = (7 * hw->core_clock_mhz / 16); - bc_dec_reg_wr(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | refresh_reg)); - - bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg); - - i = 0; - - for (i = 0; i < 10; i++) { - reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); - - if (reg & 0x00020000) { - hw->prev_n = n; - /* FIXME: jarod: outputting - a random "C" is... confusing... */ - BCMLOG(BCMLOG_INFO, "C"); - return BC_STS_SUCCESS; - } else { - msleep_interruptible(10); - } - } - BCMLOG(BCMLOG_INFO, "clk change failed\n"); - return BC_STS_CLK_NOCHG; -} --- crystalhd~/crystalhd_hw.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_hw.h 2015-04-06 20:15:30.000000000 +0300 @@ -26,168 +26,49 @@ #ifndef _CRYSTALHD_HW_H_ #define _CRYSTALHD_HW_H_ +#define DEBUG 1 -#include "crystalhd.h" +#include +#include +#include +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) +#include +#else +#include +#endif +#include "crystalhd_fw_if.h" +#include "crystalhd_misc.h" +#include "DriverFwShare.h" +#include "FleaDefs.h" /* HW constants..*/ #define DMA_ENGINE_CNT 2 #define MAX_PIB_Q_DEPTH 64 #define MIN_PIB_Q_DEPTH 2 #define WR_POINTER_OFF 4 +#define MAX_VALID_POLL_CNT 1000 -#define ASPM_L1_ENABLE (BC_BIT(27)) - -/************************************************* - 7412 Decoder Registers. -**************************************************/ -#define FW_CMD_BUFF_SZ 64 -#define TS_Host2CpuSnd 0x00000100 -#define Hst2CpuMbx1 0x00100F00 -#define Cpu2HstMbx1 0x00100F04 -#define MbxStat1 0x00100F08 -#define Stream2Host_Intr_Sts 0x00100F24 -#define C011_RET_SUCCESS 0x0 /* Return status of firmware command. */ - -/* TS input status register */ -#define TS_StreamAFIFOStatus 0x0010044C -#define TS_StreamBFIFOStatus 0x0010084C - -/*UART Selection definitions*/ -#define UartSelectA 0x00100300 -#define UartSelectB 0x00100304 - -#define BSVS_UART_DEC_NONE 0x00 -#define BSVS_UART_DEC_OUTER 0x01 -#define BSVS_UART_DEC_INNER 0x02 -#define BSVS_UART_STREAM 0x03 - -/* Code-In fifo */ -#define REG_DecCA_RegCinCTL 0xa00 -#define REG_DecCA_RegCinBase 0xa0c -#define REG_DecCA_RegCinEnd 0xa10 -#define REG_DecCA_RegCinWrPtr 0xa04 -#define REG_DecCA_RegCinRdPtr 0xa08 - -#define REG_Dec_TsUser0Base 0x100864 -#define REG_Dec_TsUser0Rdptr 0x100868 -#define REG_Dec_TsUser0Wrptr 0x10086C -#define REG_Dec_TsUser0End 0x100874 - -/* ASF Case ...*/ -#define REG_Dec_TsAudCDB2Base 0x10036c -#define REG_Dec_TsAudCDB2Rdptr 0x100378 -#define REG_Dec_TsAudCDB2Wrptr 0x100374 -#define REG_Dec_TsAudCDB2End 0x100370 - -/* DRAM bringup Registers */ -#define SDRAM_PARAM 0x00040804 -#define SDRAM_PRECHARGE 0x000408B0 -#define SDRAM_EXT_MODE 0x000408A4 -#define SDRAM_MODE 0x000408A0 -#define SDRAM_REFRESH 0x00040890 -#define SDRAM_REF_PARAM 0x00040808 - -#define DecHt_PllACtl 0x34000C -#define DecHt_PllBCtl 0x340010 -#define DecHt_PllCCtl 0x340014 -#define DecHt_PllDCtl 0x340034 -#define DecHt_PllECtl 0x340038 -#define AUD_DSP_MISC_SOFT_RESET 0x00240104 -#define AIO_MISC_PLL_RESET 0x0026000C -#define PCIE_CLK_REQ_REG 0xDC -#define PCI_CLK_REQ_ENABLE (BC_BIT(8)) - -/************************************************* - F/W Copy engine definitions.. -**************************************************/ -#define BC_FWIMG_ST_ADDR 0x00000000 -/* FIXME: jarod: there's a kernel function that'll do this for us... */ -#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n))) -#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) - -#define DecHt_HostSwReset 0x340000 -#define BC_DRAM_FW_CFG_ADDR 0x001c2000 - -union addr_64 { - struct { - uint32_t low_part; - uint32_t high_part; - }; +#define TX_WRAP_THRESHOLD 128 * 1024 - uint64_t full_addr; - -}; - -union intr_mask_reg { - struct { - uint32_t mask_tx_done:1; - uint32_t mask_tx_err:1; - uint32_t mask_rx_done:1; - uint32_t mask_rx_err:1; - uint32_t mask_pcie_err:1; - uint32_t mask_pcie_rbusmast_err:1; - uint32_t mask_pcie_rgr_bridge:1; - uint32_t reserved:25; - }; - - uint32_t whole_reg; - -}; - -union link_misc_perst_deco_ctrl { - struct { - uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held - in reset. Reset value 1.*/ - uint32_t reserved0:3; /* Reserved.No Effect*/ - uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of - 27MHz clk used to clk BCM7412*/ - uint32_t reserved1:27; /* Reserved. No Effect*/ - }; - - uint32_t whole_reg; - -}; - -union link_misc_perst_clk_ctrl { - struct { - uint32_t sel_alt_clk:1; /* When set, selects a - 6.75MHz clock as the source of core_clk */ - uint32_t stop_core_clk:1; /* When set, stops the branch - of core_clk that is not needed for low power operation */ - uint32_t pll_pwr_dn:1; /* When set, powers down the - main PLL. The alternate clock bit should be set to - select an alternate clock before setting this bit.*/ - uint32_t reserved0:5; /* Reserved */ - uint32_t pll_mult:8; /* This setting controls - the multiplier for the PLL. */ - uint32_t pll_div:4; /* This setting controls - the divider for the PLL. */ - uint32_t reserved1:12; /* Reserved */ - }; - - uint32_t whole_reg; - -}; - -union link_misc_perst_decoder_ctrl { - struct { - uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held - in reset. Reset value 1.*/ - uint32_t res0:3; /* Reserved.No Effect*/ - uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz - clk used to clk BCM7412*/ - uint32_t res1:27; /* Reserved. No Effect */ - }; - - uint32_t whole_reg; +#define NUMBER_OF_TRANSFERS_TX_SIDE 1 +#define NUMBER_OF_TRANSFERS_RX_SIDE 2 +struct BC_DRV_PIC_INFO { + struct C011_PIB DecoPIB; + struct BC_DRV_PIC_INFO *Flink; }; union desc_low_addr_reg { struct { +#ifdef __LITTLE_ENDIAN_BITFIELD uint32_t list_valid:1; uint32_t reserved:4; uint32_t low_addr:27; +#else + uint32_t low_addr:27; + uint32_t reserved:4; + uint32_t list_valid:1; +#endif }; uint32_t whole_reg; @@ -195,6 +76,7 @@ union desc_low_addr_reg { }; struct dma_descriptor { /* 8 32-bit values */ +#ifdef __LITTLE_ENDIAN_BITFIELD /* 0th u32 */ uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ uint32_t res0:4; /* bits 28-31: Reserved */ @@ -225,7 +107,38 @@ struct dma_descriptor { /* 8 32-bit valu /* 7th u32 */ uint32_t res8; /* Last 32bits reserved */ +#else + /* 0th u32 */ + uint32_t res0:4; /* bits 28-31: Reserved */ + uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ + /* 1st u32 */ + uint32_t buff_addr_low; /* 1 buffer address low */ + uint32_t buff_addr_high; /* 2 buffer address high */ + + /* 3rd u32 */ + uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ + uint32_t res3:6; /* 25-30 reserved */ + uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ + uint32_t res2:2; /* 0-1 - Reserved */ + + /* 4th u32 */ + uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ + uint32_t dma_dir:1; /* 30 bit DMA Direction */ + uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ + uint32_t res4:25; /* 3 - 27 Reserved bits */ + uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ + uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ + + /* 5th u32 */ + uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ + + /* 6th u32 */ + uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ + + /* 7th u32 */ + uint32_t res8; /* Last 32bits reserved */ +#endif }; /* @@ -234,17 +147,15 @@ struct dma_descriptor { /* 8 32-bit valu * The virtual address will determine what should be freed. */ struct dma_desc_mem { - struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma - descriptor. should be first element */ - dma_addr_t phy_addr; /* physical address - of each DMA desc */ + struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ + dma_addr_t phy_addr; /* physical address of each DMA desc */ uint32_t sz; - struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ + struct dma_desc_mem *Next; /* points to Next Descriptor in chain */ }; enum list_sts { - sts_free = 0, + sts_free = 0, /* RX-Y Bits 0:7 */ rx_waiting_y_intr = 0x00000001, @@ -259,27 +170,84 @@ enum list_sts { rx_y_mask = 0x000000FF, rx_uv_mask = 0x0000FF00, + +}; + + +enum INTERRUPT_STATUS { + NO_INTERRUPT = 0x0000, + FPGA_RX_L0_DMA_DONE = 0x0001, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + FPGA_RX_L1_DMA_DONE = 0x0002, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + FPGA_TX_L0_DMA_DONE = 0x0004, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + FPGA_TX_L1_DMA_DONE = 0x0008, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + DECO_PIB_INTR = 0x0010, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + DECO_FMT_CHANGE = 0x0020, + DECO_MBOX_RESP = 0x0040, + DECO_RESUME_FRM_INTER_PAUSE = 0x0080, /*Not Handled in DPC Need to Fire Rx cmds on resume from Pause*/ +}; + +enum ERROR_STATUS { + NO_ERROR =0, + RX_Y_DMA_ERR_L0 =0x0001,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + RX_UV_DMA_ERR_L0 =0x0002,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + RX_Y_DMA_ERR_L1 =0x0004,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + RX_UV_DMA_ERR_L1 =0x0008,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + TX_DMA_ERR_L0 =0x0010,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + TX_DMA_ERR_L1 =0x0020,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ + FW_CMD_ERROR =0x0040, + DROP_REPEATED =0x0080, + DROP_FLEA_FMTCH =0x0100,/*We do not want to deliver the flea dummy frame*/ + DROP_DATA_ERROR =0x0200,/*We were not able to get the PIB correctly so drop the frame. */ + DROP_SIZE_ERROR =0x0400,/*We were not able to get the size properly from hardware. */ + FORCE_CANCEL =0x8000 +}; + +enum LIST_STATUS { + ListStsFree=0, /* Initial state and state the buffer is moved to Ready Buffer list. */ + RxListWaitingForYIntr=1, /* When the Y Descriptor is posted. */ + RxListWaitingForUVIntr=2, /* When the UV descriptor is posted. */ + TxListWaitingForIntr =4, +}; + +struct RX_DMA_LIST { + enum LIST_STATUS ListSts; + /*LIST_ENTRY ActiveList; */ + uint32_t ActiveListLen; + uint32_t ListLockInd; /* To Be Filled up During Init */ + uint32_t ulDiscCount; /* Discontinuity On this list */ + uint32_t RxYFirstDescLADDRReg; /* First Desc Low Addr Y */ + uint32_t RxYFirstDescUADDRReg; /* First Desc UPPER Addr Y */ + uint32_t RxYCurDescLADDRReg; /* Current Desc Low Addr Y */ + uint32_t RxYCurDescUADDRReg; /* First Desc Low Addr Y */ + uint32_t RxYCurByteCntRemReg; /* Cur Byte Cnt Rem Y */ + + uint32_t RxUVFirstDescLADDRReg; /* First Desc Low Addr UV */ + uint32_t RxUVFirstDescUADDRReg; /* First Desc UPPER Addr UV */ + uint32_t RxUVCurDescLADDRReg; /* Current Desc Low Addr UV */ + uint32_t RxUVCurDescUADDRReg; /* Current Desc UPPER Addr UV */ + uint32_t RxUVCurByteCntRemReg; /* Cur Byte Cnt Rem UV */ }; struct tx_dma_pkt { - struct dma_desc_mem desc_mem; + struct dma_desc_mem desc_mem; hw_comp_callback call_back; struct crystalhd_dio_req *dio_req; wait_queue_head_t *cb_event; uint32_t list_tag; + }; struct crystalhd_rx_dma_pkt { - struct dma_desc_mem desc_mem; - struct crystalhd_dio_req *dio_req; + struct dma_desc_mem desc_mem; + struct crystalhd_dio_req *dio_req; uint32_t pkt_tag; uint32_t flags; - struct BC_PIC_INFO_BLOCK pib; + BC_PIC_INFO_BLOCK pib; dma_addr_t uv_phy_addr; - struct crystalhd_rx_dma_pkt *next; + struct crystalhd_rx_dma_pkt *next; }; -struct crystalhd_hw_stats { +struct crystalhd_hw_stats{ uint32_t rx_errors; uint32_t tx_errors; uint32_t freeq_count; @@ -288,29 +256,106 @@ struct crystalhd_hw_stats { uint32_t dev_interrupts; uint32_t cin_busy; uint32_t pause_cnt; + uint32_t rx_success; }; +enum DECO_STATE { + DECO_OPERATIONAL = 0, /* We start with this state.ST_FW_DWNLD,ST_CAPTURE,STOP_CAPTURE */ + DECO_INTER_PAUSED = 1, /* Driver Issued Pause To Decoder */ + DECO_INTER_PAUSE_IN_PROGRESS = 2, /* Pause CMD is pending with F/W */ + DECO_INTER_RESUME_IN_PROGRESS = 3, /* Resume CMD is pending with F/W */ + DECO_STOPPED_BY_APP = 4 /* After STOP Video I do not want to Throttle Decoder.So Special State */ +}; + +/* */ +/* These events can be used to notify the hardware layer */ +/* to set up it adapter in proper state...or for anyother */ +/* purpose for that matter. */ +/* We will use this for intermediae events as defined below */ + +enum BRCM_EVENT { + BC_EVENT_ADAPTER_INIT_FAILED =0, + BC_EVENT_ADAPTER_INIT_SUCCESS =1, + BC_EVENT_FW_DNLD_STARTED =2, + BC_EVENT_FW_DNLD_ERR =3, + BC_EVENT_FW_DNLD_DONE =4, + BC_EVENT_SYS_SHUT_DOWN =5, + BC_EVENT_START_CAPTURE =6, + BC_EVENT_START_CAPTURE_IMMI =7, + BC_EVENT_STOP_CAPTURE =8, /* Stop Capturing the Rx buffers Stop the DMA engines UnMapBuffers Discard Free and Ready list */ + BC_EVENT_DO_CLEANUP =9, /* Total Cleanup Rx And Tx side */ + BC_DISCARD_RX_BUFFERS =10 /* Move all the Ready buffers to free list. Stop RX DMA. Post Rx Side buffers. */ +}; + +struct crystalhd_hw; /* forward declaration for the types */ + +/*typedef void* (*HW_VERIFY_DEVICE)(struct crystalhd_adp*); */ +/*typedef bool (*HW_INIT_DEVICE_RESOURCES)(struct crystalhd_adp*); */ +/*typedef bool (*HW_CLEAN_DEVICE_RESOURCES)(struct crystalhd_adp*); */ +typedef bool (*HW_START_DEVICE)(struct crystalhd_hw*); +typedef bool (*HW_STOP_DEVICE)(struct crystalhd_hw*); +/* typedef bool (*HW_XLAT_AND_FIRE_SGL)(struct crystalhd_adp*,PVOID,PSCATTER_GATHER_LIST,uint32_t); */ +/* typedef bool (*HW_RX_XLAT_SGL)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ +typedef bool (*HW_FIND_AND_CLEAR_INTR)(struct crystalhd_adp*,struct crystalhd_hw*); +typedef uint32_t (*HW_READ_DEVICE_REG)(struct crystalhd_adp*,uint32_t); +typedef void (*HW_WRITE_DEVICE_REG)(struct crystalhd_adp*,uint32_t,uint32_t); +typedef uint32_t (*HW_READ_FPGA_REG)(struct crystalhd_adp*,uint32_t); +typedef void (*HW_WRITE_FPGA_REG)(struct crystalhd_adp*,uint32_t,uint32_t); +typedef BC_STATUS (*HW_READ_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); +typedef BC_STATUS (*HW_WRITE_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); +/* typedef bool (*HW_INIT_DRAM)(struct crystalhd_adp*); */ +/* typedef bool (*HW_DISABLE_INTR)(struct crystalhd_adp*); */ +/* typedef bool (*HW_ENABLE_INTR)(struct crystalhd_adp*); */ +typedef BC_STATUS (*HW_POST_RX_SIDE_BUFF)(struct crystalhd_hw*,struct crystalhd_rx_dma_pkt*); +typedef bool (*HW_CHECK_INPUT_FIFO)(struct crystalhd_hw*, uint32_t, uint32_t*,bool,uint8_t*); +typedef void (*HW_START_TX_DMA)(struct crystalhd_hw*, uint8_t, addr_64); +typedef BC_STATUS (*HW_STOP_TX_DMA)(struct crystalhd_hw*); +/* typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_adp*,BRCM_EVENT); */ +/* typedef bool (*HW_RX_POST_INTR_PROCESSING)(struct crystalhd_adp*,uint32_t,uint32_t); */ +typedef void (*HW_GET_DONE_SIZE)(struct crystalhd_hw *hw, uint32_t, uint32_t*, uint32_t*); +/* typedef bool (*HW_ADD_DRP_TO_FREE_LIST)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ +typedef struct crystalhd_dio_req* (*HW_FETCH_DONE_BUFFERS)(struct crystalhd_adp*,bool); +/* typedef bool (*HW_ADD_ROLLBACK_RXBUF)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ +typedef bool (*HW_PEEK_NEXT_DECODED_RXBUF)(struct crystalhd_hw*,uint64_t*,uint32_t*,uint32_t); +typedef BC_STATUS (*HW_FW_PASSTHRU_CMD)(struct crystalhd_hw*,PBC_FW_CMD); +/* typedef bool (*HW_CANCEL_FW_CMDS)(struct crystalhd_adp*,OS_CANCEL_CALLBACK); */ +/* typedef void* (*HW_GET_FW_DONE_OS_CMD)(struct crystalhd_adp*); */ +/* typedef PBC_DRV_PIC_INFO (*SEARCH_FOR_PIB)(struct crystalhd_adp*,bool,uint32_t); */ +/* typedef bool (*HW_DO_DRAM_PWR_MGMT)(struct crystalhd_adp*); */ +typedef BC_STATUS (*HW_FW_DOWNLOAD)(struct crystalhd_hw*,uint8_t*,uint32_t); +typedef BC_STATUS (*HW_ISSUE_DECO_PAUSE)(struct crystalhd_hw*, bool); +typedef void (*HW_STOP_DMA_ENGINES)(struct crystalhd_hw*); +/* +typedef BOOLEAN (*FIRE_RX_REQ_TO_HW) (PHW_EXTENSION,PRX_DMA_LIST); +typedef BOOLEAN (*PIC_POST_PROC) (PHW_EXTENSION,PRX_DMA_LIST,PULONG); +typedef BOOLEAN (*HW_ISSUE_DECO_PAUSE) (PHW_EXTENSION,BOOLEAN,BOOLEAN); +typedef BOOLEAN (*FIRE_TX_CMD_TO_HW) (PCONTEXT_FOR_POST_TX); +*/ +typedef void (*NOTIFY_FLL_CHANGE)(struct crystalhd_hw*,bool); +typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_hw*, enum BRCM_EVENT); + struct crystalhd_hw { - struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; + struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; spinlock_t lock; uint32_t tx_ioq_tag_seed; uint32_t tx_list_post_index; - struct crystalhd_rx_dma_pkt *rx_pkt_pool_head; + struct crystalhd_rx_dma_pkt *rx_pkt_pool_head; uint32_t rx_pkt_tag_seed; bool dev_started; - void *adp; + struct crystalhd_adp *adp; wait_queue_head_t *pfw_cmd_event; int fwcmd_evt_sts; uint32_t pib_del_Q_addr; uint32_t pib_rel_Q_addr; + uint32_t channelNum; - struct crystalhd_dioq *tx_freeq; - struct crystalhd_dioq *tx_actq; + struct crystalhd_dioq *tx_freeq; + struct crystalhd_dioq *tx_actq; /* Rx DMA Engine Specific Locks */ spinlock_t rx_lock; @@ -321,87 +366,187 @@ struct crystalhd_hw { struct crystalhd_dioq *rx_actq; uint32_t stop_pending; + uint32_t hw_pause_issued; + + uint32_t fwcmdPostAddr; + uint32_t fwcmdPostMbox; + uint32_t fwcmdRespMbox; + /* HW counters.. */ struct crystalhd_hw_stats stats; - /* Core clock in MHz */ - uint32_t core_clock_mhz; - uint32_t prev_n; - uint32_t pwr_lock; -}; - -/* Clock defines for power control */ -#define CLOCK_PRESET 175 - -/* DMA engine register BIT mask wrappers.. */ -#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK - -#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) - -#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) - -#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) - - -/**** API Exposed to the other layers ****/ -enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, - void *buffer, uint32_t sz); -enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, - struct BC_FW_CMD *fw_cmd); -bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, - struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, - struct crystalhd_adp *); -enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *); -enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *); -enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *); - - -enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, - hw_comp_callback call_back, - wait_queue_head_t *cb_event, - uint32_t *list_id, uint8_t data_flags); - -enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, - uint32_t list_id); -enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, bool en_post); -enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, - struct BC_PIC_INFO_BLOCK *pib, - struct crystalhd_dio_req **ioreq); -enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); -void crystalhd_hw_stats(struct crystalhd_hw *hw, - struct crystalhd_hw_stats *stats); + /* Picture Information Block Management Variables */ + uint32_t PICWidth; /* Pic Width Recieved On Format Change for link/With WidthField On Flea*/ + uint32_t PICHeight; /* Pic Height Recieved on format change[Link and Flea]/Not Used in Flea*/ + uint32_t LastPicNo; /* For Repeated Frame Detection */ + uint32_t LastTwoPicNo; /* For Repeated Frame Detection on Interlace clip*/ + uint32_t LastSessNum; /* For Session Change Detection */ + + struct semaphore fetch_sem; /* semaphore between fetch and probe of the next picture information, since both will be in process context */ + + uint32_t RxCaptureState; /* 0 if capture is not enabled, 1 if capture is enabled, 2 if stop rxdma is pending */ + + /* BCM70015 mods */ + uint32_t PicQSts; /* This is the bitmap given by PiCQSts Interrupt*/ + uint32_t TxBuffInfoAddr; /* Address of the TX Fifo in DRAM*/ + uint32_t FleaRxPicDelAddr; /* Memory address where the pictures are fired*/ + uint32_t FleaFLLUpdateAddr; /* Memory Address where FLL is updated*/ + uint32_t FleaBmpIntrCnt; + uint32_t RxSeqNum; + uint32_t DrvEosDetected; + uint32_t DrvCancelEosFlag; + + uint32_t SkipDropBadFrames; + uint32_t TemperatureRegVal; + TX_INPUT_BUFFER_INFO TxFwInputBuffInfo; + + enum DECO_STATE DecoderSt; /* Weather the decoder is paused or not*/ + uint32_t PauseThreshold; + uint32_t ResumeThreshold; + + uint32_t RxListPointer; /* Treat the Rx List As Circular List */ + enum LIST_STATUS TxList0Sts; + enum LIST_STATUS TxList1Sts; + + uint32_t FleaEnablePWM; + uint32_t FleaWaitFirstPlaybackNotify; + enum FLEA_POWER_STATES FleaPowerState; + uint32_t EmptyCnt; + bool SingleThreadAppFIFOEmpty; + bool PwrDwnTxIntr; /* Got an TX FIFO status interrupt when in power down state */ + bool PwrDwnPiQIntr; /* Got a Picture Q interrupt when in power down state */ + uint32_t OLWatchDogTimer; + uint32_t ILWatchDogTimer; + uint32_t FwCmdCnt; + bool WakeUpDecodeDone; /* Used to indicate that the HW is awake to RX is running so we can actively manage power */ + + uint64_t TickCntDecodePU; /* Time when we first powered up to decode */ + uint64_t TickSpentInPD; /* Total amount of time spent in PD */ + uint64_t TickStartInPD; /* Tick count when we start in PD */ + uint32_t PDRatio; /* % of time spent in power down. Goal is to keep this close to 50 */ + uint32_t DefaultPauseThreshold; /* default threshold to set when we start power management */ + +/* uint32_t FreeListLen; */ +/* uint32_t ReadyListLen; */ + +/* */ +/* Counters needed for monitoring purposes. */ +/* These counters are per session and will be reset to zero in */ +/* start capture. */ +/* */ + uint32_t DrvPauseCnt; /* Number of Times the driver has issued pause.*/ +#if 0 + uint32_t DrvServiceIntrCnt; /* Number of interrutps the driver serviced. */ + uint32_t DrvIgnIntrCnt; /* Number of Interrupts Driver Ignored.NOT OUR INTR. */ + uint32_t DrvTotalFrmDropped; /* Number of frames dropped by the driver.*/ +#endif + uint32_t DrvTotalFrmCaptured; /* Numner of Good Frames Captured*/ +#if 0 + uint32_t DrvTotalHWErrs; /* Total HW Errors.*/ + uint32_t DrvTotalPIBFlushCnt; /* Number of Times the driver flushed PIB Queues.*/ + uint32_t DrvMissedPIBCnt; /* Number of Frames for which the PIB was not found.*/ + uint64_t TickCntOnPause; */ + uint32_t TotalTimeInPause; /* In Milliseconds */ + uint32_t RepeatedFramesCnt; */ +#endif -/* API to program the core clock on the decoder */ -enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *); +/* HW_VERIFY_DEVICE pfnVerifyDevice; */ +/* HW_INIT_DEVICE_RESOURCES pfnInitDevResources; */ +/* HW_CLEAN_DEVICE_RESOURCES pfnCleanDevResources; */ + HW_START_DEVICE pfnStartDevice; + HW_STOP_DEVICE pfnStopDevice; +/* HW_XLAT_AND_FIRE_SGL pfnTxXlatAndFireSGL; */ +/* HW_RX_XLAT_SGL pfnRxXlatSgl; */ + HW_FIND_AND_CLEAR_INTR pfnFindAndClearIntr; + HW_READ_DEVICE_REG pfnReadDevRegister; + HW_WRITE_DEVICE_REG pfnWriteDevRegister; + HW_READ_FPGA_REG pfnReadFPGARegister; + HW_WRITE_FPGA_REG pfnWriteFPGARegister; + HW_READ_DEV_MEM pfnDevDRAMRead; + HW_WRITE_DEV_MEM pfnDevDRAMWrite; +/* HW_INIT_DRAM pfnInitDRAM; */ +/* HW_DISABLE_INTR pfnDisableIntr; */ +/* HW_ENABLE_INTR pfnEnableIntr; */ + HW_POST_RX_SIDE_BUFF pfnPostRxSideBuff; + HW_CHECK_INPUT_FIFO pfnCheckInputFIFO; + HW_START_TX_DMA pfnStartTxDMA; + HW_STOP_TX_DMA pfnStopTxDMA; + HW_GET_DONE_SIZE pfnHWGetDoneSize; +/* HW_EVENT_NOTIFICATION pfnNotifyHardware; */ +/* HW_ADD_DRP_TO_FREE_LIST pfnAddRxDRPToFreeList; */ +/* HW_FETCH_DONE_BUFFERS pfnFetchReadyRxDRP; */ +/* HW_ADD_ROLLBACK_RXBUF pfnRollBackRxBuf; */ + HW_PEEK_NEXT_DECODED_RXBUF pfnPeekNextDeodedFr; + HW_FW_PASSTHRU_CMD pfnDoFirmwareCmd; +/* HW_GET_FW_DONE_OS_CMD pfnGetFWDoneCmdOsCntxt; */ +/* HW_CANCEL_FW_CMDS pfnCancelFWCmds; */ +/* SEARCH_FOR_PIB pfnSearchPIB; */ +/* HW_DO_DRAM_PWR_MGMT pfnDRAMPwrMgmt; */ + HW_FW_DOWNLOAD pfnFWDwnld; + HW_ISSUE_DECO_PAUSE pfnIssuePause; + HW_STOP_DMA_ENGINES pfnStopRXDMAEngines; +/* FIRE_RX_REQ_TO_HW pfnFireRx; */ +/* PIC_POST_PROC pfnPostProcessPicture; */ +/* FIRE_TX_CMD_TO_HW pfnFireTx; */ + NOTIFY_FLL_CHANGE pfnNotifyFLLChange; + HW_EVENT_NOTIFICATION pfnNotifyHardware; +}; + +struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw); +void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *pkt); +void crystalhd_tx_desc_rel_call_back(void *context, void *data); +void crystalhd_rx_pkt_rel_call_back(void *context, void *data); +void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp); +BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp); +BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, uint32_t list_id, BC_STATUS cs); +BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, + struct dma_descriptor *desc, + dma_addr_t desc_paddr_base, + uint32_t sg_cnt, uint32_t sg_st_ix, + uint32_t sg_st_off, uint32_t xfr_sz, + struct device *dev, uint32_t destDRAMaddr); +BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq, + struct dma_desc_mem * pdesc_mem, + uint32_t *uv_desc_index, + struct device *dev, uint32_t destDRAMaddr); +BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, + uint32_t list_index, + BC_STATUS comp_sts); +BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, + hw_comp_callback call_back, + wait_queue_head_t *cb_event, uint32_t *list_id, + uint8_t data_flags); +BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); +BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,struct crystalhd_dio_req *ioreq, bool en_post); +BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,struct C011_PIB *pib,struct crystalhd_dio_req **ioreq); +BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap); +BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_resume(struct crystalhd_hw *hw); +void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); + +#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) + +#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) #endif --- crystalhd~/crystalhd_linkfuncs.c 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_linkfuncs.c 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,2058 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_hw . c + * + * Description: + * BCM70010 Linux driver HW layer. + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include +#include +#include +#include +#include "crystalhd_hw.h" +#include "crystalhd_lnx.h" +#include "crystalhd_linkfuncs.h" + +#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) + +/** +* link_dec_reg_rd - Read 70010's device register. +* @adp: Adapter instance +* @reg_off: Register offset. +* +* Return: +* 32bit value read +* +* 70010's device register read routine. This interface use +* 70010's device access range mapped from BAR-2 (4M) of PCIe +* configuration space. +*/ +uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) +{ + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return 0; + } + + if (reg_off > adp->pci_mem_len) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return 0; + } + + return readl(adp->mem_addr + reg_off); +} + +/** +* link_dec_reg_wr - Write 70010's device register +* @adp: Adapter instance +* @reg_off: Register offset. +* @val: Dword value to be written. +* +* Return: +* none. +* +* 70010's device register write routine. This interface use +* 70010's device access range mapped from BAR-2 (4M) of PCIe +* configuration space. +*/ +void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +{ + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return; + } + + if (reg_off > adp->pci_mem_len) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return; + } + + writel(val, adp->mem_addr + reg_off); + + /* the udelay is required for latest 70012, not for others... :( */ + udelay(8); +} + +/** +* crystalhd_reg_rd - Read 70012's device register. +* @adp: Adapter instance +* @reg_off: Register offset. +* +* Return: +* 32bit value read +* +* 70012 device register read routine. This interface use +* 70012's device access range mapped from BAR-1 (64K) of PCIe +* configuration space. +* +*/ +uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) +{ + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return 0; + } + + if (reg_off > adp->pci_i2o_len) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return 0; + } + + return readl(adp->i2o_addr + reg_off); +} + +/** +* crystalhd_reg_wr - Write 70012's device register +* @adp: Adapter instance +* @reg_off: Register offset. +* @val: Dword value to be written. +* +* Return: +* none. +* +* 70012 device register write routine. This interface use +* 70012's device access range mapped from BAR-1 (64K) of PCIe +* configuration space. +* +*/ +void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +{ + if (!adp) { + printk(KERN_ERR "%s: Invalid args\n", __func__); + return; + } + + if (reg_off > adp->pci_i2o_len) { + dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", + __func__, reg_off); + return; + } + + writel(val, adp->i2o_addr + reg_off); +} + +inline uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off) +{ + hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); + return hw->pfnReadDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF))); +} + +inline void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val) +{ + hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); + hw->pfnWriteDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); +} + +/** +* crystalhd_link_mem_rd - Read data from DRAM area. +* @adp: Adapter instance +* @start_off: Start offset. +* @dw_cnt: Count in dwords. +* @rd_buff: Buffer to copy the data from dram. +* +* Return: +* Status. +* +* Dram read routine. +*/ +BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, + uint32_t dw_cnt, uint32_t *rd_buff) +{ + uint32_t ix = 0; + + if (!hw || !rd_buff) { + printk(KERN_ERR "%s: Invalid arg\n", __func__); + return BC_STS_INV_ARG; + } + for (ix = 0; ix < dw_cnt; ix++) + rd_buff[ix] = crystalhd_link_dram_rd(hw, (start_off + (ix * 4))); + + return BC_STS_SUCCESS; +} + +/** +* crystalhd_link_mem_wr - Write data to DRAM area. +* @adp: Adapter instance +* @start_off: Start offset. +* @dw_cnt: Count in dwords. +* @wr_buff: Data Buffer to be written. +* +* Return: +* Status. +* +* Dram write routine. +*/ +BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, + uint32_t dw_cnt, uint32_t *wr_buff) +{ + uint32_t ix = 0; + + if (!hw || !wr_buff) { + printk(KERN_ERR "%s: Invalid arg\n", __func__); + return BC_STS_INV_ARG; + } + + for (ix = 0; ix < dw_cnt; ix++) + crystalhd_link_dram_wr(hw, (start_off + (ix * 4)), wr_buff[ix]); + + return BC_STS_SUCCESS; +} + +void crystalhd_link_enable_uarts(struct crystalhd_hw *hw) +{ + hw->pfnWriteDevRegister(hw->adp, UartSelectA, BSVS_UART_STREAM); + hw->pfnWriteDevRegister(hw->adp, UartSelectB, BSVS_UART_DEC_OUTER); +} + +void crystalhd_link_start_dram(struct crystalhd_hw *hw) +{ + hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) | +#if 0 + tras (40ns tras)/(5ns period) -1 ((15/5 - 1) << 4) | /* trcd */ +#endif + ((15 / 5 - 1) << 7) | /* trp */ + ((10 / 5 - 1) << 10) | /* trrd */ + ((15 / 5 + 1) << 12) | /* twr */ + ((2 + 1) << 16) | /* twtr */ + ((70 / 5 - 2) << 19) | /* trfc */ + (0 << 23)); + + hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); + hw->pfnWriteDevRegister(hw->adp, SDRAM_EXT_MODE, 2); + hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x132); + hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); + hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); + hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); + hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x32); + /* setting the refresh rate here */ + hw->pfnWriteDevRegister(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | 96)); +} + + +bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw) +{ + union link_misc_perst_deco_ctrl rst_deco_cntrl; + union link_misc_perst_clk_ctrl rst_clk_cntrl; + uint32_t temp; + + /* + * Link clocks: MISC_PERST_CLOCK_CTRL Clear PLL power down bit, + * delay to allow PLL to lock Clear alternate clock, stop clock bits + */ + rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.pll_pwr_dn = 0; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.stop_core_clk = 0; + rst_clk_cntrl.sel_alt_clk = 0; + + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + /* + * Bus Arbiter Timeout: GISB_ARBITER_TIMER + * Set internal bus arbiter timeout to 40us based on core clock speed + * (63MHz * 40us = 0x9D8) + */ + hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x9D8); + + /* + * Decoder clocks: MISC_PERST_DECODER_CTRL + * Enable clocks while 7412 reset is asserted, delay + * De-assert 7412 reset + */ + rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.stop_bcm_7412_clk = 0; + rst_deco_cntrl.bcm7412_rst = 1; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(50); + + rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.bcm7412_rst = 0; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(50); + + /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ + hw->pfnWriteFPGARegister(hw->adp, OTP_CONTENT_MISC, 0); + + /* Clear bit 29 of 0x404 */ + temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); + temp &= ~BC_BIT(29); + hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); + + /* 2.5V regulator must be set to 2.6 volts (+6%) */ + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_VREG_CTRL, 0xF3); + + return true; +} + +bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw) +{ + union link_misc_perst_deco_ctrl rst_deco_cntrl; + union link_misc_perst_clk_ctrl rst_clk_cntrl; + uint32_t temp; + + /* + * Decoder clocks: MISC_PERST_DECODER_CTRL + * Assert 7412 reset, delay + * Assert 7412 stop clock + */ + rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.stop_bcm_7412_clk = 1; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(50); + + /* Bus Arbiter Timeout: GISB_ARBITER_TIMER + * Set internal bus arbiter timeout to 40us based on core clock speed + * (6.75MHZ * 40us = 0x10E) + */ + hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x10E); + + /* Link clocks: MISC_PERST_CLOCK_CTRL + * Stop core clk, delay + * Set alternate clk, delay, set PLL power down + */ + rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.stop_core_clk = 1; + rst_clk_cntrl.sel_alt_clk = 1; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.pll_pwr_dn = 1; + hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + + /* + * Read and restore the Transaction Configuration Register + * after core reset + */ + temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); + + /* + * Link core soft reset: MISC3_RESET_CTRL + * - Write BIT[0]=1 and read it back for core reset to take place + */ + hw->pfnWriteFPGARegister(hw->adp, MISC3_RESET_CTRL, 1); + rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC3_RESET_CTRL); + msleep_interruptible(50); + + /* restore the transaction configuration register */ + hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); + + return true; +} + +void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw) +{ + union intr_mask_reg intr_mask; + intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); + intr_mask.mask_pcie_err = 1; + intr_mask.mask_pcie_rbusmast_err = 1; + intr_mask.mask_pcie_rgr_bridge = 1; + intr_mask.mask_rx_done = 1; + intr_mask.mask_rx_err = 1; + intr_mask.mask_tx_done = 1; + intr_mask.mask_tx_err = 1; + hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg); + + return; +} + +void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw) +{ + union intr_mask_reg intr_mask; + intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); + intr_mask.mask_pcie_err = 1; + intr_mask.mask_pcie_rbusmast_err = 1; + intr_mask.mask_pcie_rgr_bridge = 1; + intr_mask.mask_rx_done = 1; + intr_mask.mask_rx_err = 1; + intr_mask.mask_tx_done = 1; + intr_mask.mask_tx_err = 1; + hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg); + + return; +} + +void crystalhd_link_clear_errors(struct crystalhd_hw *hw) +{ + uint32_t reg; + + /* Writing a 1 to a set bit clears that bit */ + reg = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); + if (reg) + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, reg); + + reg = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); + if (reg) + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, reg); + + reg = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); + if (reg) + hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, reg); +} + +void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw) +{ + uint32_t intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); + + if (intr_sts) { + hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); + + /* Write End Of Interrupt for PCIE */ + hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); + } +} + +void crystalhd_link_soft_rst(struct crystalhd_hw *hw) +{ + uint32_t val; + + /* Assert c011 soft reset*/ + hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000001); + msleep_interruptible(50); + + /* Release c011 soft reset*/ + hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000000); + + /* Disable Stuffing..*/ + val = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); + val |= BC_BIT(8); + hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, val); +} + +bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw) +{ + uint32_t i = 0, reg; + + hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); + + hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0); + hw->pfnWriteFPGARegister(hw->adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); + hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0x1); + + for (i = 0; i < 100; ++i) { + reg = hw->pfnReadFPGARegister(hw->adp, AES_STATUS); + if (reg & 0x1) + return true; + msleep_interruptible(10); + } + + return false; +} + + +bool crystalhd_link_start_device(struct crystalhd_hw *hw) +{ + uint32_t dbg_options, glb_cntrl = 0, reg_pwrmgmt = 0; + struct device *dev; + + if (!hw) + return -EINVAL; + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "Starting Crystal HD BCM70012 Device\n"); + + if (!crystalhd_link_bring_out_of_rst(hw)) { + dev_err(dev, "Failed To Bring BCM70012 Out Of Reset\n"); + return false; + } + + crystalhd_link_disable_interrupts(hw); + + crystalhd_link_clear_errors(hw); + + crystalhd_link_clear_interrupts(hw); + + crystalhd_link_enable_interrupts(hw); + + /* Enable the option for getting the total no. of DWORDS + * that have been transfered by the RXDMA engine + */ + dbg_options = hw->pfnReadFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG); + dbg_options |= 0x10; + hw->pfnWriteFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options); + + /* Enable PCI Global Control options */ + glb_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); + glb_cntrl |= 0x100; + glb_cntrl |= 0x8000; + hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, glb_cntrl); + + crystalhd_link_enable_interrupts(hw); + + crystalhd_link_soft_rst(hw); + crystalhd_link_start_dram(hw); + crystalhd_link_enable_uarts(hw); + + /* Disable L1 ASPM while video is playing as this causes performance problems otherwise */ + reg_pwrmgmt = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); + reg_pwrmgmt &= ~ASPM_L1_ENABLE; + + hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt); + + return true; +} + +bool crystalhd_link_stop_device(struct crystalhd_hw *hw) +{ + uint32_t reg; + BC_STATUS sts; + + dev_dbg(&hw->adp->pdev->dev, "Stopping Crystal HD BCM70012 Device\n"); + sts = crystalhd_link_put_ddr2sleep(hw); + if (sts != BC_STS_SUCCESS) { + dev_err(&hw->adp->pdev->dev, "Failed to Put DDR To Sleep!!\n"); + return BC_STS_ERROR; + } + + /* Clear and disable interrupts */ + crystalhd_link_disable_interrupts(hw); + crystalhd_link_clear_errors(hw); + crystalhd_link_clear_interrupts(hw); + + if (!crystalhd_link_put_in_reset(hw)) + dev_err(&hw->adp->pdev->dev, "Failed to Put Link To Reset State\n"); + + reg = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); + reg |= ASPM_L1_ENABLE; + hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg); + + /* Set PCI Clk Req */ + reg = hw->pfnReadFPGARegister(hw->adp, PCIE_CLK_REQ_REG); + reg |= PCI_CLK_REQ_ENABLE; + hw->pfnWriteFPGARegister(hw->adp, PCIE_CLK_REQ_REG, reg); + + return true; +} + +uint32_t link_GetPicInfoLineNum(struct crystalhd_dio_req *dio, uint8_t *base) +{ + uint32_t PicInfoLineNum = 0; + + if (dio->uinfo.b422mode == MODE422_YUY2) { + PicInfoLineNum = ((uint32_t)(*(base + 6)) & 0xff) + | (((uint32_t)(*(base + 4)) << 8) & 0x0000ff00) + | (((uint32_t)(*(base + 2)) << 16) & 0x00ff0000) + | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); + } else if (dio->uinfo.b422mode == MODE422_UYVY) { + PicInfoLineNum = ((uint32_t)(*(base + 7)) & 0xff) + | (((uint32_t)(*(base + 5)) << 8) & 0x0000ff00) + | (((uint32_t)(*(base + 3)) << 16) & 0x00ff0000) + | (((uint32_t)(*(base + 1)) << 24) & 0xff000000); + } else { + PicInfoLineNum = ((uint32_t)(*(base + 3)) & 0xff) + | (((uint32_t)(*(base + 2)) << 8) & 0x0000ff00) + | (((uint32_t)(*(base + 1)) << 16) & 0x00ff0000) + | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); + } + + return PicInfoLineNum; +} + +uint32_t link_GetMode422Data(struct crystalhd_dio_req *dio, + PBC_PIC_INFO_BLOCK pPicInfoLine, int type) +{ + int i; + uint32_t offset = 0, val = 0; + uint8_t *tmp; + tmp = (uint8_t *)&val; + + if (type == 1) + offset = OFFSETOF(BC_PIC_INFO_BLOCK, picture_meta_payload); + else if (type == 2) + offset = OFFSETOF(BC_PIC_INFO_BLOCK, height); + else + offset = 0; + + if (dio->uinfo.b422mode == MODE422_YUY2) { + for (i = 0; i < 4; i++) + ((uint8_t*)tmp)[i] = + ((uint8_t*)pPicInfoLine)[(offset + i) * 2]; + } else if (dio->uinfo.b422mode == MODE422_UYVY) { + for (i = 0; i < 4; i++) + ((uint8_t*)tmp)[i] = + ((uint8_t*)pPicInfoLine)[(offset + i) * 2 + 1]; + } + + return val; +} + +uint32_t link_GetMetaDataFromPib(struct crystalhd_dio_req *dio, + PBC_PIC_INFO_BLOCK pPicInfoLine) +{ + uint32_t picture_meta_payload = 0; + + if (dio->uinfo.b422mode) + picture_meta_payload = link_GetMode422Data(dio, pPicInfoLine, 1); + else + picture_meta_payload = pPicInfoLine->picture_meta_payload; + + return BC_SWAP32(picture_meta_payload); +} + +uint32_t link_GetHeightFromPib(struct crystalhd_dio_req *dio, + PBC_PIC_INFO_BLOCK pPicInfoLine) +{ + uint32_t height = 0; + + if (dio->uinfo.b422mode) + height = link_GetMode422Data(dio, pPicInfoLine, 2); + else + height = pPicInfoLine->height; + + return BC_SWAP32(height); +} + +/* This function cannot be called from ISR context since it uses APIs that can sleep */ +bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, struct crystalhd_dio_req *dio, + uint32_t *PicNumber, uint64_t *PicMetaData) +{ + uint32_t PicInfoLineNum = 0, HeightInPib = 0, offset = 0, size = 0; + PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; + uint32_t pic_number = 0; + uint8_t *tmp = (uint8_t *)&pic_number; + int i; + unsigned long res = 0; + + dev_dbg(&hw->adp->pdev->dev, "getting Picture Info\n"); + + *PicNumber = 0; + *PicMetaData = 0; + + if (!dio || !picWidth) + goto getpictureinfo_err_nosem; + +/* if(down_interruptible(&hw->fetch_sem)) */ +/* goto getpictureinfo_err_nosem; */ + + dio->pib_va = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); /* since copy_from_user can sleep anyway */ + if(dio->pib_va == NULL) + goto getpictureinfo_err; + + res = copy_from_user(dio->pib_va, (void *)dio->uinfo.xfr_buff, 8); + if (res != 0) + goto getpictureinfo_err; + + /* + * -- Ajitabh[01-16-2009]: Strictly check against done size. + * -- we have seen that the done size sometimes comes less without + * -- any error indicated to the driver. So we change the limit + * -- to check against the done size rather than the full buffer size + * -- this way we will always make sure that the PIB is recieved by + * -- the driver. + */ + /* Limit = Base + pRxDMAReq->RxYDMADesc.RxBuffSz; */ + /* Limit = Base + (pRxDMAReq->RxYDoneSzInDword * 4); */ +/* Limit = dio->uinfo.xfr_buff + dio->uinfo.xfr_len; */ + + PicInfoLineNum = link_GetPicInfoLineNum(dio, dio->pib_va); + if (PicInfoLineNum > 1092) { + dev_dbg(&hw->adp->pdev->dev, "Invalid Line Number[%x]\n", (int)PicInfoLineNum); + goto getpictureinfo_err; + } + + /* + * -- Ajitabh[01-16-2009]: Added the check for validating the + * -- PicInfoLine Number. This function is only called for link so we + * -- do not have to check for height+1 or (Height+1)/2 as we are doing + * -- in DIL. In DIL we need that because for flea firmware is padding + * -- the data to make it 16 byte aligned. This Validates the reception + * -- of PIB itself. + */ + if (picHeight) { + if ((PicInfoLineNum != picHeight) && + (PicInfoLineNum != picHeight/2)) { + dev_dbg(&hw->adp->pdev->dev, "PicInfoLineNum[%d] != PICHeight " + "Or PICHeight/2 [%d]\n", + (int)PicInfoLineNum, picHeight); + goto getpictureinfo_err; + } + } + + /* calc pic info line offset */ + if (dio->uinfo.b422mode) { + size = 2 * sizeof(BC_PIC_INFO_BLOCK); + offset = (PicInfoLineNum * picWidth * 2) + 8; + } else { + size = sizeof(BC_PIC_INFO_BLOCK); + offset = (PicInfoLineNum * picWidth) + 4; + } + + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), size); + if (res != 0) + goto getpictureinfo_err; + pPicInfoLine = (PBC_PIC_INFO_BLOCK)(dio->pib_va); + +/* if (((uint8_t *)pPicInfoLine < Base) || */ +/* ((uint8_t *)pPicInfoLine > Limit)) { */ +/* dev_err(dev, "Base Limit Check Failed for Extracting " */ +/* "the PIB\n"); */ +/* goto getpictureinfo_err; */ +/* } */ + + /* + * -- Ajitabh[01-16-2009]: + * We have seen that the data gets shifted for some repeated frames. + * To detect those we use PicInfoLineNum and compare it with height. + */ + + HeightInPib = link_GetHeightFromPib(dio, pPicInfoLine); + if ((PicInfoLineNum != HeightInPib) && + (PicInfoLineNum != HeightInPib / 2)) { + printk("Height Match Failed: HeightInPIB[%d] " + "PicInfoLineNum[%d]\n", + (int)HeightInPib, (int)PicInfoLineNum); + goto getpictureinfo_err; + } + + /* get pic meta data from pib */ + *PicMetaData = link_GetMetaDataFromPib(dio, pPicInfoLine); + /* get pic number from pib */ + /* calc pic info line offset */ + if (dio->uinfo.b422mode) + offset = (PicInfoLineNum * picWidth * 2); + else + offset = (PicInfoLineNum * picWidth); + + res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 12); + if (res != 0) + goto getpictureinfo_err; + + if (dio->uinfo.b422mode == MODE422_YUY2) { + for (i = 0; i < 4; i++) + ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[i * 2]; + } else if (dio->uinfo.b422mode == MODE422_UYVY) { + for (i = 0; i < 4; i++) + ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[(i * 2) + 1]; + } else + pic_number = *(uint32_t *)(dio->pib_va); + + *PicNumber = BC_SWAP32(pic_number); + + if(dio->pib_va) + kfree(dio->pib_va); + +/* up(&hw->fetch_sem); */ + + return true; + +getpictureinfo_err: +/* up(&hw->fetch_sem); */ + +getpictureinfo_err_nosem: + if(dio->pib_va) + kfree(dio->pib_va); + *PicNumber = 0; + *PicMetaData = 0; + + return false; +} + +uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void* pRxDMAReq) +{ + uint32_t PicNumber = 0, result = 0; + uint64_t PicMetaData = 0; + + if(link_GetPictureInfo(hw, picHeight, picWidth, ((struct crystalhd_rx_dma_pkt *)pRxDMAReq)->dio_req, + &PicNumber, &PicMetaData)) + result = PicNumber; + + return result; +} + +/* +* This function gets the next picture metadata payload +* from the decoded picture in ReadyQ (if there was any) +* and returns it. THIS IS ONLY USED FOR LINK. +*/ +bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, + uint64_t *meta_payload, uint32_t *picNumFlags, + uint32_t PicWidth) +{ + uint32_t PicNumber = 0; + unsigned long flags = 0; + struct crystalhd_dioq *ioq; + struct crystalhd_elem *tmp; + struct crystalhd_rx_dma_pkt *rpkt; + + *meta_payload = 0; + + ioq = hw->rx_rdyq; + spin_lock_irqsave(&ioq->lock, flags); + + if ((ioq->count > 0) && (ioq->head != (struct crystalhd_elem *)&ioq->head)) { + tmp = ioq->head; + spin_unlock_irqrestore(&ioq->lock, flags); + rpkt = (struct crystalhd_rx_dma_pkt *)tmp->data; + if (rpkt) { + /* We are in process context here and have to check if we have repeated pictures */ + /* Drop repeated pictures or garbabge pictures here */ + /* This is because if we advertize a valid picture here, but later drop it */ + /* It will cause single threaded applications to hang, or errors in applications that expect */ + /* pictures not to be dropped once we have advertized their availability */ + + /* If format change packet, then return with out checking anything */ + if (!(rpkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE))) { + link_GetPictureInfo(hw, hw->PICHeight, hw->PICWidth, rpkt->dio_req, + &PicNumber, meta_payload); + if(!PicNumber || (PicNumber == hw->LastPicNo) || (PicNumber == hw->LastTwoPicNo)) { + /* discard picture */ + if(PicNumber != 0) { + hw->LastTwoPicNo = hw->LastPicNo; + hw->LastPicNo = PicNumber; + } + rpkt = crystalhd_dioq_fetch(hw->rx_rdyq); + if (rpkt) { + crystalhd_dioq_add(hw->rx_freeq, rpkt, false, rpkt->pkt_tag); + rpkt = NULL; + } + *meta_payload = 0; + } + return true; + /* Do not update the picture numbers here since they will be updated on the actual fetch of a valid picture */ + } + else + return false; /* don't use the meta_payload information */ + } + else + return false; + } + spin_unlock_irqrestore(&ioq->lock, flags); + + return false; +} + +bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, + uint32_t needed_sz, uint32_t *empty_sz, + bool b_188_byte_pkts, uint8_t *flags) +{ + uint32_t base, end, writep, readp; + uint32_t cpbSize, cpbFullness, fifoSize; + + if (*flags & 0x02) { /* ASF Bit is set */ + base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Base); + end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2End); + writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Wrptr); + readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Rdptr); + } else if (b_188_byte_pkts) { /*Encrypted 188 byte packets*/ + base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Base); + end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0End); + writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Wrptr); + readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Rdptr); + } else { + base = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinBase); + end = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinEnd); + writep = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinWrPtr); + readp = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinRdPtr); + } + + cpbSize = end - base; + if (writep >= readp) + cpbFullness = writep - readp; + else + cpbFullness = (end - base) - (readp - writep); + + fifoSize = cpbSize - cpbFullness; + + + if (fifoSize < BC_INFIFO_THRESHOLD) + { + *empty_sz = 0; + return true; + } + + if (needed_sz > (fifoSize - BC_INFIFO_THRESHOLD)) + { + *empty_sz = 0; + return true; + } + *empty_sz = fifoSize - BC_INFIFO_THRESHOLD; + + return false; +} + +bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + /* reset list index.*/ + hw->tx_list_post_index = 0; + } + + tmp = err_sts & err_mask; + hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + /* reset list index.*/ + hw->tx_list_post_index = 0; + } + + tmp = err_sts & err_mask; + hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts) +{ + uint32_t err_sts; + + if (int_sts & INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, + BC_STS_SUCCESS); + + if (int_sts & INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, + BC_STS_SUCCESS); + + if (!(int_sts & (INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK | + INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK))) + /* No error mask set.. */ + return; + + /* Handle Tx errors. */ + err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); + + if (crystalhd_link_tx_list0_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, + BC_STS_ERROR); + + if (crystalhd_link_tx_list1_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, + BC_STS_ERROR); + + hw->stats.tx_errors++; +} + +void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) +{ + uint32_t dma_cntrl; + uint32_t first_desc_u_addr, first_desc_l_addr; + + if (list_id == 0) { + first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST0; + first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST0; + } else { + first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST1; + first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST1; + } + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp,MISC1_TX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); + + hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); + /* Be sure we set the valid bit ^^^^ */ + return; +} + +/* _CHECK_THIS_ + * + * Verify if the Stop generates a completion interrupt or not. + * if it does not generate an interrupt, then add polling here. + */ +BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw) +{ + struct device *dev; + uint32_t dma_cntrl, cnt = 30; + uint32_t l1 = 1, l2 = 1; + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "Stopping TX DMA Engine..\n"); + + if (!(dma_cntrl & DMA_START_BIT)) { + hw->tx_list_post_index = 0; + dev_dbg(dev, "Already Stopped\n"); + return BC_STS_SUCCESS; + } + + crystalhd_link_disable_interrupts(hw); + + /* Issue stop to HW */ + dma_cntrl &= ~DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + + dev_dbg(dev, "Cleared the DMA Start bit\n"); + + /* Poll for 3seconds (30 * 100ms) on both the lists..*/ + while ((l1 || l2) && cnt) { + + if (l1) { + l1 = hw->pfnReadFPGARegister(hw->adp, + MISC1_TX_FIRST_DESC_L_ADDR_LIST0); + l1 &= DMA_START_BIT; + } + + if (l2) { + l2 = hw->pfnReadFPGARegister(hw->adp, + MISC1_TX_FIRST_DESC_L_ADDR_LIST1); + l2 &= DMA_START_BIT; + } + + msleep_interruptible(100); + + cnt--; + } + + if (!cnt) { + dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); + crystalhd_link_enable_interrupts(hw); + return BC_STS_ERROR; + } + + hw->tx_list_post_index = 0; + dev_dbg(dev, "stopped TX DMA..\n"); + crystalhd_link_enable_interrupts(hw); + + return BC_STS_SUCCESS; +} + +uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw) +{ + /* + * Position of the PIB Entries can be found at + * 0th and the 1st location of the Circular list. + */ + uint32_t Q_addr; + uint32_t pib_cnt, r_offset, w_offset; + + Q_addr = hw->pib_del_Q_addr; + + /* Get the Read Pointer */ + crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); + + /* Get the Write Pointer */ + crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); + + if (r_offset == w_offset) + return 0; /* Queue is empty */ + + if (w_offset > r_offset) + pib_cnt = w_offset - r_offset; + else + pib_cnt = (w_offset + MAX_PIB_Q_DEPTH) - + (r_offset + MIN_PIB_Q_DEPTH); + + if (pib_cnt > MAX_PIB_Q_DEPTH) { + dev_err(&hw->adp->pdev->dev, "Invalid PIB Count (%u)\n", pib_cnt); + return 0; + } + + return pib_cnt; +} + +uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw) +{ + uint32_t Q_addr; + uint32_t addr_entry, r_offset, w_offset; + + Q_addr = hw->pib_del_Q_addr; + + /* Get the Read Pointer 0Th Location is Read Pointer */ + crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); + + /* Get the Write Pointer 1st Location is Write pointer */ + crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); + + /* Queue is empty */ + if (r_offset == w_offset) + return 0; + + if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) + return 0; + + /* Get the Actual Address of the PIB */ + crystalhd_link_mem_rd(hw, Q_addr + (r_offset * sizeof(uint32_t)), + 1, &addr_entry); + + /* Increment the Read Pointer */ + r_offset++; + + if (MAX_PIB_Q_DEPTH == r_offset) + r_offset = MIN_PIB_Q_DEPTH; + + /* Write back the read pointer to It's Location */ + crystalhd_link_mem_wr(hw, Q_addr, 1, &r_offset); + + return addr_entry; +} + +bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel) +{ + uint32_t Q_addr; + uint32_t r_offset, w_offset, n_offset; + + Q_addr = hw->pib_rel_Q_addr; + + /* Get the Read Pointer */ + crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); + + /* Get the Write Pointer */ + crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); + + if ((r_offset < MIN_PIB_Q_DEPTH) || + (r_offset >= MAX_PIB_Q_DEPTH)) + return false; + + n_offset = w_offset + 1; + + if (MAX_PIB_Q_DEPTH == n_offset) + n_offset = MIN_PIB_Q_DEPTH; + + if (r_offset == n_offset) + return false; /* should never happen */ + + /* Write the DRAM ADDR to the Queue at Next Offset */ + crystalhd_link_mem_wr(hw, Q_addr + (w_offset * sizeof(uint32_t)), + 1, &addr_to_rel); + + /* Put the New value of the write pointer in Queue */ + crystalhd_link_mem_wr(hw, Q_addr + sizeof(uint32_t), 1, &n_offset); + + return true; +} + +void link_cpy_pib_to_app(struct C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib) +{ + if (!src_pib || !dst_pib) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return; + } + + dst_pib->timeStamp = 0; + dst_pib->picture_number = src_pib->ppb.picture_number; + dst_pib->width = src_pib->ppb.width; + dst_pib->height = src_pib->ppb.height; + dst_pib->chroma_format = src_pib->ppb.chroma_format; + dst_pib->pulldown = src_pib->ppb.pulldown; + dst_pib->flags = src_pib->ppb.flags; + dst_pib->sess_num = src_pib->ptsStcOffset; + dst_pib->aspect_ratio = src_pib->ppb.aspect_ratio; + dst_pib->colour_primaries = src_pib->ppb.colour_primaries; + dst_pib->picture_meta_payload = src_pib->ppb.picture_meta_payload; + dst_pib->frame_rate = src_pib->resolution ; + return; +} + +void crystalhd_link_proc_pib(struct crystalhd_hw *hw) +{ + unsigned int cnt; + struct C011_PIB src_pib; + uint32_t pib_addr, pib_cnt; + BC_PIC_INFO_BLOCK *AppPib; + struct crystalhd_rx_dma_pkt *rx_pkt = NULL; + + pib_cnt = crystalhd_link_get_pib_avail_cnt(hw); + + if (!pib_cnt) + return; + + for (cnt = 0; cnt < pib_cnt; cnt++) { + pib_addr = crystalhd_link_get_addr_from_pib_Q(hw); + crystalhd_link_mem_rd(hw, pib_addr, sizeof(struct C011_PIB) / 4, + (uint32_t *)&src_pib); + + if (src_pib.bFormatChange) { + rx_pkt = (struct crystalhd_rx_dma_pkt *) + crystalhd_dioq_fetch(hw->rx_freeq); + if (!rx_pkt) + return; + + rx_pkt->flags = 0; + rx_pkt->flags |= COMP_FLAG_PIB_VALID | + COMP_FLAG_FMT_CHANGE; + AppPib = &rx_pkt->pib; + link_cpy_pib_to_app(&src_pib, AppPib); + + hw->PICHeight = rx_pkt->pib.height; + if (rx_pkt->pib.width > 1280) + hw->PICWidth = 1920; + else if (rx_pkt->pib.width > 720) + hw->PICWidth = 1280; + else + hw->PICWidth = 720; + + dev_info(&hw->adp->pdev->dev, + "[FMT CH] PIB:%x %x %x %x %x %x %x %x %x %x\n", + rx_pkt->pib.picture_number, + rx_pkt->pib.aspect_ratio, + rx_pkt->pib.chroma_format, + rx_pkt->pib.colour_primaries, + rx_pkt->pib.frame_rate, + rx_pkt->pib.height, + rx_pkt->pib.width, + rx_pkt->pib.n_drop, + rx_pkt->pib.pulldown, + rx_pkt->pib.ycom); + + crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, + true, rx_pkt->pkt_tag); + + } + + crystalhd_link_rel_addr_to_pib_Q(hw, pib_addr); + } +} + +void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl; + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + return; +} + +void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw) +{ + struct device *dev = &hw->adp->pdev->dev; + uint32_t dma_cntrl = 0, count = 30; + uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if ((dma_cntrl & DMA_START_BIT)) { + dma_cntrl &= ~DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if ((dma_cntrl & DMA_START_BIT)) { + dma_cntrl &= ~DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + /* Poll for 3seconds (30 * 100ms) on both the lists..*/ + while ((l0y || l0uv || l1y || l1uv) && count) { + + if (l0y) { + l0y = hw->pfnReadFPGARegister(hw->adp, + MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); + l0y &= DMA_START_BIT; + if (!l0y) + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + } + + if (l1y) { + l1y = hw->pfnReadFPGARegister(hw->adp, + MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); + l1y &= DMA_START_BIT; + if (!l1y) + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + } + + if (l0uv) { + l0uv = hw->pfnReadFPGARegister(hw->adp, + MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); + l0uv &= DMA_START_BIT; + if (!l0uv) + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + } + + if (l1uv) { + l1uv = hw->pfnReadFPGARegister(hw->adp, + MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); + l1uv &= DMA_START_BIT; + if (!l1uv) + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + } + msleep_interruptible(100); + count--; + } + + hw->rx_list_post_index = 0; + + dev_dbg(dev, "Capture Stop: %d List0:Sts:%x List1:Sts:%x\n", + count, hw->rx_list_sts[0], hw->rx_list_sts[1]); +} + +BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, + struct crystalhd_rx_dma_pkt *rx_pkt) +{ + struct device *dev; + uint32_t y_low_addr_reg, y_high_addr_reg; + uint32_t uv_low_addr_reg, uv_high_addr_reg; + addr_64 desc_addr; + unsigned long flags; + + if (!hw || !rx_pkt) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { + dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); + return BC_STS_INV_ARG; + } + + spin_lock_irqsave(&hw->rx_lock, flags); + if (hw->rx_list_sts[hw->rx_list_post_index]) { + spin_unlock_irqrestore(&hw->rx_lock, flags); + return BC_STS_BUSY; + } + + if (!hw->rx_list_post_index) { + y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0; + y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0; + uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0; + uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0; + } else { + y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1; + y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1; + uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1; + uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1; + } + rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; + if (rx_pkt->uv_phy_addr) + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; + hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; + + crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); + + crystalhd_link_start_rx_dma_engine(hw); + /* Program the Y descriptor */ + desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; + hw->pfnWriteFPGARegister(hw->adp, y_high_addr_reg, desc_addr.high_part); + hw->pfnWriteFPGARegister(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01); + + if (rx_pkt->uv_phy_addr) { + /* Program the UV descriptor */ + desc_addr.full_addr = rx_pkt->uv_phy_addr; + hw->pfnWriteFPGARegister(hw->adp, uv_high_addr_reg, desc_addr.high_part); + hw->pfnWriteFPGARegister(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01); + } + + spin_unlock_irqrestore(&hw->rx_lock, flags); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, + struct crystalhd_rx_dma_pkt *rx_pkt) +{ + BC_STATUS sts = crystalhd_link_hw_prog_rxdma(hw, rx_pkt); + + if (sts == BC_STS_BUSY) + crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, + false, rx_pkt->pkt_tag); + + return sts; +} + +void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, + uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) +{ + uint32_t y_dn_sz_reg, uv_dn_sz_reg; + + if (!list_index) { + y_dn_sz_reg = MISC1_Y_RX_LIST0_CUR_BYTE_CNT; + uv_dn_sz_reg = MISC1_UV_RX_LIST0_CUR_BYTE_CNT; + } else { + y_dn_sz_reg = MISC1_Y_RX_LIST1_CUR_BYTE_CNT; + uv_dn_sz_reg = MISC1_UV_RX_LIST1_CUR_BYTE_CNT; + } + + *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); + *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); +} + +/* + * This function should be called only after making sure that the two DMA + * lists are free. This function does not check if DMA's are active, before + * turning off the DMA. + */ +void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl; + + hw->stop_pending = 0; + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if (dma_cntrl & DMA_START_BIT) { + dma_cntrl &= ~DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if (dma_cntrl & DMA_START_BIT) { + dma_cntrl &= ~DMA_START_BIT; + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + hw->rx_list_post_index = 0; + +/* aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); */ +/* aspm |= ASPM_L1_ENABLE; */ +/* dev_info(&hw->adp->pdev->dev, "aspm on\n"); */ +/* crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); */ +} + +bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw, + uint32_t int_sts, + uint32_t y_err_sts, + uint32_t uv_err_sts) +{ + uint32_t tmp; + enum list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[0]; + + /* Y0 - DMA */ + tmp = y_err_sts & GET_Y0_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV0 - DMA */ + tmp = uv_err_sts & GET_UV0_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y0_ERR_MSK) { + tmp = y_err_sts & GET_Y0_ERR_MSK; + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV0_ERR_MSK) { + tmp = uv_err_sts & GET_UV0_ERR_MSK; + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[0]); +} + +bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw, + uint32_t int_sts, uint32_t y_err_sts, + uint32_t uv_err_sts) +{ + uint32_t tmp; + enum list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[1]; + + /* Y1 - DMA */ + tmp = y_err_sts & GET_Y1_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Add retry-support..*/ + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV1 - DMA */ + tmp = uv_err_sts & GET_UV1_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Add retry-support*/ + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y1_ERR_MSK) { + tmp = y_err_sts & GET_Y1_ERR_MSK; + hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV1_ERR_MSK) { + tmp = uv_err_sts & GET_UV1_ERR_MSK; + hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[1]); +} + +void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) +{ + unsigned long flags; + uint32_t i, list_avail = 0; + BC_STATUS comp_sts = BC_STS_NO_DATA; + uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; + bool ret = 0; + + if (!hw) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return; + } + + if (!(intr_sts & GET_RX_INTR_MASK)) + return; + + y_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); + uv_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); + + for (i = 0; i < DMA_ENGINE_CNT; i++) { + /* Update States..*/ + spin_lock_irqsave(&hw->rx_lock, flags); + if (i == 0) + ret = crystalhd_link_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); + else + ret = crystalhd_link_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); + if (ret) { + switch (hw->rx_list_sts[i]) { + case sts_free: + comp_sts = BC_STS_SUCCESS; + list_avail = 1; + hw->stats.rx_success++; + break; + case rx_y_error: + case rx_uv_error: + case rx_sts_error: + /* We got error on both or Y or uv. */ + hw->stats.rx_errors++; + hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); + dev_info(&hw->adp->pdev->dev, "list_index:%x " + "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " + "UVDnSz:%x\n", i, hw->stats.rx_errors, + hw->stats.rx_errors + hw->stats.rx_success, + y_err_sts, uv_err_sts, intr_sts, + y_dn_sz, uv_dn_sz); + hw->rx_list_sts[i] = sts_free; + comp_sts = BC_STS_ERROR; + break; + default: + /* Wait for completion..*/ + comp_sts = BC_STS_NO_DATA; + break; + } + } + spin_unlock_irqrestore(&hw->rx_lock, flags); + + /* handle completion...*/ + if (comp_sts != BC_STS_NO_DATA) { + crystalhd_rx_pkt_done(hw, i, comp_sts); + comp_sts = BC_STS_NO_DATA; + } + } + + if (list_avail) { + if (hw->stop_pending) { + if ((hw->rx_list_sts[0] == sts_free) && + (hw->rx_list_sts[1] == sts_free)) + crystalhd_link_hw_finalize_pause(hw); + } else { + if(!hw->hw_pause_issued) + crystalhd_hw_start_capture(hw); + } + } +} + +BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state) +{ + uint32_t pause = 0; + BC_STATUS sts = BC_STS_SUCCESS; + + if(state) { + pause = 1; + hw->stats.pause_cnt++; + hw->stop_pending = 1; + hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); + + if ((hw->rx_list_sts[0] == sts_free) && + (hw->rx_list_sts[1] == sts_free)) + crystalhd_link_hw_finalize_pause(hw); + } else { + pause = 0; + hw->stop_pending = 0; + sts = crystalhd_hw_start_capture(hw); + hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); + } + return sts; +} + +BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, + BC_FW_CMD *fw_cmd) +{ + BC_STATUS sts = BC_STS_SUCCESS; + struct DecRspChannelStartVideo *st_rsp = NULL; + + switch (fw_cmd->cmd[0]) { + case eCMD_C011_DEC_CHAN_START_VIDEO: + st_rsp = (struct DecRspChannelStartVideo *)fw_cmd->rsp; + hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; + hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; + dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", + hw->pib_del_Q_addr, hw->pib_rel_Q_addr); + break; + case eCMD_C011_INIT: + if (!(crystalhd_link_load_firmware_config(hw))) { + dev_err(&hw->adp->pdev->dev, "Invalid Params\n"); + sts = BC_STS_FW_AUTH_FAILED; + } + break; + default: + break; + } + return sts; +} + +BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw) +{ + uint32_t reg; + union link_misc_perst_decoder_ctrl rst_cntrl_reg; + + /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ + rst_cntrl_reg.whole_reg = hw->pfnReadDevRegister(hw->adp, MISC_PERST_DECODER_CTRL); + + rst_cntrl_reg.bcm_7412_rst = 1; + hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + msleep_interruptible(50); + + rst_cntrl_reg.bcm_7412_rst = 0; + hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + + /* Close all banks, put DDR in idle */ + hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); + + /* Set bit 25 (drop CKE pin of DDR) */ + reg = hw->pfnReadDevRegister(hw->adp, SDRAM_PARAM); + reg |= 0x02000000; + hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, reg); + + /* Reset the audio block */ + hw->pfnWriteDevRegister(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1); + + /* Power down Raptor PLL */ + reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllCCtl); + reg |= 0x00008000; + hw->pfnWriteDevRegister(hw->adp, DecHt_PllCCtl, reg); + + /* Power down all Audio PLL */ + hw->pfnWriteDevRegister(hw->adp, AIO_MISC_PLL_RESET, 0x1); + + /* Power down video clock (75MHz) */ + reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllECtl); + reg |= 0x00008000; + hw->pfnWriteDevRegister(hw->adp, DecHt_PllECtl, reg); + + /* Power down video clock (75MHz) */ + reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllDCtl); + reg |= 0x00008000; + hw->pfnWriteDevRegister(hw->adp, DecHt_PllDCtl, reg); + + /* Power down core clock (200MHz) */ + reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllACtl); + reg |= 0x00008000; + hw->pfnWriteDevRegister(hw->adp, DecHt_PllACtl, reg); + + /* Power down core clock (200MHz) */ + reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllBCtl); + reg |= 0x00008000; + hw->pfnWriteDevRegister(hw->adp, DecHt_PllBCtl, reg); + + return BC_STS_SUCCESS; +} + +/************************************************ +** +*************************************************/ + +BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw *hw, + uint8_t *buffer, uint32_t sz) +{ + struct device *dev; + uint32_t reg_data, cnt, *temp_buff; + uint32_t fw_sig_len = 36; + uint32_t dram_offset = BC_FWIMG_ST_ADDR, sig_reg; + + if (!hw || !buffer || !sz) { + printk(KERN_ERR "%s: Invalid Params\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "%s entered\n", __func__); + + reg_data = hw->pfnReadFPGARegister(hw->adp, OTP_CMD); + if (!(reg_data & 0x02)) { + dev_err(dev, "Invalid hw config.. otp not programmed\n"); + return BC_STS_ERROR; + } + + reg_data = 0; + hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, 0); + reg_data |= BC_BIT(0); + hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); + + reg_data = 0; + cnt = 1000; + msleep_interruptible(10); + + while (reg_data != BC_BIT(4)) { + reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); + reg_data &= BC_BIT(4); + if (--cnt == 0) { + dev_err(dev, "Firmware Download RDY Timeout.\n"); + return BC_STS_TIMEOUT; + } + } + + msleep_interruptible(10); + /* Load the FW to the FW_ADDR field in the DCI_FIRMWARE_ADDR */ + hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_ADDR, dram_offset); + temp_buff = (uint32_t *)buffer; + for (cnt = 0; cnt < (sz - fw_sig_len); cnt += 4) { + hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19)); + hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_DATA, *temp_buff); + dram_offset += 4; + temp_buff++; + } + msleep_interruptible(10); + + temp_buff++; + + sig_reg = (uint32_t)DCI_SIGNATURE_DATA_7; + for (cnt = 0; cnt < 8; cnt++) { + uint32_t swapped_data = *temp_buff; + swapped_data = cpu_to_be32(swapped_data); + hw->pfnWriteFPGARegister(hw->adp, sig_reg, swapped_data); + sig_reg -= 4; + temp_buff++; + } + msleep_interruptible(10); + + reg_data = 0; + reg_data |= BC_BIT(1); + hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); + msleep_interruptible(10); + + reg_data = 0; + reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); + + if ((reg_data & BC_BIT(9)) == BC_BIT(9)) { + cnt = 1000; + while ((reg_data & BC_BIT(0)) != BC_BIT(0)) { + reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); + reg_data &= BC_BIT(0); + if (!(--cnt)) + break; + msleep_interruptible(10); + } + reg_data = 0; + reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_CMD); + reg_data |= BC_BIT(4); + hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); + + } else { + dev_err(dev, "F/w Signature mismatch\n"); + return BC_STS_FW_AUTH_FAILED; + } + + dev_dbg(dev, "Firmware Downloaded Successfully\n"); + + /* Load command response addresses */ + hw->fwcmdPostAddr = TS_Host2CpuSnd; + hw->fwcmdPostMbox = Hst2CpuMbx1; + hw->fwcmdRespMbox = Cpu2HstMbx1; + + return BC_STS_SUCCESS;; +} + +BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) +{ + struct device *dev; + uint32_t cnt = 0, cmd_res_addr; + uint32_t *cmd_buff, *res_buff; + wait_queue_head_t fw_cmd_event; + int rc = 0; + BC_STATUS sts; + unsigned long flags; + + crystalhd_create_event(&fw_cmd_event); + + if (!hw || !fw_cmd) { + printk(KERN_ERR "%s: Invalid Arguments\n", __func__); + return BC_STS_INV_ARG; + } + + dev = &hw->adp->pdev->dev; + + dev_dbg(dev, "%s entered\n", __func__); + + cmd_buff = fw_cmd->cmd; + res_buff = fw_cmd->rsp; + + if (!cmd_buff || !res_buff) { + dev_err(dev, "Invalid Parameters for F/W Command\n"); + return BC_STS_INV_ARG; + } + + hw->fwcmd_evt_sts = 0; + hw->pfw_cmd_event = &fw_cmd_event; + + spin_lock_irqsave(&hw->lock, flags); + + /*Write the command to the memory*/ + hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); + + /*Memory Read for memory arbitrator flush*/ + hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); + + /* Write the command address to mailbox */ + hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); + + spin_unlock_irqrestore(&hw->lock, flags); + + msleep_interruptible(50); + + /* FW commands should complete even if we got a signal from the upper layer */ + crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, + 20000, rc, true); + + if (!rc) { + sts = BC_STS_SUCCESS; + } else if (rc == -EBUSY) { + dev_err(dev, "Firmware command T/O\n"); + sts = BC_STS_TIMEOUT; + } else if (rc == -EINTR) { + dev_err(dev, "FwCmd Wait Signal int - Should never happen\n"); + sts = BC_STS_IO_USER_ABORT; + } else { + dev_err(dev, "FwCmd IO Error.\n"); + sts = BC_STS_IO_ERROR; + } + + if (sts != BC_STS_SUCCESS) { + dev_err(dev, "FwCmd Failed.\n"); + return sts; + } + + spin_lock_irqsave(&hw->lock, flags); + + /*Get the Responce Address*/ + cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); + + /*Read the Response*/ + hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); + + spin_unlock_irqrestore(&hw->lock, flags); + + if (res_buff[2] != C011_RET_SUCCESS) { + dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); + return BC_STS_FW_CMD_ERR; + } + + sts = crystalhd_link_fw_cmd_post_proc(hw, fw_cmd); + if (sts != BC_STS_SUCCESS) + dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); + + return sts; +} + +bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) +{ + uint32_t intr_sts = 0; + uint32_t deco_intr = 0; + bool rc = false; + + if (!adp || !hw->dev_started) + return rc; + + hw->stats.num_interrupts++; + + deco_intr = hw->pfnReadDevRegister(hw->adp, Stream2Host_Intr_Sts); + intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); + + if (intr_sts) { + /* let system know we processed interrupt..*/ + rc = true; + hw->stats.dev_interrupts++; + } + + if (deco_intr && (deco_intr != 0xdeaddead)) { + + if (deco_intr & 0x80000000) { + /*Set the Event and the status flag*/ + if (hw->pfw_cmd_event) { + hw->fwcmd_evt_sts = 1; + crystalhd_set_event(hw->pfw_cmd_event); + } + } + + if (deco_intr & BC_BIT(1)) + crystalhd_link_proc_pib(hw); + + hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, deco_intr); + hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, 0); + rc = 1; + } + + /* Rx interrupts */ + crystalhd_link_rx_isr(hw, intr_sts); + + /* Tx interrupts*/ + crystalhd_link_tx_isr(hw, intr_sts); + + /* Clear interrupts */ + if (rc) { + if (intr_sts) + hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); + + hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); + } + + return rc; +} + +/* Dummy private function */ +void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) +{ + return; +} + +bool crystalhd_link_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode) +{ + return true; +} --- crystalhd~/crystalhd_linkfuncs.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/crystalhd_linkfuncs.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,228 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_linkfuncs . h + * + * Description: + * BCM70012 Linux driver hardware layer. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_LINKFUNCS_H_ +#define _CRYSTALHD_LINKFUNCS_H_ + +#define ASPM_L1_ENABLE (BC_BIT(27)) + +/************************************************* + 7412 Decoder Registers. +**************************************************/ +#define FW_CMD_BUFF_SZ 64 +#define TS_Host2CpuSnd 0x00000100 +#define HW_PauseMbx 0x00000300 +#define Hst2CpuMbx1 0x00100F00 +#define Cpu2HstMbx1 0x00100F04 +#define MbxStat1 0x00100F08 +#define Stream2Host_Intr_Sts 0x00100F24 +#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ + +/* TS input status register */ +#define TS_StreamAFIFOStatus 0x0010044C +#define TS_StreamBFIFOStatus 0x0010084C + +/*UART Selection definitions*/ +#define UartSelectA 0x00100300 +#define UartSelectB 0x00100304 + +#define BSVS_UART_DEC_NONE 0x00 +#define BSVS_UART_DEC_OUTER 0x01 +#define BSVS_UART_DEC_INNER 0x02 +#define BSVS_UART_STREAM 0x03 + +/* Code-In fifo */ +#define REG_DecCA_RegCinCTL 0xa00 +#define REG_DecCA_RegCinBase 0xa0c +#define REG_DecCA_RegCinEnd 0xa10 +#define REG_DecCA_RegCinWrPtr 0xa04 +#define REG_DecCA_RegCinRdPtr 0xa08 + +#define REG_Dec_TsUser0Base 0x100864 +#define REG_Dec_TsUser0Rdptr 0x100868 +#define REG_Dec_TsUser0Wrptr 0x10086C +#define REG_Dec_TsUser0End 0x100874 + +/* ASF Case ...*/ +#define REG_Dec_TsAudCDB2Base 0x10036c +#define REG_Dec_TsAudCDB2Rdptr 0x100378 +#define REG_Dec_TsAudCDB2Wrptr 0x100374 +#define REG_Dec_TsAudCDB2End 0x100370 + +/* DRAM bringup Registers */ +#define SDRAM_PARAM 0x00040804 +#define SDRAM_PRECHARGE 0x000408B0 +#define SDRAM_EXT_MODE 0x000408A4 +#define SDRAM_MODE 0x000408A0 +#define SDRAM_REFRESH 0x00040890 +#define SDRAM_REF_PARAM 0x00040808 + +#define DecHt_PllACtl 0x34000C +#define DecHt_PllBCtl 0x340010 +#define DecHt_PllCCtl 0x340014 +#define DecHt_PllDCtl 0x340034 +#define DecHt_PllECtl 0x340038 +#define AUD_DSP_MISC_SOFT_RESET 0x00240104 +#define AIO_MISC_PLL_RESET 0x0026000C +#define PCIE_CLK_REQ_REG 0xDC +#define PCI_CLK_REQ_ENABLE (BC_BIT(8)) + +/************************************************* + F/W Copy engine definitions.. +**************************************************/ +#define BC_FWIMG_ST_ADDR 0x00000000 + +#define DecHt_HostSwReset 0x340000 +#define BC_DRAM_FW_CFG_ADDR 0x001c2000 + +union intr_mask_reg { + struct { + uint32_t mask_tx_done:1; + uint32_t mask_tx_err:1; + uint32_t mask_rx_done:1; + uint32_t mask_rx_err:1; + uint32_t mask_pcie_err:1; + uint32_t mask_pcie_rbusmast_err:1; + uint32_t mask_pcie_rgr_bridge:1; + uint32_t reserved:25; + }; + + uint32_t whole_reg; + +}; + +union link_misc_perst_deco_ctrl { + struct { + uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t reserved0:3; /* Reserved.No Effect*/ + uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t reserved1:27; /* Reseved. No Effect*/ + }; + + uint32_t whole_reg; + +}; + +union link_misc_perst_clk_ctrl { + struct { + uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ + uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ + uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set + to select an alternate clock before setting this bit.*/ + uint32_t reserved0:5; /* Reserved */ + uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ + uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ + uint32_t reserved1:12; /* Reserved */ + }; + + uint32_t whole_reg; + +}; + + +union link_misc_perst_decoder_ctrl { + struct { + uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t res0:3; /* Reserved.No Effect*/ + uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t res1:27; /* Reseved. No Effect */ + }; + + uint32_t whole_reg; + +}; + +/* DMA engine register BIT mask wrappers.. */ +#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK + +#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) + +uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); +void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); +uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); +void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); +uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off); +void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val); +BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); +BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); +void crystalhd_link_enable_uarts(struct crystalhd_hw *hw); +void crystalhd_link_start_dram(struct crystalhd_hw *hw); +bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw); +bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw); +void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw); +void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw); +void crystalhd_link_clear_errors(struct crystalhd_hw *hw); +void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw); +void crystalhd_link_soft_rst(struct crystalhd_hw *hw); +bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw); +bool crystalhd_link_start_device(struct crystalhd_hw *hw); +bool crystalhd_link_stop_device(struct crystalhd_hw *hw); +uint32_t link_GetPicInfoLineNum(struct crystalhd_dio_req *dio, uint8_t *base); +uint32_t link_GetMode422Data(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine, int type); +uint32_t link_GetMetaDataFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); +uint32_t link_GetHeightFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); +bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, struct crystalhd_dio_req *dio, + uint32_t *PicNumber, uint64_t *PicMetaData); +uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *pRxDMAReq); +bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); +bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, + bool b_188_byte_pkts, uint8_t *flags); +bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); +bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); +void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts); +void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); +BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw); +uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw); +uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw); +bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel); +void link_cpy_pib_to_app(struct C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib); +void crystalhd_link_proc_pib(struct crystalhd_hw *hw); +void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw); +void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw); +BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); +BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); +void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, + uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); +void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw); +bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); +bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); +void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts); +BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state); +BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); +BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw); +BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); +BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); +bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); +void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); +bool crystalhd_link_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode); +#endif --- crystalhd~/crystalhd_lnx.c 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_lnx.c 2015-04-06 20:13:44.000000000 +0300 @@ -15,18 +15,33 @@ along with this driver. If not, see . ***************************************************************************/ -#include "crystalhd.h" +#include -#include -#include +#include "crystalhd_lnx.h" - -static DEFINE_MUTEX(chd_dec_mutex); static struct class *crystalhd_class; static struct crystalhd_adp *g_adp_info; +extern int bc_get_userhandle_count(struct crystalhd_cmd *ctx); + +struct device *chddev(void) +{ + return &g_adp_info->pdev->dev; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) +loff_t noop_llseek(struct file *file, loff_t offset, int origin) +{ + return file->f_pos; +} +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18) static irqreturn_t chd_dec_isr(int irq, void *arg) +#else +static irqreturn_t chd_dec_isr(int irq, void *arg, struct pt_regs *r) +#endif { struct crystalhd_adp *adp = (struct crystalhd_adp *) arg; int rc = 0; @@ -41,20 +56,25 @@ static int chd_dec_enable_int(struct cry int rc = 0; if (!adp || !adp->pdev) { - BCMLOG_ERR("Invalid arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } - if (adp->pdev->msi_enabled) - adp->msi = 1; + rc = pci_enable_msi(adp->pdev); + if(rc != 0) + dev_err(&adp->pdev->dev, "MSI request failed..\n"); else - adp->msi = pci_enable_msi(adp->pdev); + adp->msi = 1; rc = request_irq(adp->pdev->irq, chd_dec_isr, IRQF_SHARED, adp->name, (void *)adp); - if (rc) { - BCMLOG_ERR("Interrupt request failed..\n"); - pci_disable_msi(adp->pdev); + + if (rc != 0) { + dev_err(&adp->pdev->dev, "Interrupt request failed..\n"); + if(adp->msi) { + pci_disable_msi(adp->pdev); + adp->msi = 0; + } } return rc; @@ -63,24 +83,24 @@ static int chd_dec_enable_int(struct cry static int chd_dec_disable_int(struct crystalhd_adp *adp) { if (!adp || !adp->pdev) { - BCMLOG_ERR("Invalid arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } free_irq(adp->pdev->irq, adp); - if (adp->msi) + if (adp->msi) { pci_disable_msi(adp->pdev); + adp->msi = 0; + } return 0; } -static struct -crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, - bool isr) +crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr) { unsigned long flags = 0; - struct crystalhd_ioctl_data *temp; + crystalhd_ioctl_data *temp; if (!adp) return NULL; @@ -97,8 +117,8 @@ crystalhd_ioctl_data *chd_dec_alloc_ioda return temp; } -static void chd_dec_free_iodata(struct crystalhd_adp *adp, - struct crystalhd_ioctl_data *iodata, bool isr) +void chd_dec_free_iodata(struct crystalhd_adp *adp, crystalhd_ioctl_data *iodata, + bool isr) { unsigned long flags = 0; @@ -111,13 +131,12 @@ static void chd_dec_free_iodata(struct c spin_unlock_irqrestore(&adp->lock, flags); } -static inline int crystalhd_user_data(unsigned long ud, void *dr, - int size, int set) +static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int set) { int rc; if (!ud || !dr) { - BCMLOG_ERR("Invalid arg\n"); + dev_err(chddev(), "%s: Invalid arg\n", __func__); return -EINVAL; } @@ -127,27 +146,27 @@ static inline int crystalhd_user_data(un rc = copy_from_user(dr, (void *)ud, size); if (rc) { - BCMLOG_ERR("Invalid args for command\n"); + dev_err(chddev(), "Invalid args for command\n"); rc = -EFAULT; } return rc; } -static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, - struct crystalhd_ioctl_data *io, uint32_t m_sz, unsigned long ua) +static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, + uint32_t m_sz, unsigned long ua) { unsigned long ua_off; int rc = 0; if (!adp || !io || !ua || !m_sz) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } io->add_cdata = vmalloc(m_sz); if (!io->add_cdata) { - BCMLOG_ERR("kalloc fail for sz:%x\n", m_sz); + dev_err(chddev(), "kalloc fail for sz:%x\n", m_sz); return -ENOMEM; } @@ -155,9 +174,10 @@ static int chd_dec_fetch_cdata(struct cr ua_off = ua + sizeof(io->udata); rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 0); if (rc) { - BCMLOG_ERR("failed to pull add_cdata sz:%x ua_off:%x\n", - io->add_cdata_sz, (unsigned int)ua_off); - vfree(io->add_cdata); + dev_err(chddev(), "failed to pull add_cdata sz:%x " + "ua_off:%x\n", io->add_cdata_sz, + (unsigned int)ua_off); + kfree(io->add_cdata); io->add_cdata = NULL; return -ENODATA; } @@ -166,13 +186,13 @@ static int chd_dec_fetch_cdata(struct cr } static int chd_dec_release_cdata(struct crystalhd_adp *adp, - struct crystalhd_ioctl_data *io, unsigned long ua) + crystalhd_ioctl_data *io, unsigned long ua) { unsigned long ua_off; int rc; if (!adp || !io || !ua) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } @@ -181,9 +201,9 @@ static int chd_dec_release_cdata(struct rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 1); if (rc) { - BCMLOG_ERR( - "failed to push add_cdata sz:%x ua_off:%x\n", - io->add_cdata_sz, (unsigned int)ua_off); + dev_err(chddev(), "failed to push add_cdata sz:%x " + "ua_off:%x\n", io->add_cdata_sz, + (unsigned int)ua_off); return -ENODATA; } } @@ -197,20 +217,21 @@ static int chd_dec_release_cdata(struct } static int chd_dec_proc_user_data(struct crystalhd_adp *adp, - struct crystalhd_ioctl_data *io, + crystalhd_ioctl_data *io, unsigned long ua, int set) { int rc; uint32_t m_sz = 0; if (!adp || !io || !ua) { - BCMLOG_ERR("Invalid Arg!!\n"); + dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } rc = crystalhd_user_data(ua, &io->udata, sizeof(io->udata), set); if (rc) { - BCMLOG_ERR("failed to %s iodata\n", (set ? "set" : "get")); + dev_err(chddev(), "failed to %s iodata\n", + (set ? "set" : "get")); return rc; } @@ -235,12 +256,12 @@ static int chd_dec_api_cmd(struct crysta uint32_t uid, uint32_t cmd, crystalhd_cmd_proc func) { int rc; - struct crystalhd_ioctl_data *temp; - enum BC_STATUS sts = BC_STS_SUCCESS; + crystalhd_ioctl_data *temp; + BC_STATUS sts = BC_STS_SUCCESS; temp = chd_dec_alloc_iodata(adp, 0); if (!temp) { - BCMLOG_ERR("Failed to get iodata..\n"); + dev_err(chddev(), "Failed to get iodata..\n"); return -EINVAL; } @@ -249,76 +270,88 @@ static int chd_dec_api_cmd(struct crysta rc = chd_dec_proc_user_data(adp, temp, ua, 0); if (!rc) { - sts = func(&adp->cmds, temp); + if(func == NULL) + sts = BC_STS_PWR_MGMT; /* Can only happen when we are in suspend state */ + else + sts = func(&adp->cmds, temp); if (sts == BC_STS_PENDING) sts = BC_STS_NOT_IMPL; temp->udata.RetSts = sts; rc = chd_dec_proc_user_data(adp, temp, ua, 1); } - chd_dec_free_iodata(adp, temp, 0); + if (temp) { + chd_dec_free_iodata(adp, temp, 0); + temp = NULL; + } return rc; } /* API interfaces */ -static long chd_dec_ioctl(struct file *fd, unsigned int cmd, unsigned long ua) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) +static int chd_dec_ioctl(struct inode *in, struct file *fd, + unsigned int cmd, unsigned long ua) +#else +static long chd_dec_ioctl(struct file *fd, + unsigned int cmd, unsigned long ua) +#endif { struct crystalhd_adp *adp = chd_get_adp(); + struct device *dev = &adp->pdev->dev; crystalhd_cmd_proc cproc; struct crystalhd_user *uc; - int ret; + + dev_dbg(dev, "Entering %s\n", __func__); if (!adp || !fd) { - BCMLOG_ERR("Invalid adp\n"); + dev_err(chddev(), "Invalid adp\n"); return -EINVAL; } uc = fd->private_data; if (!uc) { - BCMLOG_ERR("Failed to get uc\n"); + dev_err(chddev(), "Failed to get uc\n"); return -ENODATA; } - mutex_lock(&chd_dec_mutex); cproc = crystalhd_get_cmd_proc(&adp->cmds, cmd, uc); - if (!cproc) { - BCMLOG_ERR("Unhandled command: %d\n", cmd); - mutex_unlock(&chd_dec_mutex); + if (!cproc && !(adp->cmds.state & BC_LINK_SUSPEND)) { + dev_err(chddev(), "Unhandled command: %d\n", cmd); return -EINVAL; } - ret = chd_dec_api_cmd(adp, ua, uc->uid, cmd, cproc); - mutex_unlock(&chd_dec_mutex); - return ret; + return chd_dec_api_cmd(adp, ua, uc->uid, cmd, cproc); } static int chd_dec_open(struct inode *in, struct file *fd) { struct crystalhd_adp *adp = chd_get_adp(); + struct device *dev = &adp->pdev->dev; int rc = 0; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; struct crystalhd_user *uc = NULL; + dev_dbg(dev, "Entering %s\n", __func__); if (!adp) { - BCMLOG_ERR("Invalid adp\n"); + dev_err(dev, "Invalid adp\n"); return -EINVAL; } if (adp->cfg_users >= BC_LINK_MAX_OPENS) { - BCMLOG(BCMLOG_INFO, "Already in use.%d\n", adp->cfg_users); + dev_info(dev, "Already in use.%d\n", adp->cfg_users); return -EBUSY; } sts = crystalhd_user_open(&adp->cmds, &uc); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("cmd_user_open - %d\n", sts); + dev_err(dev, "cmd_user_open - %d\n", sts); rc = -EBUSY; } - - adp->cfg_users++; - - fd->private_data = uc; + else { + adp->cfg_users++; + fd->private_data = uc; + } return rc; } @@ -326,38 +359,83 @@ static int chd_dec_open(struct inode *in static int chd_dec_close(struct inode *in, struct file *fd) { struct crystalhd_adp *adp = chd_get_adp(); + struct device *dev = &adp->pdev->dev; + struct crystalhd_cmd *ctx = &adp->cmds; struct crystalhd_user *uc; + uint32_t mode; + dev_dbg(dev, "Entering %s\n", __func__); if (!adp) { - BCMLOG_ERR("Invalid adp\n"); + dev_err(dev, "Invalid adp\n"); return -EINVAL; } uc = fd->private_data; if (!uc) { - BCMLOG_ERR("Failed to get uc\n"); + dev_err(dev, "Failed to get uc\n"); return -ENODATA; } - crystalhd_user_close(&adp->cmds, uc); + /* Check and close only if we have not flush/closed before */ + /* This is needed because release is not guarenteed to be called immediately on close, + * if duplicate file handles exist due to fork etc. This causes problems with close and re-open + of the device immediately */ + + if(uc->in_use) { + mode = uc->mode; + + ctx->user[uc->uid].mode = DTS_MODE_INV; + ctx->user[uc->uid].in_use = 0; + + dev_info(chddev(), "Closing user[%x] handle with mode %x\n", uc->uid, mode); + + if (((mode & 0xFF) == DTS_DIAG_MODE) || + ((mode & 0xFF) == DTS_PLAYBACK_MODE) || + ((bc_get_userhandle_count(ctx) == 0) && (ctx->hw_ctx != NULL))) { + ctx->cin_wait_exit = 1; + ctx->pwr_state_change = BC_HW_RUNNING; + /* Stop the HW Capture just in case flush did not get called before stop */ + /* And only if we had actually started it */ + if(ctx->hw_ctx->rx_freeq != NULL) { + crystalhd_hw_stop_capture(ctx->hw_ctx, true); + crystalhd_hw_free_dma_rings(ctx->hw_ctx); + } + if(ctx->adp->fill_byte_pool) + crystalhd_destroy_dio_pool(ctx->adp); + if(ctx->adp->elem_pool_head) + crystalhd_delete_elem_pool(ctx->adp); + ctx->state = BC_LINK_INVALID; + crystalhd_hw_close(ctx->hw_ctx, ctx->adp); + kfree(ctx->hw_ctx); + ctx->hw_ctx = NULL; + } - adp->cfg_users--; + uc->in_use = 0; + + if(adp->cfg_users > 0) + adp->cfg_users--; + } return 0; } static const struct file_operations chd_dec_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = chd_dec_ioctl, - .open = chd_dec_open, - .release = chd_dec_close, - .llseek = noop_llseek, + .owner = THIS_MODULE, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) + .ioctl = chd_dec_ioctl, +#else + .unlocked_ioctl = chd_dec_ioctl, +#endif + .open = chd_dec_open, + .release = chd_dec_close, + .llseek = noop_llseek, }; static int chd_dec_init_chdev(struct crystalhd_adp *adp) { - struct crystalhd_ioctl_data *temp; + struct device *xdev = &adp->pdev->dev; struct device *dev; + crystalhd_ioctl_data *temp; int rc = -ENODEV, i = 0; if (!adp) @@ -366,7 +444,7 @@ static int chd_dec_init_chdev(struct cry adp->chd_dec_major = register_chrdev(0, CRYSTALHD_API_NAME, &chd_dec_fops); if (adp->chd_dec_major < 0) { - BCMLOG_ERR("Failed to create config dev\n"); + dev_err(xdev, "Failed to create config dev\n"); rc = adp->chd_dec_major; goto fail; } @@ -374,31 +452,33 @@ static int chd_dec_init_chdev(struct cry /* register crystalhd class */ crystalhd_class = class_create(THIS_MODULE, "crystalhd"); if (IS_ERR(crystalhd_class)) { - rc = PTR_ERR(crystalhd_class); - BCMLOG_ERR("failed to create class\n"); - goto class_create_fail; + dev_err(xdev, "failed to create class\n"); + goto fail; } - dev = device_create(crystalhd_class, NULL, - MKDEV(adp->chd_dec_major, 0), NULL, "crystalhd"); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 25) + dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), + NULL, "crystalhd"); +#else + dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), + "crystalhd"); +#endif if (IS_ERR(dev)) { - rc = PTR_ERR(dev); - BCMLOG_ERR("failed to create device\n"); + dev_err(xdev, "failed to create device\n"); goto device_create_fail; } - rc = crystalhd_create_elem_pool(adp, BC_LINK_ELEM_POOL_SZ); - if (rc) { - BCMLOG_ERR("failed to create device\n"); - goto elem_pool_fail; - } +/* rc = crystalhd_create_elem_pool(adp, BC_LINK_ELEM_POOL_SZ); */ +/* if (rc) { */ +/* dev_err(xdev, "failed to create device\n"); */ +/* goto elem_pool_fail; */ +/* } */ /* Allocate general purpose ioctl pool. */ for (i = 0; i < CHD_IODATA_POOL_SZ; i++) { - temp = kzalloc(sizeof(struct crystalhd_ioctl_data), - GFP_KERNEL); + temp = kzalloc(sizeof(crystalhd_ioctl_data), GFP_KERNEL); if (!temp) { - BCMLOG_ERR("ioctl data pool kzalloc failed\n"); + dev_err(xdev, "ioctl data pool kzalloc failed\n"); rc = -ENOMEM; goto kzalloc_fail; } @@ -409,20 +489,18 @@ static int chd_dec_init_chdev(struct cry return 0; kzalloc_fail: - crystalhd_delete_elem_pool(adp); -elem_pool_fail: + /*crystalhd_delete_elem_pool(adp); */ +/*elem_pool_fail: */ device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); device_create_fail: class_destroy(crystalhd_class); -class_create_fail: - unregister_chrdev(adp->chd_dec_major, CRYSTALHD_API_NAME); fail: return rc; } static void chd_dec_release_chdev(struct crystalhd_adp *adp) { - struct crystalhd_ioctl_data *temp = NULL; + crystalhd_ioctl_data *temp = NULL; if (!adp) return; @@ -430,7 +508,7 @@ static void chd_dec_release_chdev(struct /* unregister crystalhd class */ device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); unregister_chrdev(adp->chd_dec_major, CRYSTALHD_API_NAME); - BCMLOG(BCMLOG_INFO, "released api device - %d\n", + dev_info(chddev(), "released api device - %d\n", adp->chd_dec_major); class_destroy(crystalhd_class); } @@ -442,58 +520,64 @@ static void chd_dec_release_chdev(struct kfree(temp); } while (temp); - crystalhd_delete_elem_pool(adp); + /*crystalhd_delete_elem_pool(adp); */ } static int chd_pci_reserve_mem(struct crystalhd_adp *pinfo) { + struct device *dev = &pinfo->pdev->dev; int rc; - unsigned long bar2 = pci_resource_start(pinfo->pdev, 2); - uint32_t mem_len = pci_resource_len(pinfo->pdev, 2); - unsigned long bar0 = pci_resource_start(pinfo->pdev, 0); - uint32_t i2o_len = pci_resource_len(pinfo->pdev, 0); - BCMLOG(BCMLOG_SSTEP, "bar2:0x%lx-0x%08x bar0:0x%lx-0x%08x\n", - bar2, mem_len, bar0, i2o_len); + uint32_t bar0 = pci_resource_start(pinfo->pdev, 0); + uint32_t i2o_len = pci_resource_len(pinfo->pdev, 0); - rc = check_mem_region(bar2, mem_len); + uint32_t bar2 = pci_resource_start(pinfo->pdev, 2); + uint32_t mem_len = pci_resource_len(pinfo->pdev, 2); + + dev_dbg(dev, "bar0:0x%x-0x%08x bar2:0x%x-0x%08x\n", + bar0, i2o_len, bar2, mem_len); + + /* bar-0 */ + rc = check_mem_region(bar0, i2o_len); if (rc) { - BCMLOG_ERR("No valid mem region...\n"); + printk(KERN_ERR "No valid mem region...\n"); return -ENOMEM; } - pinfo->addr = ioremap_nocache(bar2, mem_len); - if (!pinfo->addr) { - BCMLOG_ERR("Failed to remap mem region...\n"); + pinfo->i2o_addr = ioremap_nocache(bar0, i2o_len); + if (!pinfo->i2o_addr) { + printk(KERN_ERR "Failed to remap i2o region...\n"); return -ENOMEM; } - pinfo->pci_mem_start = bar2; - pinfo->pci_mem_len = mem_len; + pinfo->pci_i2o_start = bar0; + pinfo->pci_i2o_len = i2o_len; - rc = check_mem_region(bar0, i2o_len); + /* bar-2 */ + rc = check_mem_region(bar2, mem_len); if (rc) { - BCMLOG_ERR("No valid mem region...\n"); + printk(KERN_ERR "No valid mem region...\n"); return -ENOMEM; } - pinfo->i2o_addr = ioremap_nocache(bar0, i2o_len); - if (!pinfo->i2o_addr) { - BCMLOG_ERR("Failed to remap mem region...\n"); + pinfo->mem_addr = ioremap_nocache(bar2, mem_len); + if (!pinfo->mem_addr) { + printk(KERN_ERR "Failed to remap mem region...\n"); return -ENOMEM; } - pinfo->pci_i2o_start = bar0; - pinfo->pci_i2o_len = i2o_len; + pinfo->pci_mem_start = bar2; + pinfo->pci_mem_len = mem_len; + /* pdev */ rc = pci_request_regions(pinfo->pdev, pinfo->name); if (rc < 0) { - BCMLOG_ERR("Region request failed: %d\n", rc); + printk(KERN_ERR "Region request failed: %d\n", rc); return rc; } - BCMLOG(BCMLOG_SSTEP, "Mapped addr:0x%08lx i2o_addr:0x%08lx\n", - (unsigned long)pinfo->addr, (unsigned long)pinfo->i2o_addr); + dev_dbg(dev, "i2o_addr:0x%08lx Mapped addr:0x%08lx \n", + (unsigned long)pinfo->i2o_addr, (unsigned long)pinfo->mem_addr); return 0; } @@ -503,8 +587,8 @@ static void chd_pci_release_mem(struct c if (!pinfo) return; - if (pinfo->addr) - iounmap(pinfo->addr); + if (pinfo->mem_addr) + iounmap(pinfo->mem_addr); if (pinfo->i2o_addr) iounmap(pinfo->i2o_addr); @@ -516,17 +600,19 @@ static void chd_pci_release_mem(struct c static void chd_dec_pci_remove(struct pci_dev *pdev) { struct crystalhd_adp *pinfo; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; - pinfo = pci_get_drvdata(pdev); + dev_dbg(chddev(), "Entering %s\n", __func__); + + pinfo = (struct crystalhd_adp *) pci_get_drvdata(pdev); if (!pinfo) { - BCMLOG_ERR("could not get adp\n"); + dev_err(chddev(), "could not get adp\n"); return; } sts = crystalhd_delete_cmd_context(&pinfo->cmds); if (sts != BC_STS_SUCCESS) - BCMLOG_ERR("cmd delete :%d\n", sts); + dev_err(chddev(), "cmd delete :%d\n", sts); chd_dec_release_chdev(pinfo); @@ -542,26 +628,26 @@ static void chd_dec_pci_remove(struct pc static int chd_dec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *entry) { + struct device *dev = &pdev->dev; struct crystalhd_adp *pinfo; int rc; - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; - BCMLOG(BCMLOG_DBG, "PCI_INFO: Vendor:0x%04x Device:0x%04x s_vendor:0x%04x s_device: 0x%04x\n", - pdev->vendor, pdev->device, pdev->subsystem_vendor, - pdev->subsystem_device); + dev_info(dev, "Starting Device:0x%04x\n", pdev->device); pinfo = kzalloc(sizeof(struct crystalhd_adp), GFP_KERNEL); if (!pinfo) { - BCMLOG_ERR("Failed to allocate memory\n"); - return -ENOMEM; + dev_err(dev, "%s: Failed to allocate memory\n", __func__); + rc = -ENOMEM; + goto out; } pinfo->pdev = pdev; rc = pci_enable_device(pdev); if (rc) { - BCMLOG_ERR("Failed to enable PCI device\n"); - goto err; + dev_err(dev, "%s: Failed to enable PCI device\n", __func__); + goto free_priv; } snprintf(pinfo->name, sizeof(pinfo->name), "crystalhd_pci_e:%d:%d:%d", @@ -570,10 +656,9 @@ static int chd_dec_pci_probe(struct pci_ rc = chd_pci_reserve_mem(pinfo); if (rc) { - BCMLOG_ERR("Failed to setup memory regions.\n"); - pci_disable_device(pdev); - rc = -ENOMEM; - goto err; + dev_err(dev, "%s: Failed to set up memory regions.\n", + __func__); + goto disable_device; } pinfo->present = 1; @@ -583,13 +668,14 @@ static int chd_dec_pci_probe(struct pci_ spin_lock_init(&pinfo->lock); /* setup api stuff.. */ - chd_dec_init_chdev(pinfo); + rc = chd_dec_init_chdev(pinfo); + if (rc) + goto release_mem; + rc = chd_dec_enable_int(pinfo); if (rc) { - BCMLOG_ERR("_enable_int err:%d\n", rc); - pci_disable_device(pdev); - rc = -ENODEV; - goto err; + dev_err(dev, "%s: _enable_int err:%d\n", __func__, rc); + goto cleanup_chdev; } /* Set dma mask... */ @@ -600,18 +686,16 @@ static int chd_dec_pci_probe(struct pci_ pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); pinfo->dmabits = 32; } else { - BCMLOG_ERR("Unabled to setup DMA %d\n", rc); - pci_disable_device(pdev); + dev_err(dev, "%s: Unabled to setup DMA %d\n", __func__, rc); rc = -ENODEV; - goto err; + goto cleanup_int; } sts = crystalhd_setup_cmd_context(&pinfo->cmds, pinfo); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("cmd setup :%d\n", sts); - pci_disable_device(pdev); + dev_err(dev, "%s: cmd setup :%d\n", __func__, sts); rc = -ENODEV; - goto err; + goto cleanup_int; } pci_set_master(pdev); @@ -620,35 +704,44 @@ static int chd_dec_pci_probe(struct pci_ g_adp_info = pinfo; - return 0; - -err: - kfree(pinfo); +out: return rc; +cleanup_int: + chd_dec_disable_int(pinfo); +cleanup_chdev: + chd_dec_release_chdev(pinfo); +release_mem: + chd_pci_release_mem(pinfo); +disable_device: + pci_disable_device(pdev); +free_priv: + kfree(pdev); + goto out; } -#ifdef CONFIG_PM -static int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state) +int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state) { struct crystalhd_adp *adp; - struct crystalhd_ioctl_data *temp; - enum BC_STATUS sts = BC_STS_SUCCESS; + struct device *dev = &pdev->dev; + crystalhd_ioctl_data *temp; + BC_STATUS sts = BC_STS_SUCCESS; - adp = pci_get_drvdata(pdev); + adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); if (!adp) { - BCMLOG_ERR("could not get adp\n"); + dev_err(dev, "%s: could not get adp\n", __func__); return -ENODEV; } temp = chd_dec_alloc_iodata(adp, false); if (!temp) { - BCMLOG_ERR("could not get ioctl data\n"); + dev_err(dev, "could not get ioctl data\n"); return -ENODEV; } sts = crystalhd_suspend(&adp->cmds, temp); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("BCM70012 Suspend %d\n", sts); + dev_err(dev, "Crystal HD Suspend %d\n", sts); + chd_dec_free_iodata(adp, temp, false); return -ENODEV; } @@ -662,15 +755,16 @@ static int chd_dec_pci_suspend(struct pc return 0; } -static int chd_dec_pci_resume(struct pci_dev *pdev) +int chd_dec_pci_resume(struct pci_dev *pdev) { struct crystalhd_adp *adp; - enum BC_STATUS sts = BC_STS_SUCCESS; + struct device *dev = &pdev->dev; + BC_STATUS sts = BC_STS_SUCCESS; int rc; - adp = pci_get_drvdata(pdev); + adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); if (!adp) { - BCMLOG_ERR("could not get adp\n"); + dev_err(dev, "%s: could not get adp\n", __func__); return -ENODEV; } @@ -679,7 +773,7 @@ static int chd_dec_pci_resume(struct pci /* device's irq possibly is changed, driver should take care */ if (pci_enable_device(pdev)) { - BCMLOG_ERR("Failed to enable PCI device\n"); + dev_err(dev, "Failed to enable PCI device\n"); return 1; } @@ -687,59 +781,46 @@ static int chd_dec_pci_resume(struct pci rc = chd_dec_enable_int(adp); if (rc) { - BCMLOG_ERR("_enable_int err:%d\n", rc); + dev_err(dev, "_enable_int err:%d\n", rc); pci_disable_device(pdev); return -ENODEV; } sts = crystalhd_resume(&adp->cmds); if (sts != BC_STS_SUCCESS) { - BCMLOG_ERR("BCM70012 Resume %d\n", sts); + dev_err(dev, "Crystal HD Resume %d\n", sts); pci_disable_device(pdev); return -ENODEV; } return 0; } -#endif -static const struct pci_device_id chd_dec_pci_id_table[] = { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) +static DEFINE_PCI_DEVICE_TABLE(chd_dec_pci_id_table) = { { PCI_VDEVICE(BROADCOM, 0x1612), 8 }, + { PCI_VDEVICE(BROADCOM, 0x1615), 8 }, + { 0, }, +}; +#else +static struct pci_device_id chd_dec_pci_id_table[] = { +/* vendor, device, subvendor, subdevice, class, classmask, driver_data */ + { 0x14e4, 0x1612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, + { 0x14e4, 0x1615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, { 0, }, }; +#endif MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); -static struct pci_driver bc_chd_70012_driver = { - .name = "Broadcom 70012 Decoder", +static struct pci_driver bc_chd_driver = { + .name = "crystalhd", .probe = chd_dec_pci_probe, .remove = chd_dec_pci_remove, .id_table = chd_dec_pci_id_table, -#ifdef CONFIG_PM .suspend = chd_dec_pci_suspend, .resume = chd_dec_pci_resume -#endif }; -void chd_set_log_level(struct crystalhd_adp *adp, char *arg) -{ - if ((!arg) || (strlen(arg) < 3)) - g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA; - else if (!strncmp(arg, "sstep", 5)) - g_linklog_level = BCMLOG_INFO | BCMLOG_DATA | BCMLOG_DBG | - BCMLOG_SSTEP | BCMLOG_ERROR; - else if (!strncmp(arg, "info", 4)) - g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA | BCMLOG_INFO; - else if (!strncmp(arg, "debug", 5)) - g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA | BCMLOG_INFO | - BCMLOG_DBG; - else if (!strncmp(arg, "pball", 5)) - g_linklog_level = 0xFFFFFFFF & ~(BCMLOG_SPINLOCK); - else if (!strncmp(arg, "silent", 6)) - g_linklog_level = 0; - else - g_linklog_level = 0; -} - struct crystalhd_adp *chd_get_adp(void) { return g_adp_info; @@ -749,14 +830,14 @@ static int __init chd_dec_module_init(vo { int rc; - chd_set_log_level(NULL, "debug"); - BCMLOG(BCMLOG_DATA, "Loading crystalhd %d.%d.%d\n", + printk(KERN_DEBUG "Loading crystalhd v%d.%d.%d\n", crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); - rc = pci_register_driver(&bc_chd_70012_driver); + rc = pci_register_driver(&bc_chd_driver); if (rc < 0) - BCMLOG_ERR("Could not find any devices. err:%d\n", rc); + printk(KERN_ERR "%s: Could not find any devices. err:%d\n", + __func__, rc); return rc; } @@ -764,10 +845,10 @@ module_init(chd_dec_module_init); static void __exit chd_dec_module_cleanup(void) { - BCMLOG(BCMLOG_DATA, "unloading crystalhd %d.%d.%d\n", + printk(KERN_DEBUG "Unloading crystalhd %d.%d.%d\n", crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); - pci_unregister_driver(&bc_chd_70012_driver); + pci_unregister_driver(&bc_chd_driver); } module_exit(chd_dec_module_cleanup); @@ -775,4 +856,4 @@ MODULE_AUTHOR("Naren Sankar "); MODULE_DESCRIPTION(CRYSTAL_HD_NAME); MODULE_LICENSE("GPL"); -MODULE_ALIAS("bcm70012"); +MODULE_ALIAS("crystalhd"); --- crystalhd~/crystalhd_lnx.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_lnx.h 2015-04-06 20:14:53.000000000 +0300 @@ -1,7 +1,7 @@ /*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * - * Name: crystalhd_lnx . h + * Name: crystalhd_lnx . c * * Description: * BCM70012 Linux driver @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -44,11 +45,12 @@ #include #include #include +/*#include */ #include -#include "crystalhd.h" +#include "crystalhd_cmds.h" -#define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder (BCM70012) Driver" +#define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder Driver" /* OS specific PCI information structure and adapter information. */ struct crystalhd_adp { @@ -57,12 +59,12 @@ struct crystalhd_adp { struct pci_dev *pdev; unsigned long pci_mem_start; - uint32_t pci_mem_len; - void *addr; + uint32_t pci_mem_len; + void *mem_addr; unsigned long pci_i2o_start; - uint32_t pci_i2o_len; - void *i2o_addr; + uint32_t pci_i2o_len; + void *i2o_addr; unsigned int drv_data; unsigned int dmabits; /* 32 | 64 */ @@ -73,11 +75,11 @@ struct crystalhd_adp { spinlock_t lock; /* API Related */ - int chd_dec_major; + int chd_dec_major; unsigned int cfg_users; - struct crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ - struct crystalhd_elem *elem_pool_head; /* Queue element pool */ + crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ + struct crystalhd_elem *elem_pool_head; /* Queue element pool */ struct crystalhd_cmd cmds; @@ -87,7 +89,6 @@ struct crystalhd_adp { struct crystalhd_adp *chd_get_adp(void); -void chd_set_log_level(struct crystalhd_adp *adp, char *arg); +struct device *chddev(void); #endif - --- crystalhd~/crystalhd_misc.c 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_misc.c 2011-03-14 23:02:54.000000000 +0300 @@ -24,31 +24,15 @@ * along with this driver. If not, see . **********************************************************************/ -#include "crystalhd.h" +#include +#include -#include +#include "crystalhd_lnx.h" +#include "crystalhd_misc.h" -uint32_t g_linklog_level; - -static inline uint32_t crystalhd_dram_rd(struct crystalhd_adp *adp, - uint32_t mem_off) -{ - crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); - return bc_dec_reg_rd(adp, (0x00380000 | (mem_off & 0x0007FFFF))); -} - -static inline void crystalhd_dram_wr(struct crystalhd_adp *adp, - uint32_t mem_off, uint32_t val) -{ - crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); - bc_dec_reg_wr(adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); -} - -static inline enum BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, - uint32_t start_off, uint32_t cnt) -{ - return BC_STS_SUCCESS; -} +/* Some HW specific code defines */ +extern uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *); +extern uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void *); static struct crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp) { @@ -56,7 +40,7 @@ static struct crystalhd_dio_req *crystal struct crystalhd_dio_req *temp = NULL; if (!adp) { - BCMLOG_ERR("Invalid Arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return temp; } @@ -69,8 +53,7 @@ static struct crystalhd_dio_req *crystal return temp; } -static void crystalhd_free_dio(struct crystalhd_adp *adp, - struct crystalhd_dio_req *dio) +static void crystalhd_free_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) { unsigned long flags = 0; @@ -92,19 +75,22 @@ static struct crystalhd_elem *crystalhd_ struct crystalhd_elem *temp = NULL; if (!adp) + { + printk(KERN_ERR "%s: Invalid args\n", __func__); return temp; + } spin_lock_irqsave(&adp->lock, flags); temp = adp->elem_pool_head; if (temp) { adp->elem_pool_head = adp->elem_pool_head->flink; memset(temp, 0, sizeof(*temp)); } + spin_unlock_irqrestore(&adp->lock, flags); return temp; } -static void crystalhd_free_elem(struct crystalhd_adp *adp, - struct crystalhd_elem *elem) +static void crystalhd_free_elem(struct crystalhd_adp *adp, struct crystalhd_elem *elem) { unsigned long flags = 0; @@ -119,168 +105,28 @@ static void crystalhd_free_elem(struct c static inline void crystalhd_set_sg(struct scatterlist *sg, struct page *page, unsigned int len, unsigned int offset) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) sg_set_page(sg, page, len, offset); +#else + sg->page = page; + sg->offset = offset; + sg->length = len; +#endif #ifdef CONFIG_X86_64 sg->dma_length = len; #endif } -static inline void crystalhd_init_sg(struct scatterlist *sg, - unsigned int entries) +static inline void crystalhd_init_sg(struct scatterlist *sg, unsigned int entries) { /* http://lkml.org/lkml/2007/11/27/68 */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) sg_init_table(sg, entries); +#endif } /*========================== Extern ========================================*/ /** - * bc_dec_reg_rd - Read 7412's device register. - * @adp: Adapter instance - * @reg_off: Register offset. - * - * Return: - * 32bit value read - * - * 7412's device register read routine. This interface use - * 7412's device access range mapped from BAR-2 (4M) of PCIe - * configuration space. - */ -uint32_t bc_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) -{ - if (!adp || (reg_off > adp->pci_mem_len)) { - BCMLOG_ERR("dec_rd_reg_off outof range: 0x%08x\n", reg_off); - return 0; - } - - return readl(adp->addr + reg_off); -} - -/** - * bc_dec_reg_wr - Write 7412's device register - * @adp: Adapter instance - * @reg_off: Register offset. - * @val: Dword value to be written. - * - * Return: - * none. - * - * 7412's device register write routine. This interface use - * 7412's device access range mapped from BAR-2 (4M) of PCIe - * configuration space. - */ -void bc_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) -{ - if (!adp || (reg_off > adp->pci_mem_len)) { - BCMLOG_ERR("dec_wr_reg_off outof range: 0x%08x\n", reg_off); - return; - } - writel(val, adp->addr + reg_off); - udelay(8); -} - -/** - * crystalhd_reg_rd - Read Link's device register. - * @adp: Adapter instance - * @reg_off: Register offset. - * - * Return: - * 32bit value read - * - * Link device register read routine. This interface use - * Link's device access range mapped from BAR-1 (64K) of PCIe - * configuration space. - * - */ -uint32_t crystalhd_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) -{ - if (!adp || (reg_off > adp->pci_i2o_len)) { - BCMLOG_ERR("link_rd_reg_off outof range: 0x%08x\n", reg_off); - return 0; - } - return readl(adp->i2o_addr + reg_off); -} - -/** - * crystalhd_reg_wr - Write Link's device register - * @adp: Adapter instance - * @reg_off: Register offset. - * @val: Dword value to be written. - * - * Return: - * none. - * - * Link device register write routine. This interface use - * Link's device access range mapped from BAR-1 (64K) of PCIe - * configuration space. - * - */ -void crystalhd_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, - uint32_t val) -{ - if (!adp || (reg_off > adp->pci_i2o_len)) { - BCMLOG_ERR("link_wr_reg_off outof range: 0x%08x\n", reg_off); - return; - } - writel(val, adp->i2o_addr + reg_off); -} - -/** - * crystalhd_mem_rd - Read data from 7412's DRAM area. - * @adp: Adapter instance - * @start_off: Start offset. - * @dw_cnt: Count in dwords. - * @rd_buff: Buffer to copy the data from dram. - * - * Return: - * Status. - * - * 7412's Dram read routine. - */ -enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *adp, uint32_t start_off, - uint32_t dw_cnt, uint32_t *rd_buff) -{ - uint32_t ix = 0; - - if (!adp || !rd_buff || - (bc_chk_dram_range(adp, start_off, dw_cnt) != BC_STS_SUCCESS)) { - BCMLOG_ERR("Invalid arg\n"); - return BC_STS_INV_ARG; - } - for (ix = 0; ix < dw_cnt; ix++) - rd_buff[ix] = crystalhd_dram_rd(adp, (start_off + (ix * 4))); - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_mem_wr - Write data to 7412's DRAM area. - * @adp: Adapter instance - * @start_off: Start offset. - * @dw_cnt: Count in dwords. - * @wr_buff: Data Buffer to be written. - * - * Return: - * Status. - * - * 7412's Dram write routine. - */ -enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *adp, uint32_t start_off, - uint32_t dw_cnt, uint32_t *wr_buff) -{ - uint32_t ix = 0; - - if (!adp || !wr_buff || - (bc_chk_dram_range(adp, start_off, dw_cnt) != BC_STS_SUCCESS)) { - BCMLOG_ERR("Invalid arg\n"); - return BC_STS_INV_ARG; - } - - for (ix = 0; ix < dw_cnt; ix++) - crystalhd_dram_wr(adp, (start_off + (ix * 4)), wr_buff[ix]); - - return BC_STS_SUCCESS; -} -/** * crystalhd_pci_cfg_rd - PCIe config read * @adp: Adapter instance * @off: PCI config space offset. @@ -290,16 +136,16 @@ enum BC_STATUS crystalhd_mem_wr(struct c * Return: * Status. * - * Get value from Link's PCIe config space. + * Get value from PCIe config space. */ -enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off, +BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off, uint32_t len, uint32_t *val) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; int rc = 0; if (!adp || !val) { - BCMLOG_ERR("Invalid arg\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } @@ -316,8 +162,8 @@ enum BC_STATUS crystalhd_pci_cfg_rd(stru default: rc = -EINVAL; sts = BC_STS_INV_ARG; - BCMLOG_ERR("Invalid len:%d\n", len); - } + dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); + }; if (rc && (sts == BC_STS_SUCCESS)) sts = BC_STS_ERROR; @@ -337,14 +183,14 @@ enum BC_STATUS crystalhd_pci_cfg_rd(stru * * Set value to Link's PCIe config space. */ -enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off, +BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off, uint32_t len, uint32_t val) { - enum BC_STATUS sts = BC_STS_SUCCESS; + BC_STATUS sts = BC_STS_SUCCESS; int rc = 0; if (!adp || !val) { - BCMLOG_ERR("Invalid arg\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } @@ -361,8 +207,8 @@ enum BC_STATUS crystalhd_pci_cfg_wr(stru default: rc = -EINVAL; sts = BC_STS_INV_ARG; - BCMLOG_ERR("Invalid len:%d\n", len); - } + dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); + }; if (rc && (sts == BC_STS_SUCCESS)) sts = BC_STS_ERROR; @@ -389,7 +235,7 @@ void *bc_kern_dma_alloc(struct crystalhd void *temp = NULL; if (!adp || !sz || !phy_addr) { - BCMLOG_ERR("Invalid Arg..\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return temp; } @@ -415,7 +261,7 @@ void bc_kern_dma_free(struct crystalhd_a dma_addr_t phy_addr) { if (!adp || !ka || !sz || !phy_addr) { - BCMLOG_ERR("Invalid Arg..\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return; } @@ -435,14 +281,14 @@ void bc_kern_dma_free(struct crystalhd_a * Initialize Generic DIO queue to hold any data. Callback * will be used to free elements while deleting the queue. */ -enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, +BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq **dioq_hnd, crystalhd_data_free_cb cb, void *cbctx) { struct crystalhd_dioq *dioq = NULL; if (!adp || !dioq_hnd) { - BCMLOG_ERR("Invalid arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } @@ -476,8 +322,7 @@ enum BC_STATUS crystalhd_create_dioq(str * by calling the call back provided during creation. * */ -void crystalhd_delete_dioq(struct crystalhd_adp *adp, - struct crystalhd_dioq *dioq) +void crystalhd_delete_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq *dioq) { void *temp; @@ -505,20 +350,20 @@ void crystalhd_delete_dioq(struct crysta * * Insert new element to Q tail. */ -enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, +BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag) { unsigned long flags = 0; struct crystalhd_elem *tmp; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !data) { - BCMLOG_ERR("Invalid arg!!\n"); + dev_err(chddev(), "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } tmp = crystalhd_alloc_elem(ioq->adp); if (!tmp) { - BCMLOG_ERR("No free elements.\n"); + dev_err(chddev(), "%s: No free elements.\n", __func__); return BC_STS_INSUFF_RES; } @@ -555,7 +400,11 @@ void *crystalhd_dioq_fetch(struct crysta void *data = NULL; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { - BCMLOG_ERR("Invalid arg!!\n"); + dev_err(chddev(), "%s: Invalid arg\n", __func__); + if(!ioq) + dev_err(chddev(), "ioq not initialized\n"); + else + dev_err(chddev(), "ioq invalid signature\n"); return data; } @@ -593,7 +442,7 @@ void *crystalhd_dioq_find_and_fetch(stru void *data = NULL; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { - BCMLOG_ERR("Invalid arg!!\n"); + dev_err(chddev(), "%s: Invalid arg\n", __func__); return data; } @@ -630,39 +479,88 @@ void *crystalhd_dioq_find_and_fetch(stru * Return element from head if Q is not empty. Wait for new element * if Q is empty for Timeout seconds. */ -void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs, - uint32_t *sig_pend) +void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend) { + struct device *dev = chddev(); unsigned long flags = 0; - int rc = 0, count; - void *tmp = NULL; + int rc = 0; + + struct crystalhd_rx_dma_pkt *r_pkt = NULL; + struct crystalhd_dioq *ioq = hw->rx_rdyq; + uint32_t picYcomp = 0; + + unsigned long fetchTimeout = jiffies + msecs_to_jiffies(to_secs * 1000); if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !to_secs || !sig_pend) { - BCMLOG_ERR("Invalid arg!!\n"); - return tmp; + dev_err(dev, "%s: Invalid arg\n", __func__); + return r_pkt; } - count = to_secs; spin_lock_irqsave(&ioq->lock, flags); - while ((ioq->count == 0) && count) { - spin_unlock_irqrestore(&ioq->lock, flags); - - crystalhd_wait_on_event(&ioq->event, - (ioq->count > 0), 1000, rc, 0); + while (!time_after_eq(jiffies, fetchTimeout)) { + if(ioq->count == 0) { + spin_unlock_irqrestore(&ioq->lock, flags); + crystalhd_wait_on_event(&ioq->event, (ioq->count > 0), + 250, rc, false); + } + else + spin_unlock_irqrestore(&ioq->lock, flags); if (rc == 0) { - goto out; + /* Found a packet. Check if it is a repeated picture or not */ + /* Drop the picture if it is a repeated picture */ + /* Lock against checks from get status calls */ + if(down_interruptible(&hw->fetch_sem)) + goto sem_error; + r_pkt = crystalhd_dioq_fetch(ioq); + /* If format change packet, then return with out checking anything */ + if (r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) + goto sem_rel_return; + if (hw->adp->pdev->device == BC_PCI_DEVID_LINK) { + picYcomp = link_GetRptDropParam(hw, hw->PICHeight, hw->PICWidth, (void *)r_pkt); + } + else { + /* For Flea, we don't have the width and height handy since they */ + /* come in the PIB in the picture, so this function will also */ + /* populate the width and height */ + picYcomp = flea_GetRptDropParam(hw, (void *)r_pkt); + /* For flea it is the above function that indicated format change */ + if(r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) + goto sem_rel_return; + } + if(!picYcomp || (picYcomp == hw->LastPicNo) || + (picYcomp == hw->LastTwoPicNo)) { + /*Discard picture */ + if(picYcomp != 0) { + hw->LastTwoPicNo = hw->LastPicNo; + hw->LastPicNo = picYcomp; + } + crystalhd_dioq_add(hw->rx_freeq, r_pkt, false, r_pkt->pkt_tag); + r_pkt = NULL; + up(&hw->fetch_sem); + } else { + if(hw->adp->pdev->device == BC_PCI_DEVID_LINK) { + if((picYcomp - hw->LastPicNo) > 1) { + dev_info(dev, "MISSING %u PICTURES\n", (picYcomp - hw->LastPicNo)); + } + } + hw->LastTwoPicNo = hw->LastPicNo; + hw->LastPicNo = picYcomp; + goto sem_rel_return; + } } else if (rc == -EINTR) { - BCMLOG(BCMLOG_INFO, "Cancelling fetch wait\n"); *sig_pend = 1; - return tmp; + return r_pkt; } spin_lock_irqsave(&ioq->lock, flags); - count--; } + dev_info(dev, "FETCH TIMEOUT\n"); spin_unlock_irqrestore(&ioq->lock, flags); - -out: - return crystalhd_dioq_fetch(ioq); + return r_pkt; +sem_error: + return NULL; +sem_rel_return: + up(&hw->fetch_sem); + return r_pkt; } /** @@ -681,37 +579,40 @@ out: * This routine maps user address and lock pages for DMA. * */ -enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, +BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, uint32_t ubuff_sz, uint32_t uv_offset, bool en_422mode, bool dir_tx, struct crystalhd_dio_req **dio_hnd) { + struct device *dev; struct crystalhd_dio_req *dio; - /* FIXME: jarod: should some of these - unsigned longs be uint32_t or uintptr_t? */ - unsigned long start = 0, end = 0, uaddr = 0, count = 0; - unsigned long spsz = 0, uv_start = 0; + uint32_t start = 0, end = 0, count = 0; + uint32_t spsz = 0; + unsigned long uaddr = 0, uv_start = 0; int i = 0, rw = 0, res = 0, nr_pages = 0, skip_fb_sg = 0; if (!adp || !ubuff || !ubuff_sz || !dio_hnd) { - BCMLOG_ERR("Invalid arg\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } + + dev = &adp->pdev->dev; + /* Compute pages */ uaddr = (unsigned long)ubuff; - count = (unsigned long)ubuff_sz; + count = ubuff_sz; end = (uaddr + count + PAGE_SIZE - 1) >> PAGE_SHIFT; start = uaddr >> PAGE_SHIFT; nr_pages = end - start; if (!count || ((uaddr + count) < uaddr)) { - BCMLOG_ERR("User addr overflow!!\n"); + dev_err(dev, "User addr overflow!!\n"); return BC_STS_INV_ARG; } dio = crystalhd_alloc_dio(adp); if (!dio) { - BCMLOG_ERR("dio pool empty..\n"); + dev_err(dev, "dio pool empty..\n"); return BC_STS_INSUFF_RES; } @@ -724,17 +625,16 @@ enum BC_STATUS crystalhd_map_dio(struct } if (nr_pages > dio->max_pages) { - BCMLOG_ERR("max_pages(%d) exceeded(%d)!!\n", - dio->max_pages, nr_pages); + dev_err(dev, "max_pages(%d) exceeded(%d)!!\n", + dio->max_pages, nr_pages); crystalhd_unmap_dio(adp, dio); return BC_STS_INSUFF_RES; } if (uv_offset) { - uv_start = (uaddr + (unsigned long)uv_offset) >> PAGE_SHIFT; + uv_start = (uaddr + uv_offset) >> PAGE_SHIFT; dio->uinfo.uv_sg_ix = uv_start - start; - dio->uinfo.uv_sg_off = ((uaddr + (unsigned long)uv_offset) & - ~PAGE_MASK); + dio->uinfo.uv_sg_off = ((uaddr + uv_offset) & ~PAGE_MASK); } dio->fb_size = ubuff_sz & 0x03; @@ -743,9 +643,9 @@ enum BC_STATUS crystalhd_map_dio(struct (void *)(uaddr + count - dio->fb_size), dio->fb_size); if (res) { - BCMLOG_ERR("failed %d to copy %u fill bytes from %p\n", - res, dio->fb_size, - (void *)(uaddr + count-dio->fb_size)); + dev_err(dev, "failed %d to copy %u fill bytes from %p\n", + res, dio->fb_size, + (void *)(uaddr + count-dio->fb_size)); crystalhd_unmap_dio(adp, dio); return BC_STS_INSUFF_RES; } @@ -759,7 +659,7 @@ enum BC_STATUS crystalhd_map_dio(struct /* Save for release..*/ dio->sig = crystalhd_dio_locked; if (res < nr_pages) { - BCMLOG_ERR("get pages failed: %d-%d\n", nr_pages, res); + dev_err(dev, "get pages failed: %d-%d\n", nr_pages, res); dio->page_cnt = res; crystalhd_unmap_dio(adp, dio); return BC_STS_ERROR; @@ -772,9 +672,11 @@ enum BC_STATUS crystalhd_map_dio(struct if (nr_pages > 1) { dio->sg[0].length = PAGE_SIZE - dio->sg[0].offset; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) #ifdef CONFIG_X86_64 dio->sg[0].dma_length = dio->sg[0].length; #endif +#endif count -= dio->sg[0].length; for (i = 1; i < nr_pages; i++) { if (count < 4) { @@ -794,14 +696,16 @@ enum BC_STATUS crystalhd_map_dio(struct } else { dio->sg[0].length = count - dio->fb_size; } +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) #ifdef CONFIG_X86_64 dio->sg[0].dma_length = dio->sg[0].length; #endif +#endif } dio->sg_cnt = pci_map_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); if (dio->sg_cnt <= 0) { - BCMLOG_ERR("sg map %d-%d\n", dio->sg_cnt, dio->page_cnt); + dev_err(dev, "sg map %d-%d\n", dio->sg_cnt, dio->page_cnt); crystalhd_unmap_dio(adp, dio); return BC_STS_ERROR; } @@ -830,14 +734,13 @@ enum BC_STATUS crystalhd_map_dio(struct * * This routine is to unmap the user buffer pages. */ -enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, - struct crystalhd_dio_req *dio) +BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) { struct page *page = NULL; int j = 0; if (!adp || !dio) { - BCMLOG_ERR("Invalid arg\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } @@ -853,8 +756,7 @@ enum BC_STATUS crystalhd_unmap_dio(struc } } if (dio->sig == crystalhd_dio_sg_mapped) - pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, - dio->direction); + pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); crystalhd_free_dio(adp, dio); @@ -874,20 +776,23 @@ enum BC_STATUS crystalhd_unmap_dio(struc */ int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages) { + struct device *dev; uint32_t asz = 0, i = 0; uint8_t *temp; struct crystalhd_dio_req *dio; if (!adp || !max_pages) { - BCMLOG_ERR("Invalid Arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } + dev = &adp->pdev->dev; + /* Get dma memory for fill byte handling..*/ adp->fill_byte_pool = pci_pool_create("crystalhd_fbyte", adp->pdev, 8, 8, 0); if (!adp->fill_byte_pool) { - BCMLOG_ERR("failed to create fill byte pool\n"); + dev_err(dev, "failed to create fill byte pool\n"); return -ENOMEM; } @@ -895,13 +800,13 @@ int crystalhd_create_dio_pool(struct cry asz = (sizeof(*dio->pages) * max_pages) + (sizeof(*dio->sg) * max_pages) + sizeof(*dio); - BCMLOG(BCMLOG_DBG, "Initializing Dio pool %d %d %x %p\n", - BC_LINK_SG_POOL_SZ, max_pages, asz, adp->fill_byte_pool); + dev_dbg(dev, "Initializing Dio pool %d %d %x %p\n", + BC_LINK_SG_POOL_SZ, max_pages, asz, adp->fill_byte_pool); for (i = 0; i < BC_LINK_SG_POOL_SZ; i++) { temp = kzalloc(asz, GFP_KERNEL); if ((temp) == NULL) { - BCMLOG_ERR("Failed to alloc %d mem\n", asz); + dev_err(dev, "Failed to alloc %d mem\n", asz); return -ENOMEM; } @@ -914,7 +819,7 @@ int crystalhd_create_dio_pool(struct cry dio->fb_va = pci_pool_alloc(adp->fill_byte_pool, GFP_KERNEL, &dio->fb_pa); if (!dio->fb_va) { - BCMLOG_ERR("fill byte alloc failed.\n"); + dev_err(dev, "fill byte alloc failed.\n"); return -ENOMEM; } @@ -939,7 +844,7 @@ void crystalhd_destroy_dio_pool(struct c int count = 0; if (!adp) { - BCMLOG_ERR("Invalid Arg!!\n"); + printk(KERN_ERR "%s: Invalid arg\n", __func__); return; } @@ -959,7 +864,7 @@ void crystalhd_destroy_dio_pool(struct c adp->fill_byte_pool = NULL; } - BCMLOG(BCMLOG_DBG, "Released dio pool %d\n", count); + dev_dbg(&adp->pdev->dev, "Released dio pool %d\n", count); } /** @@ -985,12 +890,12 @@ int crystalhd_create_elem_pool(struct cr for (i = 0; i < pool_size; i++) { temp = kzalloc(sizeof(*temp), GFP_KERNEL); if (!temp) { - BCMLOG_ERR("kalloc failed\n"); + dev_err(&adp->pdev->dev, "kzalloc failed\n"); return -ENOMEM; } crystalhd_free_elem(adp, temp); } - BCMLOG(BCMLOG_DBG, "allocated %d elem\n", pool_size); + dev_dbg(&adp->pdev->dev, "allocated %d elem\n", pool_size); return 0; } @@ -1019,25 +924,26 @@ void crystalhd_delete_elem_pool(struct c } } while (temp); - BCMLOG(BCMLOG_DBG, "released %d elem\n", dbg_cnt); + dev_dbg(&adp->pdev->dev, "released %d elem\n", dbg_cnt); } /*================ Debug support routines.. ================================*/ void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount) { + struct device *dev = chddev(); uint32_t i, k = 1; for (i = 0; i < dwcount; i++) { if (k == 1) - BCMLOG(BCMLOG_DATA, "0x%08X : ", off); + dev_dbg(dev, "0x%08X : ", off); - BCMLOG(BCMLOG_DATA, " 0x%08X ", *((uint32_t *)buff)); + dev_dbg(dev, " 0x%08X ", *((uint32_t *)buff)); buff += sizeof(uint32_t); off += sizeof(uint32_t); k++; if ((i == dwcount - 1) || (k > 4)) { - BCMLOG(BCMLOG_DATA, "\n"); + dev_dbg(dev, "\n"); k = 1; } } --- crystalhd~/crystalhd_misc.h 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/crystalhd_misc.h 2015-04-06 20:15:04.000000000 +0300 @@ -28,8 +28,6 @@ #ifndef _CRYSTALHD_MISC_H_ #define _CRYSTALHD_MISC_H_ -#include "crystalhd.h" - #include #include #include @@ -37,10 +35,12 @@ #include #include #include +/*#include */ #include "bc_dts_glob_lnx.h" +#include "crystalhd_hw.h" -/* Global log level variable defined in crystal_misc.c file */ -extern uint32_t g_linklog_level; +/* forward declare */ +struct crystalhd_hw; /* Global element pool for all Queue management. * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. @@ -55,7 +55,7 @@ extern uint32_t g_linklog_level; /* Scatter Gather memory pool size for Tx and Rx */ #define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) -enum crystalhd_dio_sig { +enum _crystalhd_dio_sig { crystalhd_dio_inv = 0, crystalhd_dio_locked, crystalhd_dio_sg_mapped, @@ -78,27 +78,28 @@ struct crystalhd_dio_user_info { }; struct crystalhd_dio_req { - uint32_t sig; - uint32_t max_pages; - struct page **pages; - struct scatterlist *sg; - int sg_cnt; - int page_cnt; - int direction; + uint32_t sig; + uint32_t max_pages; + struct page **pages; + struct scatterlist *sg; + int sg_cnt; + int page_cnt; + int direction; struct crystalhd_dio_user_info uinfo; - void *fb_va; - uint32_t fb_size; - dma_addr_t fb_pa; - struct crystalhd_dio_req *next; + void *fb_va; + uint32_t fb_size; + dma_addr_t fb_pa; + void *pib_va; /* pointer to temporary buffer to extract metadata */ + struct crystalhd_dio_req *next; }; #define BC_LINK_DIOQ_SIG (0x09223280) struct crystalhd_elem { - struct crystalhd_elem *flink; - struct crystalhd_elem *blink; - void *data; - uint32_t tag; + struct crystalhd_elem *flink; + struct crystalhd_elem *blink; + void *data; + uint32_t tag; }; typedef void (*crystalhd_data_free_cb)(void *context, void *data); @@ -106,8 +107,8 @@ typedef void (*crystalhd_data_free_cb)(v struct crystalhd_dioq { uint32_t sig; struct crystalhd_adp *adp; - struct crystalhd_elem *head; - struct crystalhd_elem *tail; + struct crystalhd_elem *head; + struct crystalhd_elem *tail; uint32_t count; spinlock_t lock; wait_queue_head_t event; @@ -116,27 +117,11 @@ struct crystalhd_dioq { }; typedef void (*hw_comp_callback)(struct crystalhd_dio_req *, - wait_queue_head_t *event, enum BC_STATUS sts); + wait_queue_head_t *event, BC_STATUS sts); -/*========= Decoder (7412) register access routines.================= */ -uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t); -void bc_dec_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); - -/*========= Link (70012) register access routines.. =================*/ -uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t); -void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); - -/*========= Decoder (7412) memory access routines..=================*/ -enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, - uint32_t, uint32_t, uint32_t *); -enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, - uint32_t, uint32_t, uint32_t *); - -/*==========Link (70012) PCIe Config access routines.================*/ -enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, - uint32_t, uint32_t, uint32_t *); -enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, - uint32_t, uint32_t, uint32_t); +/*========== PCIe Config access routines.================*/ +BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); +BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); /*========= Linux Kernel Interface routines. ======================= */ void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); @@ -147,11 +132,11 @@ void bc_kern_dma_free(struct crystalhd_a #define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ do { \ DECLARE_WAITQUEUE(entry, current); \ - unsigned long end = jiffies + ((timeout * HZ) / 1000); \ + unsigned long end = jiffies + msecs_to_jiffies(timeout); \ ret = 0; \ add_wait_queue(ev, &entry); \ - for (;;) { \ - __set_current_state(TASK_INTERRUPTIBLE); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ if (condition) { \ break; \ } \ @@ -165,68 +150,34 @@ do { \ break; \ } \ } \ - __set_current_state(TASK_RUNNING); \ + set_current_state(TASK_RUNNING); \ remove_wait_queue(ev, &entry); \ } while (0) /*================ Direct IO mapping routines ==================*/ extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); -extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, - uint32_t, uint32_t, bool, bool, struct crystalhd_dio_req**); +extern BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, + uint32_t, bool, bool, struct crystalhd_dio_req**); -extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, - struct crystalhd_dio_req*); -#define crystalhd_get_sgle_paddr(_dio, _ix) (sg_dma_address(&_dio->sg[_ix])) -#define crystalhd_get_sgle_len(_dio, _ix) (sg_dma_len(&_dio->sg[_ix])) +extern BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, struct crystalhd_dio_req*); +#define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) +#define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) /*================ General Purpose Queues ==================*/ -extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, - struct crystalhd_dioq **, crystalhd_data_free_cb , void *); -extern void crystalhd_delete_dioq(struct crystalhd_adp *, - struct crystalhd_dioq *); -extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, - void *data, bool wake, uint32_t tag); +extern BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, struct crystalhd_dioq **, crystalhd_data_free_cb , void *); +extern void crystalhd_delete_dioq(struct crystalhd_adp *, struct crystalhd_dioq *); +extern BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag); extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq); -extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, - uint32_t tag); -extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, - uint32_t to_secs, uint32_t *sig_pend); +extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag); +extern void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend); #define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); - /*================ Debug routines/macros .. ================================*/ -extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, - uint32_t dwcount); - -enum _chd_log_levels { - BCMLOG_ERROR = 0x80000000, /* Don't disable this option */ - BCMLOG_DATA = 0x40000000, /* Data, enable by default */ - BCMLOG_SPINLOCK = 0x20000000, /* Special case for Spin locks*/ - - /* Following are allowed only in debug mode */ - BCMLOG_INFO = 0x00000001, /* Generic informational */ - BCMLOG_DBG = 0x00000002, /* First level Debug info */ - BCMLOG_SSTEP = 0x00000004, /* Stepping information */ -}; - - -#define BCMLOG(trace, fmt, args...) \ -do { \ - if (g_linklog_level & trace) \ - printk(fmt, ##args); \ -} while (0) - - -#define BCMLOG_ERR(fmt, args...) \ -do { \ - if (g_linklog_level & BCMLOG_ERROR) \ - printk(KERN_ERR "*ERR*:%s:%d: "fmt, \ - __FILE__, __LINE__, ##args); \ -} while (0) +extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); #endif --- crystalhd~/DriverFwShare.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/DriverFwShare.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,95 @@ +#ifndef _DRIVER_FW_SHARE_ +#define _DRIVER_FW_SHARE_ + +#ifndef USE_MULTI_DECODE_DEFINES +#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 /*Original single Decode Offset*/ +#else +#if 0 +#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x200 /*New offset that we plan to use eventually*/ +#endif +#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 /*This is just for testing..remove this once tested */ +#endif + + +/* + * The TX address does not change between the + * single decode and multiple decode. + */ +#define TX_BUFF_UPDATE_ADDR 0x300 /*This is relative to BORCH */ + +typedef +struct +_PIC_DELIVERY_HOST_INFO_ +{ +/* +-- The list ping-pong code is already there in the driver +-- to save from re-inventing the code, the driver will indicate +-- to firmware on which list the command should be posted. + */ + unsigned int ListIndex; + unsigned int HostDescMemLowAddr_Y; + unsigned int HostDescMemHighAddr_Y; + unsigned int HostDescMemLowAddr_UV; + unsigned int HostDescMemHighAddr_UV; + unsigned int RxSeqNumber; + unsigned int ChannelID; + unsigned int Reserved[1]; +}PIC_DELIVERY_HOST_INFO, +*PPIC_DELIVERY_HOST_INFO; + +/* +-- We write the driver's FLL to this memory location. +-- This is the array for FLL of all the channels. +*/ +#define HOST_TO_FW_FLL_ADDR (HOST_TO_FW_PIC_DEL_INFO_ADDR + sizeof(PIC_DELIVERY_HOST_INFO)) + + +typedef enum _DRIVER_FW_FLAGS_{ + DFW_FLAGS_CLEAR =0, + DFW_FLAGS_TX_ABORT =BC_BIT(0), /*Firmware is stopped and will not give anymore buffers. */ + DFW_FLAGS_WRAP =BC_BIT(1) /*Instruct the Firmware to WRAP the input buffer pointer */ +}DRIVER_FW_FLAGS; + +typedef struct +_TX_INPUT_BUFFER_INFO_ +{ + unsigned int DramBuffAdd; /* Address of the DRAM buffer where the data can be pushed*/ + unsigned int DramBuffSzInBytes; /* Size of the available DRAM buffer, in bytes*/ + unsigned int HostXferSzInBytes; /* Actual Transfer Done By Host, In Bytes*/ + unsigned int Flags; /* DRIVER_FW_FLAGS Written By Firmware to handle Stop of TX*/ + unsigned int SeqNum; /* Sequence number of the tranfer that is done. Read-Modify-Write*/ + unsigned int ChannelID; /* To which Channel this buffer belongs to*/ + unsigned int Reserved[2]; +}TX_INPUT_BUFFER_INFO, +*PTX_INPUT_BUFFER_INFO; + + +/* +-- Out of band firmware handshake. +===================================== +-- The driver writes the SCRATCH-8 register with a Error code. +-- The driver then writes a mailbox register with 0x01. +-- The driver then polls for the ACK. This ack is if the value of the SCRATCH-8 becomes zero. +*/ + +#define OOB_ERR_CODE_BASE 70015 +typedef enum _OUT_OF_BAND_ERR_CODE_ +{ + OOB_INVALID = 0, + OOB_CODE_ACK = OOB_ERR_CODE_BASE, + OOB_CODE_STOPRX = OOB_ERR_CODE_BASE + 1, +}OUT_OF_BAND_ERR_CODE; + + +#define OOB_CMD_RESPONSE_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 +#define OOB_PCI_TO_ARM_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 +#define TX_BUFFER_AVAILABLE_INTR BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 +#define HEART_BEAT_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 +#define HEART_BEAT_POLL_CNT 5 + + +#define FLEA_WORK_AROUND_SIG 0xF1EA +#define RX_PIC_Q_STS_WRKARND BC_BIT(0) +#define RX_DRAM_WRITE_WRKARND BC_BIT(1) +#define RX_MBOX_WRITE_WRKARND BC_BIT(2) +#endif --- crystalhd~/FleaDefs.h 1970-01-01 03:00:00.000000000 +0300 +++ crystalhd/FleaDefs.h 2011-03-14 23:02:54.000000000 +0300 @@ -0,0 +1,188 @@ +#ifndef _FLEA_DEFS_ +#define _FLEA_DEFS_ + +/* +* Include a whole bunch of RDB files for register definitions +*/ +#include "bcm_70015_regs.h" + +/* Assume we have 64MB DRam */ +#define FLEA_TOTAL_DRAM_SIZE 64*1024*1024 +#define FLEA_GISB_DIRECT_BASE 0x50 + +/*- These definition of the ADDRESS and DATA + - Registers are not there in RDB. + */ +#define FLEA_GISB_INDIRECT_ADDRESS 0xFFF8 +#define FLEA_GISB_INDIRECT_DATA 0xFFFC + +/* + * POLL count for Flea. + */ +#define FLEA_MAX_POLL_CNT 1000 + +/* + -- Flea Firmware Signature length (128 bit) + */ +#define FLEA_FW_SIG_LEN_IN_BYTES 16 +#define LENGTH_FIELD_SIZE 4 +#define FLEA_FW_SIG_LEN_IN_DWORD (FLEA_FW_SIG_LEN_IN_BYTES/4) +#define FW_DOWNLOAD_START_ADDR 0 + +/* + * Some macros to ease the bit specification from RDB + */ +#define SCRAM_KEY_DONE_INT_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT) +#define BOOT_VER_DONE_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT) +#define BOOT_VER_FAIL_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT) +#define SHARF_ERR_INTR BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT) +#define SCRUB_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT) +#define DRAM_SCRAM_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT) +#define ARM_RUN_REQ_BIT BC_BIT(BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT) +#define GetScrubEndAddr(_Sz) ((FW_DOWNLOAD_START_ADDR + (_Sz - FLEA_FW_SIG_LEN_IN_BYTES -LENGTH_FIELD_SIZE-1))& (BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK)) + +/* +-- Firmware Command Interface Definitions. +-- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 as host to FW mailbox. +-- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 as FW to Host mailbox. +*/ + +/* Address where the command parameters are written. */ +#define DDRADDR_4_FWCMDS 0x100 + +/* */ +/* mailbox used for passing the FW Command address (DDR address) to */ +/* firmware. */ +/* */ +#define FW_CMD_POST_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 + +/* Once we get a firmware command done interrupt, */ +/* we will need to get the address of the response. */ +/* This mailbox is written by FW before asserting the */ +/* firmware command done interrupt. */ +#define FW_CMD_RES_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 + +/* +-- RxDMA Picture QStatus Mailbox. +-- RxDMA Picture Post Mailbox. < Write DDR address to this mailbox > + */ +#define RX_DMA_PIC_QSTS_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 +#define RX_POST_MAILBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 +#define RX_POST_CONFIRM_SCRATCH BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 +#define RX_START_SEQ_NUMBER 1 +#define INDICATE_TX_DONE_REG BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 + +/* +-- At the end of the picture frame there is the Link's Y0 data +-- and there is Width data. The driver will copy this 32 bit data to Y[0] +-- location. This makes the Flea PIB compatible with Link. +-- Also note that Flea is capable of putting out the odd size picture widths +-- so the PicWidth field is the actual picture width of the picture. In link +-- We were only getting 1920,1280 or 720 as picture widths. +*/ +#define PIC_PIB_DATA_OFFSET_FROM_END 4 +#define PIC_PIB_DATA_SIZE_IN_BYTES 4 /*The data that use to be in Y[0] component */ +#define PIC_WIDTH_OFFSET_FROM_END 8 /*Width information for the driver. */ +#define PIC_WIDTH_DATA_SIZE_IN_BYTES 4 /*Width information for the driver. */ + +/* +-- The format change PIB comes in a dummy frame now. +-- The Width field has the format change flag (bit-31) which +-- the driver uses to detect the format change now. +*/ +#define PIB_FORMAT_CHANGE_BIT BC_BIT(31) +#define PIB_EOS_DETECTED_BIT BC_BIT(30) + +#define FLEA_DECODE_ERROR_FLAG 0x800 + +/* +-- Interrupt Mask, Set and Clear registers are exactly +-- same as the interrupt status register. We will +-- Use the following union for all the registers. +*/ + +union FLEA_INTR_BITS_COMMON +{ + struct + { + uint32_t L0TxDMADone:1; /* Bit-0 */ + uint32_t L0TxDMAErr:1; /* Bit-1 */ + uint32_t L0YRxDMADone:1; /* Bit-2 */ + uint32_t L0YRxDMAErr:1; /* Bit-3 */ + uint32_t L0UVRxDMADone:1; /* Bit-4 */ + uint32_t L0UVRxDMAErr:1; /* Bit-5 */ + uint32_t Reserved1:2; /* Bit-6-7 */ + uint32_t L1TxDMADone:1; /* Bit-8 */ + uint32_t L1TxDMAErr:1; /* Bit-9 */ + uint32_t L1YRxDMADone:1; /* Bit-10 */ + uint32_t L1YRxDMAErr:1; /* Bit-11 */ + uint32_t L1UVRxDMADone:1; /* Bit-12 */ + uint32_t L1UVRxDMAErr:1; /* Bit-13 */ + uint32_t Reserved2:2; /* Bit-14-15 */ + uint32_t ArmMbox0Int:1; /* Bit-16 */ + uint32_t ArmMbox1Int:1; /* Bit-17 */ + uint32_t ArmMbox2Int:1; /* Bit-18 */ + uint32_t ArmMbox3Int:1; /* Bit-19 */ + uint32_t Reserved3:4; /* Bit-20-23 */ + uint32_t PcieTgtUrAttn:1; /* Bit-24 */ + uint32_t PcieTgtCaAttn:1; /* Bit-25 */ + uint32_t HaltIntr:1; /* Bit-26 */ + uint32_t Reserved4:5; /* Bit-27-31 */ + }; + + uint32_t WholeReg; +}; + +/* +================================================================ +-- Flea power state machine +-- FLEA_PS_NONE +-- Enter to this state when system boots up and device is not open. +-- FLEA_PS_ACTIVE: +-- 1. Set when the device is started and FW downloaded. +-- 2. We come to this state from FLEA_PS_LP_COMPLETE when +-- 2.a Free list length becomes greater than X. [Same As Internal Pause Sequence] +-- 2.b There is a firmware command issued. +-- 3. We come to this state from FLEA_PS_LP_PENDING when +-- 3.a Free list length becomes greater than X. [Same As Internal Pause Sequence] +-- 3.b There is a firmware command Issued. +-- FLEA_PS_LP_PENDING +-- 1. Enter to this state from FLEA_PS_ACTIVE +-- 1.a FLL becomes greater less than Y[Same as Internal Resume]. +-- FLEA_PS_LP_COMPLETE +-- 1. Enter in to this state from FLEA_PS_LP_PENDING +-- 1.a There are no Pending TX, RX, and FW Command. +-- 2. Enter to This state when the handle is closed. +-- 3. Enter to this state From ACTIVE +-- 3.a FLL < Y. +-- 3.b There is no TX,RX and FW pending. +-- 4. Enter this state when RX is not running, either before it is started or after it is stopped. +================================================================= +*/ + +enum FLEA_POWER_STATES { + FLEA_PS_NONE=0, + FLEA_PS_STOPPED, + FLEA_PS_ACTIVE, + FLEA_PS_LP_PENDING, + FLEA_PS_LP_COMPLETE +}; + +enum FLEA_STATE_CH_EVENT { + FLEA_EVT_NONE=0, + FLEA_EVT_START_DEVICE, + FLEA_EVT_STOP_DEVICE, + FLEA_EVT_FLL_CHANGE, + FLEA_EVT_FW_CMD_POST, + FLEA_EVT_CMD_COMP +}; + +#define TEST_BIT(_value_,_bit_number_) (_value_ & (0x00000001 << _bit_number_)) + +#define CLEAR_BIT(_value_,_bit_number_)\ +{_value_ = _value_ & (~(0x00000001 << _bit_number_));} + +#define SET_BIT(_value_,_bit_number_)\ +{_value_ |= (0x01 << _bit_number_);} + +#endif --- crystalhd~/Makefile 2014-03-31 07:40:15.000000000 +0400 +++ crystalhd/Makefile 2015-04-06 20:41:20.000000000 +0300 @@ -3,4 +3,7 @@ obj-$(CONFIG_CRYSTALHD) += crystalhd.o crystalhd-y := crystalhd_cmds.o \ crystalhd_hw.o \ crystalhd_lnx.o \ + crystalhd_linkfuncs.o \ + crystalhd_fleafuncs.o \ + crystalhd_flea_ddr.o \ crystalhd_misc.o