Attachment 10919 Details for Bug 42996 – Зависание. Ничем не закончилось. Пришлось перегружать аппаратно.

Зависание. Ничем не закончилось. Пришлось перегружать аппаратно.

1Э8СВ-uATX-AltServer10-boot-hang-1-20220615.txt (text/plain), 55.64 KB, created by asazonov on 2022-06-15 17:52:24 MSK

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Creator: asazonov

Created: 2022-06-15 17:52:24 MSK

Size: 55.64 KB

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obsolete

>CPU#C0: BOOT started.
>CPU#C0: 	BOOT		E8C2
>CPU#C0: 	VERSION:	pre-release-2.24.1.X ::::::: ( /branches/release-2.24.1.X at revision 8002 )
>CPU#C0: 	BUILT	BY	neo
>CPU#C0: 		TARGET:	uatx_388_02
>CPU#C0: 		ON	Jul 16 2021
>CPU#C0: 		AT	18:25:44
>CPU#C0: 	COMPILER:	lcc:1.23.20:Sep--4-2019:e2k-v2-linux.cross:x86_64-linux gcc (GCC) 5.5.0 compatible
>CPU#C0: 	FLAGS:	 -DCONFIG_NUMA -DCONFIG_IPCC2 -DTEST_MEMTESTER -DMEMORY_TEST_ALL_NODE -DSIC_LINK_USER_PARAMS -DIPCC_DEBUG -DMC_FREQ_1375MHZ -DALLOC_IDE_PRD_TBL_STATICALLY -DISO9660_USE_CASH -DISO9660_MANGLING_NAMES -DISO9660_USE_LOCAL_HEAP -DMCST_SATA -DMCST2_IDE -DNEW_AHCI_ATAPI -DDEBUG_TESTS -DHASH_GOST_34_11_2012_DISABLED -DNVME_DISABLED -DFAT_EFI_SUPPORT -DPCC_SIMULATE_CARD_OS_STARTED_THEN_START -DPCC_READ_CARD_FILES_BY_PARTS -DDO_NOT_INIT_MGA_IF_MGA_3D_PRESENT -DBUG52542  -DRELEASE
>
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#C0: 
>CPU#C0: L2 cache
>CPU#C0: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#C0: D_SIG1: 0
>CPU#C0: D_SIG2: 0
>CPU#C0: D_SIG3: 0
>CPU#C0: D_SIG4: 16
>CPU#C0: T_SIG: 0
>CPU#C0: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#C0: D_SIG1: 0
>CPU#C0: D_SIG2: 0
>CPU#C0: D_SIG3: 0
>CPU#C0: D_SIG4: 16
>CPU#C0: T_SIG: 0
>CPU#C0: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#C0: D_SIG1: 0
>CPU#C0: D_SIG2: 0
>CPU#C0: D_SIG3: 0
>CPU#C0: D_SIG4: 16
>CPU#C0: T_SIG: 0
>CPU#C0: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#C0: D_SIG1: 0
>CPU#C0: D_SIG2: 0
>CPU#C0: D_SIG3: 0
>CPU#C0: D_SIG4: 16
>CPU#C0: T_SIG: 0
>CPU#C0: 
> TEMP:00 bus:00 : addr:4C : LM96163: init!
> TEMP:01 bus:01 : addr:4C : LM96163: init!
>tmr_hz = 0x0000000059682D48 (1499 MHz)
>
>L3 Cache BIST checking:
>	bank 0:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 1:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 2:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 3:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 4:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 5:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 6:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>	bank 7:
>		data memory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 256
>		don't use:
>			max errors in line: 0
>			broken lines: 0
>		local directory:
>			unrecoverable: 0
>			2 broken columns: 0
>			1 broken column: 0
>			good: 32
>		don't use errors: no
>		LRU errors: no
>CPU#C0: Configure local SIC:
>CPU#C0: Link 1: Idle, powered off
>CPU#C0: Link 2: Idle, powered off
>CPU#C0: Link 3: Idle, powered off
>CPU#C0: Change own address to 00
>CPU#00: SIC configuring is finished
>CPU#00: Enable coherence
>CPU#00: Configure chipset with defaults
>CPU#00: Reset found: Software reset.
>BSP memory is not configured, mark AP nodes too
>Setup SIC_HW1
>CPU#00: Change MC frequency to 604.166MHz for channels 0 and 1
>CPU#00: Change MC frequency to 604.166MHz for channels 2 and 3
>CPU#00: Setup Fminmc
>CPU#00: Fminmc: 19
>CPU#00: PCS_CTRL1 ---> 0x04136590
>CPU#00: PCS_CTRL1 <--- 0x04136590
>Checking SIC directory cache BIST:
>	SIC_local_gen[0]:
>		DU_SIG1: 0
>		DU_SIG2: 0
>		LRU errors: no
>		don't use errors (0-31): no
>		don't use errors (32-63): no
>		don't use errors (64-95): no
>		don't use errors (96-127): no
>		MEM_SIG1: 0
>		MEM_SIG2: 0
>		MEM_SIG3: 0
>		MEM_SIG4: 128
>	SIC_local_gen[1]:
>		DU_SIG1: 0
>		DU_SIG2: 0
>		LRU errors: no
>		don't use errors (0-31): no
>		don't use errors (32-63): no
>		don't use errors (64-95): no
>		don't use errors (96-127): no
>		MEM_SIG1: 0
>		MEM_SIG2: 0
>		MEM_SIG3: 0
>		MEM_SIG4: 128
>CPU#00: Setting the directory:
>CPU#00: 	SIC_SCCFG ---> 0x000000B3
>CPU#00: 	SIC_SCCFG <--- 0x00000093
>MC is configured?: 0
>Init memory controller
>Checking known memory modules:
>Channel 0:
>Slot 0: empty
>Slot 1: empty
>Channel 1:
>Slot 0: DDR4 SDRAM 16384Mb RDIMM 2Rx4 M393A2G40DB1-CRC    
>Slot 1: empty
>Channel 2:
>Slot 0: DDR4 SDRAM 16384Mb RDIMM 2Rx4 M393A2G40DB1-CRC    
>Slot 1: empty
>Channel 3:
>Slot 0: empty
>Slot 1: empty
>MC Frequency: 604MHz
>Disable channel 0
>Disable channel 1
>Disable channel 2
>Disable channel 3
>channel 0
>Empty, skipping channel configuration.
>Low power mode on.
>channel 1
>DDR4 interface data rate: 2416Mbps
>DDR4 interface clock frequency: 1208MHz
>Init DDR4 PHY
>Set frqsel to 0
>Init DDR4 DRAM
>Computed rcven_del value is greater than 6
>Value 0x00000007 from rcven_del.get[1] is out of range (min 0x00000000, max 0x00000006).
>Start channel 1
>Enable channel 1
>channel 2
>DDR4 interface data rate: 2416Mbps
>DDR4 interface clock frequency: 1208MHz
>Init DDR4 PHY
>Set frqsel to 0
>Init DDR4 DRAM
>Start channel 2
>Enable channel 2
>channel 3
>Empty, skipping channel configuration.
>Low power mode on.
>Init memory filters
>CPU#00: Setting MCs interleaving:
>CPU#00: 	SIC_MIC <--- 0x00000008
>CPU#00: 	SIC_MIC ---> 0x00000008
>Hardware memory clean
>Channel 1 has ecc enabled, disable during mem clean
>Channel 2 has ecc enabled, disable during mem clean
>Cleaning channel 1
>Amount of memory in channel: 16384Mb
>Cleaning channel 2
>Amount of memory in channel: 16384Mb
>Enable channel 1
>Enable ecc in channel 1
>Enable channel 2
>Enable ecc in channel 2
>CPU#00: 
>Test boot memory region.
>CPU#00: 
>Memory test not selected by user, skipping. 
>CPU#00: Loading ROM DATA and BSS to RAM
>CPU#00: BOOT FREE MEM ADDR:0x0043B000
>CPU#00: Starting CPU#00 Core#01 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#01: 
>CPU#01: L2 cache
>CPU#01: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#01: D_SIG1: 0
>CPU#01: D_SIG2: 0
>CPU#01: D_SIG3: 0
>CPU#01: D_SIG4: 16
>CPU#01: T_SIG: 0
>CPU#01: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#01: D_SIG1: 0
>CPU#01: D_SIG2: 0
>CPU#01: D_SIG3: 0
>CPU#01: D_SIG4: 16
>CPU#01: T_SIG: 0
>CPU#01: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#01: D_SIG1: 0
>CPU#01: D_SIG2: 0
>CPU#01: D_SIG3: 0
>CPU#01: D_SIG4: 16
>CPU#01: T_SIG: 0
>CPU#01: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#01: D_SIG1: 0
>CPU#01: D_SIG2: 0
>CPU#01: D_SIG3: 0
>CPU#01: D_SIG4: 16
>CPU#01: T_SIG: 0
>CPU#01: 
>CPU#01: Enable coherence
>CPU#01: APIC_ID: 0x01
>CPU#01: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#02 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#02: 
>CPU#02: L2 cache
>CPU#02: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#02: D_SIG1: 0
>CPU#02: D_SIG2: 0
>CPU#02: D_SIG3: 0
>CPU#02: D_SIG4: 16
>CPU#02: T_SIG: 0
>CPU#02: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#02: D_SIG1: 0
>CPU#02: D_SIG2: 0
>CPU#02: D_SIG3: 0
>CPU#02: D_SIG4: 16
>CPU#02: T_SIG: 0
>CPU#02: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#02: D_SIG1: 0
>CPU#02: D_SIG2: 0
>CPU#02: D_SIG3: 0
>CPU#02: D_SIG4: 16
>CPU#02: T_SIG: 0
>CPU#02: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#02: D_SIG1: 0
>CPU#02: D_SIG2: 0
>CPU#02: D_SIG3: 0
>CPU#02: D_SIG4: 16
>CPU#02: T_SIG: 0
>CPU#02: 
>CPU#02: Enable coherence
>CPU#02: APIC_ID: 0x02
>CPU#02: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#03 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#03: 
>CPU#03: L2 cache
>CPU#03: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#03: D_SIG1: 0
>CPU#03: D_SIG2: 0
>CPU#03: D_SIG3: 0
>CPU#03: D_SIG4: 16
>CPU#03: T_SIG: 0
>CPU#03: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#03: D_SIG1: 0
>CPU#03: D_SIG2: 0
>CPU#03: D_SIG3: 0
>CPU#03: D_SIG4: 16
>CPU#03: T_SIG: 0
>CPU#03: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#03: D_SIG1: 0
>CPU#03: D_SIG2: 0
>CPU#03: D_SIG3: 0
>CPU#03: D_SIG4: 16
>CPU#03: T_SIG: 0
>CPU#03: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#03: D_SIG1: 0
>CPU#03: D_SIG2: 0
>CPU#03: D_SIG3: 0
>CPU#03: D_SIG4: 16
>CPU#03: T_SIG: 0
>CPU#03: 
>CPU#03: Enable coherence
>CPU#03: APIC_ID: 0x03
>CPU#03: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#04 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#04: 
>CPU#04: L2 cache
>CPU#04: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#04: D_SIG1: 0
>CPU#04: D_SIG2: 0
>CPU#04: D_SIG3: 0
>CPU#04: D_SIG4: 16
>CPU#04: T_SIG: 0
>CPU#04: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#04: D_SIG1: 0
>CPU#04: D_SIG2: 0
>CPU#04: D_SIG3: 0
>CPU#04: D_SIG4: 16
>CPU#04: T_SIG: 0
>CPU#04: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#04: D_SIG1: 0
>CPU#04: D_SIG2: 0
>CPU#04: D_SIG3: 0
>CPU#04: D_SIG4: 16
>CPU#04: T_SIG: 0
>CPU#04: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#04: D_SIG1: 0
>CPU#04: D_SIG2: 0
>CPU#04: D_SIG3: 0
>CPU#04: D_SIG4: 16
>CPU#04: T_SIG: 0
>CPU#04: 
>CPU#04: Enable coherence
>CPU#04: APIC_ID: 0x04
>CPU#04: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#05 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#05: 
>CPU#05: L2 cache
>CPU#05: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#05: D_SIG1: 0
>CPU#05: D_SIG2: 0
>CPU#05: D_SIG3: 0
>CPU#05: D_SIG4: 16
>CPU#05: T_SIG: 0
>CPU#05: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#05: D_SIG1: 0
>CPU#05: D_SIG2: 0
>CPU#05: D_SIG3: 0
>CPU#05: D_SIG4: 16
>CPU#05: T_SIG: 0
>CPU#05: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#05: D_SIG1: 0
>CPU#05: D_SIG2: 0
>CPU#05: D_SIG3: 0
>CPU#05: D_SIG4: 16
>CPU#05: T_SIG: 0
>CPU#05: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#05: D_SIG1: 0
>CPU#05: D_SIG2: 0
>CPU#05: D_SIG3: 0
>CPU#05: D_SIG4: 16
>CPU#05: T_SIG: 0
>CPU#05: 
>CPU#05: Enable coherence
>CPU#05: APIC_ID: 0x05
>CPU#05: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#06 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#06: 
>CPU#06: L2 cache
>CPU#06: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#06: D_SIG1: 0
>CPU#06: D_SIG2: 0
>CPU#06: D_SIG3: 0
>CPU#06: D_SIG4: 16
>CPU#06: T_SIG: 0
>CPU#06: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#06: D_SIG1: 0
>CPU#06: D_SIG2: 0
>CPU#06: D_SIG3: 0
>CPU#06: D_SIG4: 16
>CPU#06: T_SIG: 0
>CPU#06: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#06: D_SIG1: 0
>CPU#06: D_SIG2: 0
>CPU#06: D_SIG3: 0
>CPU#06: D_SIG4: 16
>CPU#06: T_SIG: 0
>CPU#06: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#06: D_SIG1: 0
>CPU#06: D_SIG2: 0
>CPU#06: D_SIG3: 0
>CPU#06: D_SIG4: 16
>CPU#06: T_SIG: 0
>CPU#06: 
>CPU#06: Enable coherence
>CPU#06: APIC_ID: 0x06
>CPU#06: Waking up BSP with APIC_ID=0x00
>CPU#00: Starting CPU#00 Core#07 and going to sleep
>Units BIST checking:
>	CU_HW0:
>		Chain File        OK
>		TU IP             OK
>		IB ITAG           OK
>		IB ITLB Tags      OK
>		IB ITLB Data      OK
>		IB IDATA nm       OK
>		IB IDATA cnt      OK
>	MU_HW0:
>		AAU APB           OK
>		MAU STB           OK
>		Cluster 1 DTLB    OK
>		Cluster 0 DTLB    OK
>		BIST L1 DUMEM     OK
>		BIST L1 DUCNT     OK
>L1 cache BIST checking.
>CPU#07: 
>CPU#07: L2 cache
>CPU#07: BANK#0: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#07: D_SIG1: 0
>CPU#07: D_SIG2: 0
>CPU#07: D_SIG3: 0
>CPU#07: D_SIG4: 16
>CPU#07: T_SIG: 0
>CPU#07: BANK#1: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#07: D_SIG1: 0
>CPU#07: D_SIG2: 0
>CPU#07: D_SIG3: 0
>CPU#07: D_SIG4: 16
>CPU#07: T_SIG: 0
>CPU#07: BANK#2: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#07: D_SIG1: 0
>CPU#07: D_SIG2: 0
>CPU#07: D_SIG3: 0
>CPU#07: D_SIG4: 16
>CPU#07: T_SIG: 0
>CPU#07: BANK#3: BIST_SIG1=0x0001000000000000, BIST_SIG2=0x0000000000000000
>CPU#07: D_SIG1: 0
>CPU#07: D_SIG2: 0
>CPU#07: D_SIG3: 0
>CPU#07: D_SIG4: 16
>CPU#07: T_SIG: 0
>CPU#07: 
>CPU#07: Enable coherence
>CPU#07: APIC_ID: 0x07
>CPU#07: Waking up BSP with APIC_ID=0x00
>
>All found cpu started
>
>CPU#00: Warning: interleaving between CPU's can be supported only in case of 2 or 4 node's (current number of CPU's: 1) 
>
>ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½. ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ 8388608 ï¿½ï¿½ï¿½ï¿½ @ 4f1000
>
>init_pci_hardware(): FILE=main.c, LINE=335
>CPU#00: 
> !!! TTY2 output started, PREVIOS OUTPUT on TTY1 ONLY !!! 
>
>CPU#00: Starting IO init.
>CPU#00: Found PCI on node 0 IOLink 0:
>
>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
><			SCAN PCI BUS
><
>< PCI Memory Base Reg = 0xf0008000 BGN = 0x80000000 END = 0xf7ffffff
>< PCI IO Base Reg = 0xf0000000 BGN = 0x0  END = 0xffff
><    PCI Non-pref memory BGN = 0x80000000  END = 0x8fffffff
><    PCI Pref memory BGN = 0x90000000  END = 0xf7ffffff
><    PCI IO BGN = 0x1000  END = 0xffff
><
><    BUS[0] SLOT[0] [80171fff] : 
><	Ven = 1fff, Dev = 0x8017, Rev = 0x0
><	Cmd = 100007
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 0, Line = 0xff
><	Child IRQ = 0x0
><		Reg[0]:		Size = 0x040		Base = 0x080000000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0xd] = 0x0
><	Reg[0x18] = 0x30200
><	IO base = 0x1000, Non-pref base = 0x80100000, Pref base = 0x90000000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x1 (Parent Bus = 0x0)
>	<
><	IOHub2 Device Number = 0x100
><
><	Init SLink
><		Scale = 0x13
><		Param = 0x0
>
><    BUS[1] SLOT[0] [80001fff]:
><	Ven = 1fff, Dev = 0x8000, Rev = 0x6
><	Cmd = 0
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x10
><	Child IRQ = 0x0
><	Write Latency Timer <- 0x80	Latency Timer [0x10000d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x1000, Non-pref base = 0x80100000, Pref base = 0x90000000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x2 (Parent Bus = 0x1)
>	<
><	Host Bridge timeout on secondary bus disabled for all.
><	Host Bridge transaction reordering disabled for all.
><	Host Bridge 64b operation on sec bus on downstream transactions disabled for all.
><	Reg[0x100040] = 0xe000000
>
><---------------------------------------- (Bus # 0x2 done) --------------------------------------------
>
>
><	IO base = 0x1000, Non-pref base = 0x80100000, Pref base = 0x90000000
><	IO limit= 0x1000, Non-pref limit= 0x80100000, Pref limit= 0x90000000
><	Write Reg[0x10003e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[1] [80161fff]:
><	Ven = 1fff, Dev = 0x8016, Rev = 0x0
><	Cmd = 0
><	Class code = 0x20000, Header type = 0x80
><	Network controller: Ethernet controller
>eth_process_absent_phy called
>
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x11
><		Reg[0]:		Size = 0x20		Base = 0x80100000	Non-prefetch
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 1fff, Dev = 0x8016, Rev = 0x0
><	Cmd = 0
><	Class code = 0x20000, Header type = 0x80
><	Network controller: Ethernet controller
>eth_process_absent_phy called
>
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x11
><		Reg[0]:		Size = 0x20		Base = 0x80100020	Non-prefetch
><
><        FUNC[2]:
><	Ven = 1fff, Dev = 0x8016, Rev = 0x0
><	Cmd = 0
><	Class code = 0x20000, Header type = 0x80
><	Network controller: Ethernet controller
>eth_process_absent_phy called
>
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x11
><		Reg[0]:		Size = 0x20		Base = 0x80100040	Non-prefetch
>
><    BUS[1] SLOT[2] [800b1fff]:
><	Ven = 1fff, Dev = 0x800b, Rev = 0x0
><	Cmd = 2800000
><	Class code = 0x1018a, Header type = 0x80
><	Mass storage controller: IDE controller
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x8		Base = 0x1000	IO space
><		Reg[1]:		Size = 0x4		Base = 0x1008	IO space
><		Reg[2]:		Size = 0x8		Base = 0x1010	IO space
><		Reg[3]:		Size = 0x4		Base = 0x1018	IO space
><		Reg[4]:		Size = 0x10		Base = 0x1020	IO space
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 1fff, Dev = 0x8018, Rev = 0x7
><	Cmd = 0
><	Class code = 0x70200, Header type = 0x80
><	Simple communications controller: Sub Class 2
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x40		Base = 0x90000000	Prefetchable
><		Reg[1]:		Size = 0x40		Base = 0x90000040	Prefetchable
><
><		IOHub Revision = 0x7
><
><		Reg[0x48]:	Size = 0x100000		Base = 0x80200000	Non-prefetch
><		Reg[0x58]:	Size = 0x40		Base = 0x80300000	Non-prefetch
>  Init i2c spi ... done.
>
><	IOAPIC Base = 0xfec00000
><		VER=0x11,TABL=0x17
><		Start IOAPIC ID = 0x0
><		Write IOAPIC ID = 0x10
><		Read IOAPIC ID = 0x10
><
><        FUNC[2]:
><	Ven = 1fff, Dev = 0x8019, Rev = 0x0
><	Cmd = 2000003
><	Class code = 0x78000, Header type = 0x80
><	Simple communications controller: Other
><	Parent IRQ = 0x0
><	Pin = 0, Line = 0x11
><		Reg[0]:		Size = 0x20		Base = 0x1040	IO space
><		Reg[1]:		Size = 0x10		Base = 0x80300040	Non-prefetch
><
><        FUNC[3]:
><	Ven = 1fff, Dev = 0x800a, Rev = 0x0
><	Cmd = 2000000
><	Class code = 0x40100, Header type = 0x80
><	Multimedia device: Audio device
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x4000		Base = 0x80304000	Non-prefetch
><
><        FUNC[4]:
><	Ven = 1fff, Dev = 0x8014, Rev = 0x0
><	Cmd = 2000002
><	Class code = 0x78000, Header type = 0x80
><	Simple communications controller: Other
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x20		Base = 0x80308000	Non-prefetch
><		Reg[1]:		Size = 0x80		Base = 0x80308080	Non-prefetch
>
><    BUS[1] SLOT[3] [801a1fff]:
><	Ven = 1fff, Dev = 0x801a, Rev = 0x0
><	Cmd = 2800000
><	Class code = 0x10601, Header type = 0x80
><	Mass storage controller: SATA controller
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x13
><		Reg[0]:		Size = 0x8		Base = 0x1060	IO space
><		Reg[1]:		Size = 0x10		Base = 0x1070	IO space
><		Reg[2]:		Size = 0x8		Base = 0x1080	IO space
><		Reg[3]:		Size = 0x10		Base = 0x1090	IO space
><		Reg[4]:		Size = 0x10		Base = 0x10a0	IO space
><		Reg[5]:		Size = 0x2000		Base = 0x8030a000	Non-prefetch
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 1fff, Dev = 0x801a, Rev = 0x0
><	Cmd = 2800000
><	Class code = 0x10601, Header type = 0x80
><	Mass storage controller: SATA controller
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x13
><		Reg[0]:		Size = 0x8		Base = 0x10b0	IO space
><		Reg[1]:		Size = 0x10		Base = 0x10c0	IO space
><		Reg[2]:		Size = 0x8		Base = 0x10d0	IO space
><		Reg[3]:		Size = 0x10		Base = 0x10e0	IO space
><		Reg[4]:		Size = 0x10		Base = 0x10f0	IO space
><		Reg[5]:		Size = 0x2000		Base = 0x8030c000	Non-prefetch
>
><    BUS[1] SLOT[4] [80101fff]:
><	Ven = 1fff, Dev = 0x8010, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x10
><	Child IRQ = 0x0
><		Reg[0]:		Size = 0x040		Base = 0x08030e000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x12000d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x2000, Non-pref base = 0x80400000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x3 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x8030e000] = 0x390
><    Write to Int Reg <- 0x390
><    PCI-E Int Reg = 0x390
><
>
><---------------------------------------- (Bus # 0x3 done) --------------------------------------------
>
>
><	IO base = 0x2000, Non-pref base = 0x80400000, Pref base = 0x90100000
><	IO limit= 0x2000, Non-pref limit= 0x80400000, Pref limit= 0x90100000
><	Write Reg[0x12003e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[5] [80101fff]:
><	Ven = 1fff, Dev = 0x8010, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x11
><	Child IRQ = 0x1
><		Reg[0]:		Size = 0x040		Base = 0x080400000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x12800d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x2000, Non-pref base = 0x80500000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x4 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x80400000] = 0x390
><    Write to Int Reg <- 0xe5
><    PCI-E Int Reg = 0xe5
><
>
><---------------------------------------- (Bus # 0x4 done) --------------------------------------------
>
>
><	IO base = 0x2000, Non-pref base = 0x80500000, Pref base = 0x90100000
><	IO limit= 0x2000, Non-pref limit= 0x80500000, Pref limit= 0x90100000
><	Write Reg[0x12803e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[6] [80101fff]:
><	Ven = 1fff, Dev = 0x8010, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><	Child IRQ = 0x2
><		Reg[0]:		Size = 0x040		Base = 0x080500000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x13000d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x2000, Non-pref base = 0x80600000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x5 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x80500000] = 0x390
><    Write to Int Reg <- 0x13a
><    PCI-E Int Reg = 0x13a
><
>
><    BUS[5] SLOT[0] [11501a03]:
><	Ven = 1a03, Dev = 0x1150, Rev = 0x3
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x2
><	Pin = 0, Line = 0x0
><	Child IRQ = 0x2
><	Write Latency Timer <- 0x80	Latency Timer [0x50000d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x2000, Non-pref base = 0x80600000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x6 (Parent Bus = 0x5)
>	<
>
><    BUS[6] SLOT[0] [20001a03]:
><	Ven = 1a03, Dev = 0x2000, Rev = 0x30
><	Cmd = 2100000
><	Class code = 0x30000, Header type = 0x0
><	Display controller: VGA compatible controller
><	Parent IRQ = 0x2
><	Pin = 1, Line = 0x12
><	VGA found. Bus = 0x6. 
><		Reg[0]:		Size = 0x800000		Base = 0x80800000	Non-prefetch
><		Reg[1]:		Size = 0x20000		Base = 0x81000000	Non-prefetch
><		Reg[2]:		Size = 0x80		Base = 0x2000	IO space
>
><---------------------------------------- (Bus # 0x6 done) --------------------------------------------
>
>
><	IO base = 0x2000, Non-pref base = 0x80600000, Pref base = 0x90100000
><	IO limit= 0x3000, Non-pref limit= 0x81100000, Pref limit= 0x90100000
><	Write Reg[0x50003e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><---------------------------------------- (Bus # 0x5 done) --------------------------------------------
>
>
><	IO base = 0x2000, Non-pref base = 0x80600000, Pref base = 0x90100000
><	IO limit= 0x3000, Non-pref limit= 0x81100000, Pref limit= 0x90100000
><	Write Reg[0x13003e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[7] [80101fff]:
><	Ven = 1fff, Dev = 0x8010, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x13
><	Child IRQ = 0x3
><		Reg[0]:		Size = 0x040		Base = 0x081100000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x13800d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x3000, Non-pref base = 0x81200000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x7 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x81100000] = 0x390
><    Write to Int Reg <- 0x24f
><    PCI-E Int Reg = 0x24f
><
>
><---------------------------------------- (Bus # 0x7 done) --------------------------------------------
>
>
><	IO base = 0x3000, Non-pref base = 0x81200000, Pref base = 0x90100000
><	IO limit= 0x3000, Non-pref limit= 0x81200000, Pref limit= 0x90100000
><	Write Reg[0x13803e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[8] [80111fff]:
><	Ven = 1fff, Dev = 0x8011, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x10
><	Child IRQ = 0x0
><		Reg[0]:		Size = 0x040		Base = 0x081200000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x14000d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x3000, Non-pref base = 0x81300000, Pref base = 0x90100000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x8 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x81200000] = 0x390
><    Write to Int Reg <- 0x390
><    PCI-E Int Reg = 0x390
><
>
><    BUS[8] SLOT[0] [10e21000]:
><	Ven = 1000, Dev = 0x10e2, Rev = 0x0
><	Cmd = 100000
><	Class code = 0x10400, Header type = 0x0
><	Mass storage controller: RAID controller
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x10
><		Reg[0]:		Size = 0x0100000		Base = 0x090100000	Prefetch 64 bit
><		Reg[2]:		Size = 0x0100000		Base = 0x090200000	Prefetch 64 bit
><		Reg[4]:		Size = 0x100000		Base = 0x81300000	Non-prefetch
><		Reg[5]:		Size = 0x100		Base = 0x3000	IO space
><		Reg[0x30]:	Size = 0x100000		Base = 0x90300000	Prefetchable
>
><---------------------------------------- (Bus # 0x8 done) --------------------------------------------
>
>
><	IO base = 0x3000, Non-pref base = 0x81300000, Pref base = 0x90100000
><	IO limit= 0x4000, Non-pref limit= 0x81400000, Pref limit= 0x90400000
><	Write Reg[0x14003e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[9] [80111fff]:
><	Ven = 1fff, Dev = 0x8011, Rev = 0x1
><	Cmd = 100000
><	Class code = 0x60400, Header type = 0x1
><	Bridge Device: PCI/PCI bridge
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x11
><	Child IRQ = 0x1
><		Reg[0]:		Size = 0x040		Base = 0x081400000	Non-pref 64 bit
><	Write Latency Timer <- 0x80	Latency Timer [0x14800d] = 0x0
><	Reg[0x18] = 0x0
><	IO base = 0x4000, Non-pref base = 0x81500000, Pref base = 0x90400000
><	IO limit= 0xffff, Non-pref limit= 0x8fffffff, Pref limit= 0xf7ffffff
><
><
>	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>	<	Scan PCI Bus = 0x9 (Parent Bus = 0x1)
>	<
><    PCI-E Int Reg[0x81400000] = 0x390
><    Write to Int Reg <- 0xe5
><    PCI-E Int Reg = 0xe5
><
>
><    BUS[9] SLOT[0] [101515b3]:
><	Ven = 15b3, Dev = 0x1015, Rev = 0x0
><	Cmd = 100000
><	Class code = 0x20000, Header type = 0x80
><	Network controller: Ethernet controller
>eth_process_absent_phy called
>
><	Parent IRQ = 0x1
><	Pin = 1, Line = 0x11
><		Reg[0]:		Size = 0x02000000		Base = 0x092000000	Prefetch 64 bit
><		Reg[0x30]:	Size = 0x100000		Base = 0x94000000	Prefetchable
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 15b3, Dev = 0x1015, Rev = 0x0
><	Cmd = 100000
><	Class code = 0x20000, Header type = 0x80
><	Network controller: Ethernet controller
>eth_process_absent_phy called
>
><	Parent IRQ = 0x1
><	Pin = 2, Line = 0x12
><		Reg[0]:		Size = 0x02000000		Base = 0x096000000	Prefetch 64 bit
><		Reg[0x30]:	Size = 0x100000		Base = 0x98000000	Prefetchable
>
><---------------------------------------- (Bus # 0x9 done) --------------------------------------------
>
>
><	IO base = 0x4000, Non-pref base = 0x81500000, Pref base = 0x90400000
><	IO limit= 0x4000, Non-pref limit= 0x81500000, Pref limit= 0x98100000
><	Write Reg[0x14803e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
><    BUS[1] SLOT[a] [80081fff]:
><	Ven = 1fff, Dev = 0x8008, Rev = 0x0
><	Cmd = 2000000
><	Class code = 0xc0310, Header type = 0x80
><	Serial bus controller: USB (Universal Serial Bus)
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x1000		Base = 0x81500000	Non-prefetch
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 1fff, Dev = 0x801e, Rev = 0x0
><	Cmd = 2000000
><	Class code = 0xc0320, Header type = 0x80
><	Serial bus controller: USB (Universal Serial Bus)
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x12
><		Reg[0]:		Size = 0x100		Base = 0x81501000	Non-prefetch
>
><    BUS[1] SLOT[b] [80081fff]:
><	Ven = 1fff, Dev = 0x8008, Rev = 0x0
><	Cmd = 2000000
><	Class code = 0xc0310, Header type = 0x80
><	Serial bus controller: USB (Universal Serial Bus)
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x13
><		Reg[0]:		Size = 0x1000		Base = 0x81502000	Non-prefetch
><
><    Multifunction device
><
><        FUNC[1]:
><	Ven = 1fff, Dev = 0x801e, Rev = 0x0
><	Cmd = 2000000
><	Class code = 0xc0320, Header type = 0x80
><	Serial bus controller: USB (Universal Serial Bus)
><	Parent IRQ = 0x0
><	Pin = 1, Line = 0x13
><		Reg[0]:		Size = 0x100		Base = 0x81503000	Non-prefetch
>
><    BUS[1] SLOT[c] [800e1fff]:
><	Ven = 1fff, Dev = 0x800e, Rev = 0x0
><	Cmd = 0
><	Class code = 0x0, Header type = 0x0
><	Device built before class codes: Other than VGA
><	Parent IRQ = 0x0
><	Pin = 0, Line = 0x0
> * SPMC * ACPI * 
>
><---------------------------------------- (Bus # 0x1 done) --------------------------------------------
>
>
><	IO base = 0x1000, Non-pref base = 0x80100000, Pref base = 0x90000000
><	IO limit= 0x4000, Non-pref limit= 0x81600000, Pref limit= 0x98100000
><	Write Reg[0x3e] <- 0x0	 Reg = 0x0
><
><		PCI Bridge configured
><
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
><
><    Min bus = 0x1  Max bus = 0x9
>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
>
>
> Disable Completion Timeouts... Done.
>CPU#00: No IOHUB on node 1 IOLink 0:
>CPU#00: No IOHUB on node 2 IOLink 0:
>CPU#00: No IOHUB on node 3 IOLink 0:
>CPU#00: Found IOHUB on node 0 IOLink 0:
>CPU#00: Set user baud for PCIe!
>
> VGA node num = 250
>Card auto select:=0,bus:=6
>
>Pci marker:=00:00
>Pci rom a:=FFFFFFFF
>Pcirom:=0
> Enable PCI VGA Dev.
><	Write Reg[0x50003e] <- 0x8	 Reg = 0x8
><	Write Reg[0x13003e] <- 0x8	 Reg = 0x0
><	Write Reg[0x3e] <- 0x8	 Reg = 0x8
>Found first bridge: Ven ID = 0x1fff, Dev ID = 0x8017:: AST2400
>
>   Try to start videobios.
>			CB video bios DONE!
>
>  Start Gen VGA driver.
>vga_partial_init()..
> VID=0x1A032000
>vga_font_8x16_only_load()..logo::of:=0x2000 ... done
>VGA::fb:=0xB8000
>
>Add display ... 
>Configuring screen structure. screen = 0x0, dev = 0x0
>done:=0:done
>Starting Console init:
>Found screen # 0x0, model = 0x3 
>    mode = 0x2 
>    dev =  0x0, num = 0x0
>    venid =  0x8086, devid = 0x8086
>    maxX =  80, maxY = 24
>    depth = 0x8 
>    putchar = 0x115DB8 VGA console: screen [0] - Ready
>Console init finished.
>
>************************************************************
>*			USB
>*
>*
>* EHCI found:		NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0xA] FUNC[0x1]
>* EHCI number:		0
>* EHCI revision:	1.0
>* <<<< ROOT HUB >>>>
>* Maximum Port Number:	4
>*
>* EHCI found:		NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0xB] FUNC[0x1]
>* EHCI number:		1
>* EHCI revision:	1.0
>* <<<< ROOT HUB >>>>
>* Maximum Port Number:	4
>* Device is connected:	Port 1
>*			Low-Speed Device, Port Released
>*
>* OHCI found:		NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0xA] FUNC[0x0]
>* OHCI number:		0
>* OHCI revision:	1.0
>* <<<< ROOT HUB >>>>
>* Maximum Port Number:	4
>*
>* OHCI found:		NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0xB] FUNC[0x0]
>* OHCI number:		1
>* OHCI revision:	1.0
>* <<<< ROOT HUB >>>>
>* Maximum Port Number:	4
>* Device is connected:	Port 1
>*			Low-Speed Device
>*			Device added
>*			
>* <<<< HUBS >>>>
>**********************USB3**********************************
>
>* XHCI controllers init finished
>
>************************************************************
>
>
>************************************************************
>*			KEYBOARDS
>*
>* Keyboard found
>* Location:	OHCI1	Port1
>*		Configuration1    Interface0    Alternate Setting0
>************************************************************
>
>CPU#00: Starting Unified input init:
>CPU#00: TTY1   - Ready
>CPU#00: TTY2   - Ready
>CPU#00: USB_KB - Ready
>CPU#00: Unified input init finished.
>CPU#00: Delay of 2 sec was enabled, before drives initialisation starts...
>Delay completed    
>CPU#00: Starting drives controllers init:
>CPU#00: Looking Node#0 IOlink#0 IO-hub: 
>CPU#00: Found: MCST IDE on PCI BUS[1]:DEV[2]:FUNC[0]
>CPU#00: Init MCST IDE controller: Native mode
>CPU#00: 	Drive [0]: Nothing
>CPU#00: 	Drive [1]: Nothing
>CPU#00: Found: MCST SATA COMBINED on PCI BUS[1]:DEV[3]:FUNC[0]
>CPU#00: Init MCST SATA COMBINED controller: 
>CPU#00: set_bios_settings: total_ports_implemented=4
>
>CPU#00: set_bios_settings: total_ports_implemented_mask=0xf
>
>CPU#00: set_bios_settings: SATA PI reg = 0xf
>CPU#00: Init generic AHCI interface: version 1.30, 4 ports, 32 cmd slots
>CPU#00: 	Drive [2]: Nothing 
>CPU#00: 	Drive [3]: Nothing 
>CPU#00: 	Drive [4]: Nothing 
>CPU#00: 	(Drive [5]: comm. est. at speed Gen.3)
>CPU#00: 	Drive [5]: TMI 256GB M2 CRMP.467512.002, 0x0 0x1dcf32b0 sectors, DMA: Ultra 6
>CPU#00: Found: MCST SATA COMBINED on PCI BUS[1]:DEV[3]:FUNC[1]
>CPU#00: Init MCST SATA COMBINED controller: 
>CPU#00: set_bios_settings: total_ports_implemented=4
>
>CPU#00: set_bios_settings: total_ports_implemented_mask=0xf
>
>CPU#00: set_bios_settings: SATA PI reg = 0xf
>CPU#00: Init generic AHCI interface: version 1.30, 4 ports, 32 cmd slots
>CPU#00: 	Drive [6]: Nothing 
>CPU#00: 	Drive [7]: Nothing 
>CPU#00: 	Drive [8]: Nothing 
>CPU#00: 	Drive [9]: Nothing 
>CPU#00: Drives controllers init finished
>
>************************************************************
>*		USB MASS STORAGE DEVICES
>************************************************************
>
>
>************************************************************
>*			ETHERNET
>* Looking for Ethernet Controllers
>*
>* Ethernet Controller found:	NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0x1] FUNC[0x0]
>* Ethernet Controller:		MCST ETH1000 Gigabit Ethernet
>* Interface number:		0
>* Physical Layer:		
>* Phy found (addr on mdio bus: X00):		
>* oui = 0X885
>             Microchip KSZ9031 rev.2
>* Mode:				Normal
>* Speed setting
>*	AUTO:			1000Mbps, Full-Duplex
>* MAC address:			98:A7:B0:04:B1:60
>*
>* Ethernet Controller found:	NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0x1] FUNC[0x1]
>* Ethernet Controller:		MCST ETH1000 Gigabit Ethernet
>* Interface number:		1
>* Physical Layer:		
>* Phy found (addr on mdio bus: X00):		
>* oui = 0X885
>             Microchip KSZ9031 rev.2
>* Mode:				Normal
>* Speed setting
>*	AUTO:			Failed, no link
>* MAC address:			98:A7:B0:04:B1:61
>*
>* Ethernet Controller found:	NODE[0x0] IOLINK[0x0] PCI BUS[0x1] SLOT[0x1] FUNC[0x2]
>* Ethernet Controller:		MCST ETH1000 Gigabit Ethernet
>* Interface number:		2
>* Physical Layer:		
>* Phy not found.		
>* Mode:				Normal
>* Speed setting
>*	AUTO:			Failed, no link
>* MAC address:			98:A7:B0:04:B1:62
>*
>* Ethernet Controller found:	NODE[0x0] IOLINK[0x0] PCI BUS[0x9] SLOT[0x0] FUNC[0x0]
>* Ethernet Controller:		unknown
>*
>* Ethernet Controller found:	NODE[0x0] IOLINK[0x0] PCI BUS[0x9] SLOT[0x0] FUNC[0x1]
>* Ethernet Controller:		unknown
>************************************************************
>
>
>************************************************************
>*		ATA over Ethernet
>* Using 5000 (0x1388) (ms) as aoe timeout break.
>*		AoE::aoe_timeout_break=5000
>* Interface #0: link status 1001
>* Interface #1: link status 0
>* Interface #2: link status 0
>* Server RQs:
>* Using FF:FF:FF:FF:FF:FF as the destination MAC address.
>* Using 65535 (0xFFFF) as the destination major address.
>* Using 255 (0xFF) as the destination minor address.
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* Server RQ transmitted
>* No server found
>************************************************************
>
>CPU#00: Looking Node#0 IOlink#0 IO-hub: 
>CPU#00: Found: iohub2 pci2pci bridge on PCI BUS[0]:DEV[0]:FUNC[0]
>boot assumes hardware configured iohub2 link width for value 0xf.
>actual iohub2 link widths:
>get_iohub2_link_width: pls_ctlr_reg=0x930f0f33 (first access)
>get_iohub2_link_width: pls_ctlr_reg=0x930f0f33
>link width is 0xf for iohub2 identified with
> virtual pci2pci bridge at BUS[0]:DEV[0]:FUNC[0]
>CPU#00: Starting file systems init: 
>CPU#00: 
>Skipping partition 1 on disk 5: ext4 uses unsupported features
>
>CPU#00: 
>Skipping partition 4 on disk 5: ext4 uses unsupported features
>
>CPU#00: Done
>CPU#00: BOOT:Params get..Done.
>CPU#00: Search drive and partition by label or uuid failed
>CPU#00: Drive [5]: SATA - NODE[0] IOLINK[0] PCI BUS[1]:DEV[3]:FUNC[0], MCST SATA COMBINED Port [3] - TMI 256GB M2 CRMP.467512.002
>CPU#00: 	Partition [0]: fs: Linux EXT2;
>	           U:be40257e-4b7e-4753-9572-a8fea2f0c8bf L:""
>CPU#00: 	Partition [1]: Linux
>CPU#00: 	Partition [3]: Extended
>CPU#00: 	Partition [4]: Linux
>CPU#00: 
>CPU#00: Searching auto install parameters.
>There is no drive applicable for auto install feature.
>CPU#00: Can not find auto install parameters.
>CPU#00: Trying to load boot configuration file from Drive [5]... Success
>CPU#00: Using boot parameters from Drive [5]
>CPU#00: Searching '/boot.conf' for default label '5.4.163-elbrus-def-alt2.23.1'
>CPU#00: Label '5.4.163-elbrus-def-alt2.23.1' found, loading parameters
>CPU#00: Search drive and partition by label or uuid succeed
>Starting autoboot.                              
>
>Trying to load and start image with following parameters:
>drive_number:      '5'
>drive label:       ''
>partition_number:  '0'
>file system id:    ''
>command_string:    'console=ttyS0,115200 console=tty0 hardreset root=UUID=651709cd-2659-4a98-813d-0875e572441f'
>filename:          '/image-5.4.163-elbrus-def-alt2.23.1'
>initrdfilename:    '/initrd-5.4.163-elbrus-def-alt2.23.1.img'
>
>CPU#00: Reading: File - '/initrd-5.4.163-elbrus-def-alt2.23.1.img', Drive - 5, Partition - 0, Buffer - 0x1000000
>Loaded: 100%%
>CPU#00: Reading completed. File size: 13420544 bytes
>uuid of boot fs: "be40257e-4b7e-4753-9572-a8fea2f0c8bf"
>
>CPU#00: Reading: File - '/image-5.4.163-elbrus-def-alt2.23.1', Drive - 5, Partition - 0, Buffer - 0x1ff0000
>Loaded: 100%%
>CPU#00: Reading completed. File size: 17467320 bytes
>CPU#00: '/image-5.4.163-elbrus-def-alt2.23.1' read kernel csum: 0x3a091611 (973674001)
>Calculating CRC32: 100%%
>CPU#00: '/image-5.4.163-elbrus-def-alt2.23.1' kernel csum: 0x3a091611 (973674001)
>CPU#00: Loaded image kernel checked successfully
>Kernel ROM loader's initialization started.
>
> bootblock_p: 0x1ff0100; boot_info: 0x1ff0100
> bootblock_p: 0x1ff0100; boot_info2: 0x1ff0100
>Wrong romloader signature. Must be e200 is 8086.
>CPU#00: 
> === boot_OS_IF: boot_info ====
>CPU#00: 
>bank 0: addr=00400000 size=008f1000
>prom_partition_find: PROM header not found 
> DevTree partition not found!
> devtree = 0xedfe0dd0
> Found DevTree magic at 0x100700000.
> devtree length = 0x96b Moved to 0x77a010.
>Before create_smp_config
>Bootblock: 0x1ff0100; boot_info: 0x1ff0100
> boot_info->mp_table_base = 0x077b000
> smp_write_floating_table: mpf  = 0x77b000
>mpf->mpf_physptr = 77b018
>
> smp_write_floating_table: mpf  = 0x77b000
>smp_write_config_table: mc = 77b018
>
>smp_write_config_table: mc->mpc_length = 2c
>
>smp_write_config_table: mc = 77b018
>
>smp_write_processors node=0: core=0: mc = 77b018
>
> smp_write_processor 0x77b044
>smp_write_processors node=0: core=1: mc = 77b018
>
> smp_write_processor 0x77b058
>smp_write_processors node=0: core=2: mc = 77b018
>
> smp_write_processor 0x77b06c
>smp_write_processors node=0: core=3: mc = 77b018
>
> smp_write_processor 0x77b080
>smp_write_processors node=0: core=4: mc = 77b018
>
> smp_write_processor 0x77b094
>smp_write_processors node=0: core=5: mc = 77b018
>
> smp_write_processor 0x77b0a8
>smp_write_processors node=0: core=6: mc = 77b018
>
> smp_write_processor 0x77b0bc
>smp_write_processors node=0: core=7: mc = 77b018
>
> smp_write_processor 0x77b0d0
>CPU#00: Found IOHUB on node 0 IOLink 0:
> get_iolinkver_by_revision = rev = 7
> smp_write_iolink 0x77b0e4
>before write_arch_mpspec
>
>smp_write_config_table: mc = 77b018
>
> timer addr = 0x80300000
>sizeof(mpc->mpc_timeraddr) = 0x8
>&(mpc->mpc_timeraddr) = 0x77b114
>sizeof(timer_addr) = 0x8
>sizeof(*mpc) = 0x10
> write ioapic [0x0 0x0] = 0xfec00000
> write bus-hrch
>index = 0:0 : proc_id = 0x0, apic_ver = 0x14, apic_bsp = 0x9
>index = 0:1 : proc_id = 0x1, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:2 : proc_id = 0x2, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:3 : proc_id = 0x3, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:4 : proc_id = 0x4, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:5 : proc_id = 0x5, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:6 : proc_id = 0x6, apic_ver = 0x14, apic_bsp = 0x8
>index = 0:7 : proc_id = 0x7, apic_ver = 0x14, apic_bsp = 0x8
>Interface data structures filled
>CPU#00: Ethernet Interfaces stopped
>CPU#00: USB stopped
>CPU#00: SPI frequency dropped to 12.5MHz
>Start all processors!!!
> smp starter
>Decompressor started
>Heap from 0x0000008020000000 to 0x0000008021000000
>Unpacking 0x00000000038d32e0 bytes from 0x000000000201fa18 to 0x0000008021400000...
>Done
>[    0.000000] 000: printk: bootconsole [early-dump0] enabled
>[    0.000000] 000: ARCH: E2K 
>[    0.000000] 000: NATIVE MACHINE TYPE: e8c2  IOHUB , ID 00e9, REVISION: 002, ISET #5
>[    0.000000] 000:  SERIAL # UNKNOWN
>[    0.000000] 000: Kernel image check sum: 973674001
>[    0.000000] 000: Booting native kernel without any virtualization support
>[    0.000000] 000: Zone ranges:
>[    0.000000] 000:   DMA      
>[    0.000000] 000: [mem 0x0000000000000000-0x00000000ffffffff]
>[    0.000000] 000:   Normal   
>[    0.000000] 000: [mem 0x0000000100000000-0x00000087ffffffff]
>[    0.000000] 000: Movable zone start for each node
>[    0.000000] 000: Early memory node ranges
>[    0.000000] 000:   node   0: [mem 0x0000000000000000-0x000000000009ffff]
>[    0.000000] 000:   node   0: [mem 0x00000000000c0000-0x000000001fffffff]
>[    0.000000] 000:   node   0: [mem 0x0000008020000000-0x00000087ffffffff]
>[    0.000000] 000: Zeroed struct page in unavailable ranges: 32 pages
>[    0.000000] 000: Initmem setup node 0 [mem 0x0000000000000000-0x00000087ffffffff]
>[    0.000000] 000: On node 0 totalpages: 8388576
>[    0.000000] 000:   DMA zone: 2048 pages used for memmap
>[    0.000000] 000:   DMA zone: 0 pages reserved
>[    0.000000] 000:   DMA zone: 131040 pages, LIFO batch:31
>[    0.000000] 000:   (Node 0: pfn range [0x0-0x100000] reduced to [0x0-0x20000])
>[    0.000000] 000:   Normal zone: 129024 pages used for memmap
>[    0.000000] 000:   Normal zone: 8257536 pages, LIFO batch:63
>[    0.000000] 000:   (Node 0: pfn range [0x100000-0x8800000] reduced to [0x8020000-0x8800000], real end 0x8800000)
>[    0.000000] 000: PM: Registered nosave memory: [mem 0x000a0000-0x000bffff]
>[    0.000000] 000: PM: Registered nosave memory: [mem 0x20000000-0x801fffffff]
>[    0.000000] 000: node0 kernel phys base: 0x8021400000
>[    0.000000] 000: DevTree: device tree size is 2411
>[    0.000000] 000: Memory wait type idle is not supported, turn OFF
>[    0.000000] 000: nr_irqs_gsi: 24
>[    0.000000] 000: percpu: Embedded 28 pages/cpu s73816 r8192 d32680 u114688
>[    0.000000] 000: pcpu-alloc: s73816 r8192 d32680 u114688 alloc=28*4096
>[    0.000000] 000: 
>[    0.000000] 000: pcpu-alloc: 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 0 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 1 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 2 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 3 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 4 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 5 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 6 
>[    0.000000] 000: [0] 
>[    0.000000] 000: 7 
>[    0.000000] 000: 
>[    0.000000] 000: Built 1 zonelists, mobility grouping on.  Total pages: 8257504
>[    0.000000] 000: Policy zone: Normal
>[    0.000000] 000: Kernel command line: console=ttyS0,115200 console=tty0 hardreset root=UUID=651709cd-2659-4a98-813d-0875e572441f
>[    0.000000] 000: Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
>[    0.000000] 000: Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
>[    0.000000] 000: Sorting __ex_table...
>[    0.000000] 000: mem auto-init: stack:off, heap alloc:off, heap free:off
>[    0.000000] 000: MMU: Page Table entries old format V1 is used
>[    0.000000] 000: MMU: United Page Tables for kernel and user
>[    0.000000] 000: kernel and users page table virt base: 0xff8000000000
>[    0.000000] 000: kernel virt base: 0xe20000000000, kernel virt end: 0xe200038d32e0
>[    0.000000] 000: Kernel virt base: 0000d00000000000, last valid phaddr: 0000008800000000
>[    0.000000] 000: Memory total mapped pages number 0x8800000 : valid 0x7fffe0, invalid 0x8000020
>[    0.000000] 000: Memory: 705732K/33554304K available (38912K kernel code, 3897K rwdata, 4096K rodata, 2892K init, 7022K bss, 655992K reserved, 0K cma-reserved)
>[    0.000000] 000: random: get_random_u64 called from cache_random_seq_create+0x148/0x3d8 with crng_init=0
>[    0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>[    0.000000] 000: random: get_random_u32 called from shuffle_freelist+0x128/0x4b0 with crng_init=0
>[    0.000000] 000: ftrace: allocating 30768 entries in 121 pages
>[    0.000000] 000: rcu: Hierarchical RCU implementation.
>[    0.000000] 000: rcu: 	RCU event tracing is enabled.
>[    0.000000] 000: rcu: 	RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
>[    0.000000] 000: 	RCU CPU stall warnings suppressed (rcu_cpu_stall_suppress).
>[    0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
>[    0.000000] 000: rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>[    0.000000] 000: NR_IRQS: 1536, nr_irqs: 410, preallocated irqs: 0
>[    0.000000] 000: Node #0 IO LINK #0 is
>[    0.000000] 000:  IO HUB controller
>[    0.000000] 000:  ON
>[    0.000000] 000:  connected to
>[    0.000000] 000:  IO HUB controller
>[    0.000000] 000: 
>[    0.002000] 000: Console: colour VGA+ 80x25
>[    0.003000] 000: printk: console [tty0] enabled
>ï¿½[    0.000000] 000: Linux version 5.4.163-elbrus-def-alt2.23.1 (builder@localhost.localdomain) (lcc:1.25.17:May-16-2021:e2k-v5-linux) #1 SMP Fri Dec 3 17:12:08 UTC 2021
>[    0.000000] 000: found SMP MP-table
>[    0.000000] 000: MultiProcessor Specification v1.4
>[    0.000000] 000:     Virtual Wire compatibility mode.
>[    0.000000] 000: OEM ID: LNXI     
>[    0.000000] 000: Product ID: 440GX       
>[    0.000000] 000: APIC at: 0xFEE00000
>[    0.000000] 000: Processor APIC ID #0 version 20
>[    0.000000] 000: Processor APIC ID #1 version 20
>[    0.000000] 000: Processor APIC ID #2 version 20
>[    0.000000] 000: Processor APIC ID #3 version 20
>[    0.000000] 000: Processor APIC ID #4 version 20
>[    0.000000] 000: Processor APIC ID #5 version 20
>[    0.000000] 000: Processor APIC ID #6 version 20
>[    0.000000] 000: Processor APIC ID #7 version 20
>[    0.000000] 000: IO link #0 on node 0, version 0xffff,
>[    0.000000] 000:  connected to IOHUB: min bus #1 max bus #9 IO APIC ID 16
>[    0.000000] 000: System timer type 1 Version 1 at 0x80300000.
>[    0.000000] 000: i2c_spi_info: control base addr = 0000000090000000, data base addr = 0000000090000040, IRQ 15 IOHUB revision 07
>[    0.000000] 000: IOAPIC[0]: apic_id 16, version 17, address 0xfec00000, GSI 0-23
>[    0.000000] 000: Processors: 8
>[    0.000000] 000: cpu to cpuid map: 0->0 1->1 2->2 3->3 4->4 5->5 6->6 7->7 
>[    0.000000] 000: MSI supported
>[    0.000000] 000: Full kernel command line: console=ttyS0,115200 console=tty0 hardreset root=UUID=651709cd-2659-4a98-813d-0875e572441f
>[    0.000000] 000: Base MAC address 98:a7:b0:04:b1:60
>[    0.000000] 000: printk: bootconsole [early-dump0] enabled
>[    0.000000] 000: ARCH: E2K NATIVE MACHINE TYPE: e8c2  IOHUB , ID 00e9, REVISION: 002, ISET #5 SERIAL # UNKNOWN
>[    0.000000] 000: Kernel image check sum: 973674001
>[    0.000000] 000: Booting native kernel without any virtualization support
>[    0.000000] 000: Zone ranges:
>[    0.000000] 000:   DMA      [mem 0x0000000000000000-0x00000000ffffffff]
>[    0.000000] 000:   Normal   [mem 0x0000000100000000-0x00000087ffffffff]
>[    0.000000] 000: Movable zone start for each node
>[    0.000000] 000: Early memory node ranges
>[    0.000000] 000:   node   0: [mem 0x0000000000000000-0x000000000009ffff]
>[    0.000000] 000:   node   0: [mem 0x00000000000c0000-0x000000001fffffff]
>[    0.000000] 000:   node   0: [mem 0x0000008020000000-0x00000087ffffffff]
>[    0.000000] 000: Zeroed struct page in unavailable ranges: 32 pages
>[    0.000000] 000: Initmem setup node 0 [mem 0x0000000000000000-0x00000087ffffffff]
>[    0.000000] 000:   (Node 0: pfn range [0x0-0x100000] reduced to [0x0-0x20000])
>[    0.000000] 000:   (Node 0: pfn range [0x100000-0x8800000] reduced to [0x8020000-0x8800000], real end 0x8800000)
>[    0.000000] 000: PM: Registered nosave memory: [mem 0x000a0000-0x000bffff]
>[    0.000000] 000: PM: Registered nosave memory: [mem 0x20000000-0x801fffffff]
>[    0.000000] 000: node0 kernel phys base: 0x8021400000
>[    0.000000] 000: DevTree: device tree size is 2411
>[    0.000000] 000: Memory wait type idle is not supported, turn OFF
>[    0.000000] 000: percpu: Embedded 28 pages/cpu s73816 r8192 d32680 u114688
>[    0.000000] 000: Built 1 zonelists, mobility grouping on.  Total pages: 8257504
>[    0.000000] 000: Policy zone: Normal
>[    0.000000] 000: Kernel command line: console=ttyS0,115200 console=tty0 hardreset root=UUID=651709cd-2659-4a98-813d-0875e572441f
>[    0.000000] 000: Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
>[    0.000000] 000: Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
>[    0.000000] 000: Sorting __ex_table...
>[    0.000000] 000: mem auto-init: stack:off, heap alloc:off, heap free:off
>[    0.000000] 000: MMU: Page Table entries old format V1 is used
>[    0.000000] 000: MMU: United Page Tables for kernel and user
>[    0.000000] 000: kernel and users page table virt base: 0xff8000000000
>[    0.000000] 000: kernel virt base: 0xe20000000000, kernel virt end: 0xe200038d32e0
>[    0.000000] 000: Kernel virt base: 0000d00000000000, last valid phaddr: 0000008800000000
>[    0.000000] 000: Memory total mapped pages number 0x8800000 : valid 0x7fffe0, invalid 0x8000020
>[    0.000000] 000: Memory: 705732K/33554304K available (38912K kernel code, 3897K rwdata, 4096K rodata, 2892K init, 7022K bss, 655992K reserved, 0K cma-reserved)
>[    0.000000] 000: random: get_random_u64 called from cache_random_seq_create+0x148/0x3d8 with crng_init=0
>[    0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>[    0.000000] 000: random: get_random_u32 called from shuffle_freelist+0x128/0x4b0 with crng_init=0
>[    0.000000] 000: ftrace: allocating 30768 entries in 121 pages
>[    0.000000] 000: rcu: Hierarchical RCU implementation.
>[    0.000000] 000: rcu: 	RCU event tracing is enabled.
>[    0.000000] 000: rcu: 	RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
>[    0.000000] 000: 	RCU CPU stall warnings suppressed (rcu_cpu_stall_suppress).
>[    0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
>[    0.000000] 000: rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>[    0.000000] 000: NR_IRQS: 1536, nr_irqs: 410, preallocated irqs: 0
>[    0.000000] 000: Node #0 IO LINK #0 is
>[    0.000000] 000:  IO HUB controller
>[    0.000000] 000:  ON
>[    0.000000] 000:  connected to
>[    0.000000] 000:  IO HUB controller
>[    0.000000] 000: 
>[    0.002000] 000: Console: colour VGA+ 80x25
>[    0.003000] 000: printk: console [tty0] enabled
>[    0.004000] 000: printk: bootconsole [early-dump0] disabled
>[    0.005000] 000: Zilog: console probe ...
>[    0.005000] 000: Zilog: console init port 0, control_reg = 0xe40000104040
>[    0.005000] 000: Zilog: console init port 1, control_reg = 0xe40000104042
>[    0.005000] 000:  found
>[    0.005000] 000: printk: console [ttyS0] enabled
>[    0.065000] 000: Calibrating delay using timer specific routine.. 3000.61 BogoMIPS (lpj=1500309)
>[    0.065000] 000: pid_max: default: 32768 minimum: 301
>[    0.065000] 000: LSM: Security Framework initializing
>[    0.065000] 000: Yama: becoming mindful.
>[    0.065000] 000: AltHa disabled.
>[    0.065000] 000: Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
>[    0.065000] 000: Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
>[    0.065000] 000: BSP APIC ID: 0
>[    0.067000] 000: Processor frequency 1499963022
>[    0.067000] 000: rcu: Hierarchical SRCU implementation.
>[    0.067000] 000: smp: Bringing up secondary CPUs ...
>[    0.077000] 000: smp: Brought up 1 node, 8 CPUs
>[    0.077000] 000: Total of 8 processors activated
>[    0.969000] 002: node 0 initialised, 8048145 pages in 892ms
>[    0.969000] 000: devtmpfs: initialized
>[    0.975000] 000: CF FILL depth: 16 quadro registers
>[    0.975000] 000: random: get_random_u32 called from rhashtable_init+0x568/0x7d8 with crng_init=0
>[    0.975000] 000: clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>[    0.975000] 000: futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
>[    0.976000] 000: NET: Registered protocol family 16
>[    0.976000] 000: audit: initializing netlink subsys (disabled)
>[    0.976000] 006: audit: type=2000 audit(0.976:1): state=initialized audit_enabled=0 res=1
>[    0.977000] 003: cpuidle: using governor ladder
>[    0.977000] 001: cpuidle: using governor menu
>

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Attachments on bug 42996: 10916 | 10917 | 10918 | 10919 | 10920 | 10921