--- wdt.h.orig	2016-02-15 14:34:03.536258149 +0300
+++ wdt.h	2016-02-15 14:54:42.965361255 +0300
@@ -196,14 +196,14 @@
     "wdr"                                   "\n\t" \
     : \
     : [ccp_reg]            "M" _SFR_MEM_ADDR(CCP),        \
-      [ioreg_cen_mask]     "r" CCP_IOREG_gc,              \
+      [ioreg_cen_mask]     "r" (CCP_IOREG_gc),            \
       [wdt_reg]            "M" _SFR_MEM_ADDR(WDT_CTRL),   \
       [wdt_enable_timeout] "r" (WDT_CEN_bm | WDT_ENABLE_bm | timeout), \
       [wdt_status_reg]     "M" _SFR_MEM_ADDR(WDT_STATUS), \
-      [wdt_syncbusy_bit]   "I" WDT_SYNCBUSY_bm,           \
-      [tmp]                "r" temp                       \
+      [wdt_syncbusy_bit]   "I" (WDT_SYNCBUSY_bm),         \
+      [tmp]                "r" (temp)                     \
     : "r0" \
-) \
+); \
 } while(0)
 
 #define wdt_disable() \
@@ -216,12 +216,13 @@
     "sts %[wdt_reg], %[wdt_disable]"    "\n\t" \
     : \
     : [ccp_reg]           "M" _SFR_MEM_ADDR(CCP),      \
-      [ioreg_cen_mask]    "r" CCP_IOREG_gc,            \
+      [ioreg_cen_mask]    "r" (CCP_IOREG_gc),          \
       [wdt_reg]           "M" _SFR_MEM_ADDR(WDT_CTRL), \
-      [tmp]               "r" temp,                    \
-      [disable_mask]      "M" ~WDT_ENABLE_bm,          \
+      [tmp]               "r" (temp),                  \
+      [disable_mask]      "M" (0xff ^ WDT_ENABLE_bm),  \
       [wdt_disable]       "r" (temp | WDT_CEN_bm)      \
-)
+); \
+} while(0)
 
 #elif defined(__AVR_AT90CAN32__) \
 || defined(__AVR_AT90CAN64__) \