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Lines 196-209
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| 196 |
"wdr" "\n\t" \ |
196 |
"wdr" "\n\t" \ |
| 197 |
: \ |
197 |
: \ |
| 198 |
: [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \ |
198 |
: [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \ |
| 199 |
[ioreg_cen_mask] "r" CCP_IOREG_gc, \ |
199 |
[ioreg_cen_mask] "r" (CCP_IOREG_gc), \ |
| 200 |
[wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \ |
200 |
[wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \ |
| 201 |
[wdt_enable_timeout] "r" (WDT_CEN_bm | WDT_ENABLE_bm | timeout), \ |
201 |
[wdt_enable_timeout] "r" (WDT_CEN_bm | WDT_ENABLE_bm | timeout), \ |
| 202 |
[wdt_status_reg] "M" _SFR_MEM_ADDR(WDT_STATUS), \ |
202 |
[wdt_status_reg] "M" _SFR_MEM_ADDR(WDT_STATUS), \ |
| 203 |
[wdt_syncbusy_bit] "I" WDT_SYNCBUSY_bm, \ |
203 |
[wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm), \ |
| 204 |
[tmp] "r" temp \ |
204 |
[tmp] "r" (temp) \ |
| 205 |
: "r0" \ |
205 |
: "r0" \ |
| 206 |
) \ |
206 |
); \ |
| 207 |
} while(0) |
207 |
} while(0) |
| 208 |
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208 |
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| 209 |
#define wdt_disable() \ |
209 |
#define wdt_disable() \ |
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Lines 216-227
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| 216 |
"sts %[wdt_reg], %[wdt_disable]" "\n\t" \ |
216 |
"sts %[wdt_reg], %[wdt_disable]" "\n\t" \ |
| 217 |
: \ |
217 |
: \ |
| 218 |
: [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \ |
218 |
: [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \ |
| 219 |
[ioreg_cen_mask] "r" CCP_IOREG_gc, \ |
219 |
[ioreg_cen_mask] "r" (CCP_IOREG_gc), \ |
| 220 |
[wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \ |
220 |
[wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \ |
| 221 |
[tmp] "r" temp, \ |
221 |
[tmp] "r" (temp), \ |
| 222 |
[disable_mask] "M" ~WDT_ENABLE_bm, \ |
222 |
[disable_mask] "M" (0xff ^ WDT_ENABLE_bm), \ |
| 223 |
[wdt_disable] "r" (temp | WDT_CEN_bm) \ |
223 |
[wdt_disable] "r" (temp | WDT_CEN_bm) \ |
| 224 |
) |
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); \ |
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225 |
} while(0) |
| 225 |
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226 |
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| 226 |
#elif defined(__AVR_AT90CAN32__) \ |
227 |
#elif defined(__AVR_AT90CAN32__) \ |
| 227 |
|| defined(__AVR_AT90CAN64__) \ |
228 |
|| defined(__AVR_AT90CAN64__) \ |
